diff --git a/sbus-to-ztex-gateware-migen/sbus-to-fpga.py b/sbus-to-ztex-gateware-migen/sbus-to-fpga.py
index 98e426d..57b0653 100644
--- a/sbus-to-ztex-gateware-migen/sbus-to-fpga.py
+++ b/sbus-to-ztex-gateware-migen/sbus-to-fpga.py
@@ -122,7 +122,7 @@ class SBusFPGA(SoCCore):
         self.submodules.sbus_slave = SBusFPGASlave(platform=self.platform,
                                                    prom=prom,
                                                    hold_reset=hold_reset,
-                                                   wishbone=wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width),
+                                                   wishbone=wishbone.Interface(data_width=self.bus.data_width),
                                                    chaser=self.leds)
 
         self.bus.add_master(name="SBusBridgeToWishbone", master=self.sbus_slave.wishbone)
diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_slave.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_slave.py
index 0c0a562..dfae0fb 100644
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_slave.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_slave.py
@@ -480,7 +480,7 @@ class SBusFPGASlave(Module):
                    )
         )
         wb_fsm.act("Write",
-                   self.wishbone.adr.eq(csr_data_w_addr),
+                   self.wishbone.adr.eq(csr_data_w_addr[2:32]),
                    self.wishbone.dat_w.eq(csr_data_w_data),
                    self.wishbone.we.eq(1),
                    self.wishbone.cyc.eq(1),