diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
index a5c140d..ab96820 100644
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
@@ -856,7 +856,6 @@ class SBusFPGABus(Module):
         self.submodules.wishbone_slave_buffering_fsm = wishbone_slave_buffering_fsm = FSM(reset_state="Reset")
         self.sync += led4.eq(self.master_read_buffer_start)
         wishbone_slave_buffering_fsm.act("Reset",
-                                         led1.eq(0),
                                          led2.eq(0),
                                          led3.eq(0),
                                          NextState("Idle")