diff --git a/sbus-to-ztex-gateware/rom.vhd b/sbus-to-ztex-gateware/rom.vhd index acdb3b8..57cb43c 100644 --- a/sbus-to-ztex-gateware/rom.vhd +++ b/sbus-to-ztex-gateware/rom.vhd @@ -31,11 +31,11 @@ end Prom; architecture arch of Prom is type rom_type is array (0 to addr_width-1) of std_logic_vector(data_width-1 downto 0); - + signal Prom_ROM : rom_type := ( -- copy/paste the ROM content here -- -"11110001000010000111011110000110", -- 1 -"00000000000000000000000111001100", -- 2 +"11110001000010001010010100101001", -- 1 +"00000000000000000000001001111010", -- 2 "00010010000100010101001001000100", -- 3 "01001111010011000010110001100011", -- 4 "01110010011110010111000001110100", -- 5 @@ -148,7 +148,51 @@ architecture arch of Prom is "00001000000010111011011100010010", -- 112 "00000111011011010110000101110000", -- 113 "00101101011011110111010101110100", -- 114 -"00000010000010011100001000000000", -- 115 +"00000010000010011100001000000001", -- 115 +"00100111000000010001111100010010", -- 116 +"00001011010100100100010001001111", -- 117 +"01001100001011000111001101100100", -- 118 +"01100011011000010111001001100100", -- 119 +"00000010000000010000000100000010", -- 120 +"00010000000000000000001100000000", -- 121 +"00000000000111100000000100000011", -- 122 +"00010000000000000000000000000001", -- 123 +"00000000000000010001011000010000", -- 124 +"00000000000000000000000000000100", -- 125 +"00000001000100010001001000010001", -- 126 +"01110011011011000110000101110110", -- 127 +"01100101001011010110001001110101", -- 128 +"01110010011100110111010000101101", -- 129 +"01110011011010010111101001100101", -- 130 +"01110011000000010001000000010000", -- 131 +"00000000000000000000000000000100", -- 132 +"00000001000100010001001000001011", -- 133 +"01100010011101010111001001110011", -- 134 +"01110100001011010111001101101001", -- 135 +"01111010011001010111001100000001", -- 136 +"00010000000000010000001010110110", -- 137 +"00001111011011010111100100101101", -- 138 +"01110011011000100111010101110011", -- 139 +"00101101011000010110010001100100", -- 140 +"01110010011001010111001101110011", -- 141 +"00001000000011001011101000000001", -- 142 +"00000011101101100000110101101101", -- 143 +"01111001001011010111001101100010", -- 144 +"01110101011100110010110101110011", -- 145 +"01110000011000010110001101100101", -- 146 +"00001000000011011011101010110110", -- 147 +"00000110011011010110000101110000", -- 148 +"00101101011010010110111000001000", -- 149 +"00001110101101110001001000000110", -- 150 +"01101101011000010111000000101101", -- 151 +"01101001011011100000001000001001", -- 152 +"11000010101101100000011101101101", -- 153 +"01100001011100000010110101101111", -- 154 +"01110101011101000000100000001111", -- 155 +"10110111000100100000011101101101", -- 156 +"01100001011100000010110101101111", -- 157 +"01110101011101000000001000001001", -- 158 +"11000010000000000000000000000000", -- 159 -- ROM then filled with zero others => (others => '0')); begin diff --git a/sbus-to-ztex-gateware/sbus-to-ztex.xdc b/sbus-to-ztex-gateware/sbus-to-ztex.xdc index 62c11c5..bc0afd9 100644 --- a/sbus-to-ztex-gateware/sbus-to-ztex.xdc +++ b/sbus-to-ztex-gateware/sbus-to-ztex.xdc @@ -380,12 +380,16 @@ set_property IOSTANDARD LVTTL [get_ports {LED1}] #set_property PACKAGE_PIN V6 [get_ports {SD_D3}] #set_property IOSTANDARD LVTTL [get_ports {SD_D3}] +set_property PACKAGE_PIN V6 [get_ports {SD_nCS}] +set_property IOSTANDARD LVTTL [get_ports {SD_nCS}] set_property PACKAGE_PIN U6 [get_ports {LED2}] set_property IOSTANDARD LVTTL [get_ports {LED2}] #set_property PACKAGE_PIN V5 [get_ports {SD_D0}] #set_property IOSTANDARD LVTTL [get_ports {SD_D0}] +set_property PACKAGE_PIN V5 [get_ports {SD_DI}] +set_property IOSTANDARD LVTTL [get_ports {SD_DI}] set_property PACKAGE_PIN T8 [get_ports {LED3}] set_property IOSTANDARD LVTTL [get_ports {LED3}] @@ -395,9 +399,13 @@ set_property IOSTANDARD LVTTL [get_ports {LED3}] #set_property PACKAGE_PIN R8 [get_ports {SD_CLK}] #set_property IOSTANDARD LVTTL [get_ports {SD_CLK}] +set_property PACKAGE_PIN R8 [get_ports {SD_CLK}] +set_property IOSTANDARD LVTTL [get_ports {SD_CLK}] #set_property PACKAGE_PIN T5 [get_ports {SD_CMD}] #set_property IOSTANDARD LVTTL [get_ports {SD_CMD}] +set_property PACKAGE_PIN T5 [get_ports {SD_DO}] +set_property IOSTANDARD LVTTL [get_ports {SD_DO}] set_property PACKAGE_PIN R7 [get_ports {SBUS_3V3_SIZ[0]}] set_property IOSTANDARD LVTTL [get_ports {SBUS_3V3_SIZ[0]}] diff --git a/sbus-to-ztex-gateware/sbus_fsm.vhd b/sbus-to-ztex-gateware/sbus_fsm.vhd index 28e50c5..6419950 100644 --- a/sbus-to-ztex-gateware/sbus_fsm.vhd +++ b/sbus-to-ztex-gateware/sbus_fsm.vhd @@ -13,6 +13,8 @@ USE work.LedHandlerPkg.all; USE work.PromPkg.all; use work.mastrovito_V2_multiplier_parameters.all; +library XESS; + ENTITY SBusFSM is PORT ( fxclk_in: IN std_logic; -- 48 MHz FX2 clock @@ -48,7 +50,12 @@ ENTITY SBusFSM is LED6 : OUT std_logic := '0'; LED7 : OUT std_logic := '0'; -- UART - TX : OUT std_logic := 'Z' + TX : OUT std_logic := 'Z'; + -- SD (SPI) + SD_nCS : OUT std_logic; + SD_DI : IN std_logic; + SD_DO : OUT std_logic; + SD_CLK : OUT std_logic ); -- SIZ[2..0] is positive true CONSTANT SIZ_WORD : std_logic_vector(2 downto 0):= "000"; @@ -79,6 +86,7 @@ ENTITY SBusFSM is CONSTANT ROM_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000000"; CONSTANT REG_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000001"; CONSTANT REGTRNG_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000010"; + CONSTANT REGSD_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000011"; CONSTANT REG_INDEX_LED : integer := 0; @@ -140,6 +148,8 @@ ENTITY SBusFSM is constant AES128_CTRL_DEC_IDX : integer := 25; CONSTANT REG_INDEX_TRNG_DATA : integer := 0; + + CONSTANT REG_INDEX_SD_STATUS : integer := 0; -- OFFSET to REGS; (15 downto 0) so 16 bits CONSTANT OFFSET_LENGTH : integer := 16; @@ -303,6 +313,13 @@ ARCHITECTURE RTL OF SBusFSM IS signal fifo_fromstrng_full : STD_LOGIC; signal fifo_fromstrng_empty : STD_LOGIC; + signal fifo_fromsdcard_din : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fifo_fromsdcard_wr_en : STD_LOGIC; + signal fifo_fromsdcard_rd_en : STD_LOGIC; + signal fifo_fromsdcard_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fifo_fromsdcard_full : STD_LOGIC; + signal fifo_fromsdcard_empty : STD_LOGIC; + -- SIGNAL LIFE_COUNTER25 : natural range 0 to 25000000 := 300; SIGNAL RES_COUNTER : natural range 0 to 4 := 4; @@ -316,7 +333,8 @@ ARCHITECTURE RTL OF SBusFSM IS -- bank of registers (256 bytes) for cryptoengine (and led) -- 0-64: 16 for controls (6 used) 16 registers for GCM (12 used), 16 unused, 16 for AES -- 64-127: are remmaped from TRNG space - type REGISTERS_TYPE is array(0 to 64) of std_logic_vector(31 downto 0); + -- 18-191: are remmaped from SDCARD space + type REGISTERS_TYPE is array(0 to 128) of std_logic_vector(31 downto 0); SIGNAL REGISTERS : REGISTERS_TYPE; pure function REG_OFFSET_IS_GCMINPUT(value : in std_logic_vector(OFFSET_HIGH downto OFFSET_LOW)) return boolean is @@ -414,6 +432,11 @@ ARCHITECTURE RTL OF SBusFSM IS begin return true; end function; + + pure function REG_OFFSET_IS_ANYSDREAD(value : in std_logic_vector(OFFSET_HIGH downto OFFSET_LOW)) return boolean is + begin + return true; + end function; pure function SIZ_IS_WORD(value : in std_logic_vector(2 downto 0)) return boolean is begin @@ -557,6 +580,18 @@ ARCHITECTURE RTL OF SBusFSM IS empty : out STD_LOGIC ); end component; + component fifo_generator_from_sdcard is + Port ( + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 31 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC + ); + end component; component uart_tx is generic ( @@ -616,6 +651,21 @@ ARCHITECTURE RTL OF SBusFSM IS output_fifo_wr_en : out std_logic ); end component trivium_wrapper; + + component xess_sdcard_wrapper is + port ( + xess_sdcard_wrapper_rst : in std_logic; + xess_sdcard_wrapper_clk : in std_logic; + output_fifo_in : out std_logic_vector(31 downto 0); + output_fifo_full : in std_logic; + output_fifo_wr_en : out std_logic; + -- pins + cs_bo : out std_logic; + sclk_o : out std_logic; + mosi_o : out std_logic; + miso_i : in std_logic + ); + end component xess_sdcard_wrapper; PROCEDURE SBus_Set_Default( -- signal SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0); @@ -698,6 +748,9 @@ BEGIN label_fifo_fromstrng: fifo_generator_from_strng port map(wr_clk => aes_clk_out, rd_clk => SBUS_3V3_CLK, din => fifo_fromstrng_din, wr_en => fifo_fromstrng_wr_en, rd_en => fifo_fromstrng_rd_en, dout => fifo_fromstrng_dout, full => fifo_fromstrng_full, empty => fifo_fromstrng_empty); + label_fifo_fromsdcard: fifo_generator_from_sdcard port map(wr_clk => aes_clk_out, rd_clk => SBUS_3V3_CLK, + din => fifo_fromsdcard_din, wr_en => fifo_fromsdcard_wr_en, rd_en => fifo_fromsdcard_rd_en, + dout => fifo_fromsdcard_dout, full => fifo_fromsdcard_full, empty => fifo_fromsdcard_empty); label_aes_wrapper: aes_wrapper port map( aes_wrapper_rst => aes_wrapper_rst, aes_wrapper_clk => aes_clk_out, @@ -723,6 +776,19 @@ BEGIN output_fifo_full => fifo_fromstrng_full, output_fifo_wr_en => fifo_fromstrng_wr_en ); + + label_xess_sdcard_wrapper: xess_sdcard_wrapper port map ( + xess_sdcard_wrapper_rst => aes_wrapper_rst, + xess_sdcard_wrapper_clk => aes_clk_out, + output_fifo_in => fifo_fromsdcard_din, + output_fifo_full => fifo_fromsdcard_full, + output_fifo_wr_en => fifo_fromsdcard_wr_en, + -- pins + cs_bo => SD_nCS, + sclk_o => SD_CLK, + mosi_o => SD_DO, + miso_i => SD_DI + ); -- label_clk_wiz: clk_wiz_0 port map(clk_out1 => uart_clk, clk_in1 => fxclk_in); label_aes_clk_wiz: clk_wiz_aes port map(clk_out1 => aes_clk_out, clk_in1 => fxclk_in); @@ -751,7 +817,7 @@ BEGIN variable dma_write : boolean := false; variable dma_ctrl_idx : integer range 0 to 7; variable dma_addr_idx : integer range 0 to 7; - variable reg_bank : integer range 0 to 1 := 0; + variable reg_bank : integer range 0 to 2 := 0; BEGIN IF (SBUS_3V3_RSTs = '0') THEN State <= SBus_Start; @@ -807,6 +873,15 @@ BEGIN BUF_ERRs_O <= '1'; -- no late error reg_bank := 1; State <= SBus_Slave_Ack_Read_Reg_Burst; + ELSIF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = REGSD_ADDR_PFX) AND REG_OFFSET_IS_ANYSDREAD(last_pa(OFFSET_HIGH downto OFFSET_LOW)) + -- and (fifo_fromstrng_empty = '0') + ) then + -- 32 bits read from aligned memory IN REG TRNG space ------------------------------------ + -- if FIFO is empty, will fallback to returning an error... + BUF_ACKs_O <= ACK_WORD; + BUF_ERRs_O <= '1'; -- no late error + reg_bank := 2; + State <= SBus_Slave_Ack_Read_Reg_Burst; ELSE BUF_ACKs_O <= ACK_ERR; BUF_ERRs_O <= '1'; -- no late error @@ -1443,7 +1518,15 @@ BEGIN WHEN others => -- do nothing + END CASE; --TRNG self-un-fulling FIFO + + CASE fifo_fromsdcard_empty IS + WHEN '0' => + fifo_fromsdcard_rd_en <= '1'; -- remove one word from FIFO + REGISTERS(128 + REG_INDEX_SD_STATUS) <= fifo_fromsdcard_dout; + WHEN others => + -- do nothing END CASE; --TRNG self-emptying FIFO END IF; diff --git a/sbus-to-ztex/prom.fc b/sbus-to-ztex/prom.fc index fe378c7..9e6fab7 100644 Binary files a/sbus-to-ztex/prom.fc and b/sbus-to-ztex/prom.fc differ diff --git a/sbus-to-ztex/prom.forth b/sbus-to-ztex/prom.forth index dd19e10..c67488f 100644 --- a/sbus-to-ztex/prom.forth +++ b/sbus-to-ztex/prom.forth @@ -47,6 +47,24 @@ my-space constant my-sbus-space : map-in ( adr space size -- virt ) " map-in" $call-parent ; : map-out ( virt size -- ) " map-out" $call-parent ; -\ external + +\ OpenBIOS tokenizer won't accept finish-device without new-device +\ Cheat by using the tokenizer so we can do OpenBoot 2.x siblings +tokenizer[ 01 emit-byte 27 emit-byte 01 emit-byte 1f emit-byte ]tokenizer + +\ Absolute minimal stuff; name & registers def. +" RDOL,sdcard" name +my-address h# 30000 + my-space h# 100 reg +\ we don't support ET or anything non-32bits +h# 04 xdrint " slave-burst-sizes" attribute +h# 04 xdrint " burst-sizes" attribute + +headers + +my-address constant my-sbus-address +my-space constant my-sbus-space + +: map-in ( adr space size -- virt ) " map-in" $call-parent ; +: map-out ( virt size -- ) " map-out" $call-parent ; end0