diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c index 3aa313c..c99832b 100644 --- a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_sdram.c @@ -119,7 +119,6 @@ struct sbusfpga_sdram_rwpg { u_int32_t last_blk; u_int32_t last_dma; u_int32_t dma_wrdone; - u_int32_t vdma_err; }; #define SBUSFPGA_READ_PG _IOWR('X', 0, struct sbusfpga_sdram_rwpg) #define SBUSFPGA_WRITE_PG _IOWR('X', 1, struct sbusfpga_sdram_rwpg) @@ -609,7 +608,6 @@ sbusfpga_sdram_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l pg->last_blk = exchange_with_mem_last_blk_read(sc); pg->last_dma = exchange_with_mem_last_dma_read(sc); pg->dma_wrdone = exchange_with_mem_dma_wrdone_read(sc); - pg->vdma_err = exchange_with_mem_sbus_master_error_virtual_read(sc); if (err != 0) err = EIO; goto done; @@ -624,7 +622,6 @@ sbusfpga_sdram_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l pg->last_blk = exchange_with_mem_last_blk_read(sc); pg->last_dma = exchange_with_mem_last_dma_read(sc); pg->dma_wrdone = exchange_with_mem_dma_wrdone_read(sc); - pg->vdma_err = exchange_with_mem_sbus_master_error_virtual_read(sc); if (err != 0) err = EIO; goto done; diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.c b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.c new file mode 100644 index 0000000..00be73e --- /dev/null +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.c @@ -0,0 +1,223 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 Romain Dolbeau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#include + +#include + +int sbusfpga_stat_print(void *, const char *); +int sbusfpga_stat_match(device_t, cfdata_t, void *); +void sbusfpga_stat_attach(device_t, device_t, void *); + +CFATTACH_DECL_NEW(sbusfpga_stat, sizeof(struct sbusfpga_sbus_bus_stat_softc), + sbusfpga_stat_match, sbusfpga_stat_attach, NULL, NULL); + +dev_type_open(sbusfpga_stat_open); +dev_type_close(sbusfpga_stat_close); + + + +const struct cdevsw sbusfpga_stat_cdevsw = { + .d_open = sbusfpga_stat_open, + .d_close = sbusfpga_stat_close, + .d_read = noread, + .d_write = nowrite, + .d_ioctl = noioctl, + .d_stop = nostop, + .d_tty = notty, + .d_poll = nopoll, + .d_mmap = nommap, + .d_kqfilter = nokqfilter, + .d_discard = nodiscard, + .d_flag = 0 +}; + +extern struct cfdriver sbusfpga_stat_cd; +int +sbusfpga_stat_open(dev_t dev, int flags, int mode, struct lwp *l) +{ + return (0); +} + +int +sbusfpga_stat_close(dev_t dev, int flags, int mode, struct lwp *l) +{ + return (0); +} + +int +sbusfpga_stat_print(void *aux, const char *busname) +{ + + sbus_print(aux, busname); + return (UNCONF); +} + +int +sbusfpga_stat_match(device_t parent, cfdata_t cf, void *aux) +{ + struct sbus_attach_args *sa = (struct sbus_attach_args *)aux; + + return (strcmp("RDOL,sbusstat", sa->sa_name) == 0); +} + +#define CONFIG_CSR_DATA_WIDTH 32 +// define CSR_LEDS_BASE & others to avoid defining the CSRs of HW we don't handle +#define CSR_LEDS_BASE +#define CSR_CURVE25519ENGINE_BASE +#define CSR_DDRPHY_BASE +#define CSR_EXCHANGE_WITH_MEM_BASE +// #define CSR_SBUS_BUS_STAT_BASE +#define CSR_SDRAM_BASE +#define CSR_SDBLOCK2MEM_BASE +#define CSR_SDCORE_BASE +#define CSR_SDIRQ_BASE +#define CSR_SDMEM2BLOCK_BASE +#define CSR_SDPHY_BASE +#define CSR_TRNG_BASE +#include "dev/sbus/litex_csr.h" +#undef CSR_LEDS_BASE +#undef CSR_CURVE25519ENGINE_BASE +#undef CSR_DDRPHY_BASE +#undef CSR_EXCHANGE_WITH_MEM_BASE +// #undef CSR_SBUS_BUS_STAT_BASE +#undef CSR_SDRAM_BASE +#undef CSR_SDBLOCK2MEM_BASE +#undef CSR_SDCORE_BASE +#undef CSR_SDIRQ_BASE +#undef CSR_SDMEM2BLOCK_BASE +#undef CSR_SDPHY_BASE +//#undef CSR_TRNG_BASE + + +static void sbusfpga_stat_display(void *); + +/* + * Attach all the sub-devices we can find + */ +void +sbusfpga_stat_attach(device_t parent, device_t self, void *aux) +{ + struct sbus_attach_args *sa = aux; + struct sbusfpga_sbus_bus_stat_softc *sc = device_private(self); + struct sbus_softc *sbsc = device_private(parent); + int node; + int sbusburst; + + sc->sc_bustag = sa->sa_bustag; + sc->sc_dev = self; + + if (sbus_bus_map(sc->sc_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, + BUS_SPACE_MAP_LINEAR, &sc->sc_bhregs_sbus_bus_stat) != 0) { + aprint_error(": cannot map registers\n"); + return; + } + + sc->sc_bufsiz = sa->sa_size; + + node = sc->sc_node = sa->sa_node; + + /* + * Get transfer burst size from PROM + */ + sbusburst = sbsc->sc_burst; + if (sbusburst == 0) + sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ + + sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); + if (sc->sc_burst == -1) + /* take SBus burst sizes */ + sc->sc_burst = sbusburst; + + /* Clamp at parent's burst sizes */ + sc->sc_burst &= sbusburst; + + aprint_normal("\n"); + aprint_normal_dev(self, "nid 0x%x, bustag %p, burst 0x%x (parent 0x%0x)\n", + sc->sc_node, + sc->sc_bustag, + sc->sc_burst, + sbsc->sc_burst); + + sc->sc_delay = 5 * hz; // five seconds + + callout_init(&sc->sc_display, CALLOUT_MPSAFE); + callout_setfunc(&sc->sc_display, sbusfpga_stat_display, sc); + callout_schedule(&sc->sc_display, sc->sc_delay); +} + +static void sbusfpga_stat_display(void *args) { + struct sbusfpga_sbus_bus_stat_softc *sc = args; + unsigned int c = sbus_bus_stat_stat_cycle_counter_read(sc), c2; + int count; + sbus_bus_stat_stat_ctrl_write(sc, 1); + delay(1); + count = 0; + while (count < 10 && ((c2 = sbus_bus_stat_stat_cycle_counter_read(sc)) == c)) { + count ++; + delay(1); + } + if ((c2 == c) || (c2 == 0)){ + device_printf(sc->sc_dev, "Statistics didn't update\n"); + } else { + device_printf(sc->sc_dev, "%u: slave %u %u %u %u\n", + c2, + sbus_bus_stat_stat_slave_start_counter_read(sc), + sbus_bus_stat_stat_slave_done_counter_read(sc), + sbus_bus_stat_stat_slave_rerun_counter_read(sc), + sbus_bus_stat_stat_slave_early_error_counter_read(sc)); + device_printf(sc->sc_dev, "%u: master %u %u %u %u (0x%08x)\n", + c2, + sbus_bus_stat_stat_master_start_counter_read(sc), + sbus_bus_stat_stat_master_done_counter_read(sc), + sbus_bus_stat_stat_master_error_counter_read(sc), + sbus_bus_stat_stat_master_rerun_counter_read(sc), + sbus_bus_stat_sbus_master_error_virtual_read(sc)); + } + sbus_bus_stat_stat_ctrl_write(sc, 0); + callout_schedule(&sc->sc_display, sc->sc_delay); +} diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.h b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.h new file mode 100644 index 0000000..2ab4c48 --- /dev/null +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/sbusfpga_stat.h @@ -0,0 +1,44 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 Romain Dolbeau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _SBUSFPGA_STAT_H_ +#define _SBUSFPGA_STAT_H_ + +struct sbusfpga_sbus_bus_stat_softc { + device_t sc_dev; /* us as a device */ + u_int sc_rev; /* revision */ + int sc_node; /* PROM node ID */ + int sc_burst; /* DVMA burst size in effect */ + bus_space_tag_t sc_bustag; /* bus tag */ + bus_space_handle_t sc_bhregs_sbus_bus_stat; /* bus handle */ + int sc_bufsiz; /* Size of buffer */ + callout_t sc_display; + int sc_delay; +}; + +#endif /* _SBUSFPGA_STAT_H_ */ diff --git a/sbus-to-ztex-gateware-migen/netbsd_csr.h b/sbus-to-ztex-gateware-migen/netbsd_csr.h index f6fd470..4f44e70 100644 --- a/sbus-to-ztex-gateware-migen/netbsd_csr.h +++ b/sbus-to-ztex-gateware-migen/netbsd_csr.h @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-08-21 07:21:33 +// Auto-generated by Migen (3ffd64c) & LiteX (8a644c90) on 2021-08-21 08:42:06 //-------------------------------------------------------------------------------- #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H @@ -729,12 +729,7 @@ static inline uint32_t exchange_with_mem_dma_status_has_rd_data_read(struct sbus static inline uint32_t exchange_with_mem_wr_tosdram_read(struct sbusfpga_exchange_with_mem_softc *sc) { return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x2cL); } -#define CSR_EXCHANGE_WITH_MEM_SBUS_MASTER_ERROR_VIRTUAL_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x30L) -#define CSR_EXCHANGE_WITH_MEM_SBUS_MASTER_ERROR_VIRTUAL_SIZE 1 -static inline uint32_t exchange_with_mem_sbus_master_error_virtual_read(struct sbusfpga_exchange_with_mem_softc *sc) { - return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_exchange_with_mem, 0x30L); -} -#define CSR_EXCHANGE_WITH_MEM_CHECKSUM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x34L) +#define CSR_EXCHANGE_WITH_MEM_CHECKSUM_ADDR (CSR_EXCHANGE_WITH_MEM_BASE + 0x30L) #define CSR_EXCHANGE_WITH_MEM_CHECKSUM_SIZE 8 #endif // CSR_EXCHANGE_WITH_MEM_BASE @@ -788,9 +783,9 @@ static inline uint32_t sbus_bus_stat_stat_slave_start_counter_read(struct sbusfp static inline uint32_t sbus_bus_stat_stat_slave_done_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x10L); } -#define CSR_SBUS_BUS_STAT_STAT_SLAVE_ERROR_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x14L) -#define CSR_SBUS_BUS_STAT_STAT_SLAVE_ERROR_COUNTER_SIZE 1 -static inline uint32_t sbus_bus_stat_stat_slave_error_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_RERUN_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x14L) +#define CSR_SBUS_BUS_STAT_STAT_SLAVE_RERUN_COUNTER_SIZE 1 +static inline uint32_t sbus_bus_stat_stat_slave_rerun_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x14L); } #define CSR_SBUS_BUS_STAT_STAT_SLAVE_EARLY_ERROR_COUNTER_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x18L) @@ -818,6 +813,11 @@ static inline uint32_t sbus_bus_stat_stat_master_error_counter_read(struct sbusf static inline uint32_t sbus_bus_stat_stat_master_rerun_counter_read(struct sbusfpga_sbus_bus_stat_softc *sc) { return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x28L); } +#define CSR_SBUS_BUS_STAT_SBUS_MASTER_ERROR_VIRTUAL_ADDR (CSR_SBUS_BUS_STAT_BASE + 0x2cL) +#define CSR_SBUS_BUS_STAT_SBUS_MASTER_ERROR_VIRTUAL_SIZE 1 +static inline uint32_t sbus_bus_stat_sbus_master_error_virtual_read(struct sbusfpga_sbus_bus_stat_softc *sc) { + return bus_space_read_4(sc->sc_bustag, sc->sc_bhregs_sbus_bus_stat, 0x2cL); +} #endif // CSR_SBUS_BUS_STAT_BASE /* sdram */ diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py index e2b29c7..61d3eac 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_blk_dma.py @@ -23,10 +23,10 @@ class ExchangeWithMem(Module, AutoCSR): data_width_bits = burst_size * 32 blk_addr_width = 32 - log2_int(data_width) # 27 for burst_size == 8 - assert(len(self.dram_dma_writer.sink.data == data_width_bits)) - assert(len(self.dram_dma_reader.source.data == data_width_bits)) - assert(len(self.dram_dma_writer.sink.address == blk_addr_width)) - assert(len(self.dram_dma_reader.sink.address == blk_addr_width)) + assert(len(self.dram_dma_writer.sink.data) == data_width_bits) + assert(len(self.dram_dma_reader.source.data) == data_width_bits) + assert(len(self.dram_dma_writer.sink.address) == blk_addr_width) + assert(len(self.dram_dma_reader.sink.address) == blk_addr_width) #self.wishbone_r_master = wishbone.Interface(data_width=data_width_bits) #self.wishbone_w_master = wishbone.Interface(data_width=data_width_bits) @@ -77,8 +77,6 @@ class ExchangeWithMem(Module, AutoCSR): CSRField("has_rd_data", 1, description = "Data available to write to SBus"), ]) self.wr_tosdram = CSRStatus(32, description = "Last address written to SDRAM") - - self.sbus_master_error_virtual = CSRStatus(32, description = "Virtual address that failed translation phase") if (do_checksum): self.checksum = CSRStorage(data_width_bits, write_from_dev=True, description = "checksum (XOR)"); diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index 793c452..8b92f7f 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -35,6 +35,7 @@ ENGINE_ADDR_PFXB = Signal(12, reset = 0x00b) wishbone_default_timeout = 120 ## must be > sbus_default_timeout sbus_default_timeout = 100 ## must be below 127 as we can wait twice on it inside the 255 cycles +sbus_default_master_throttle = 3 def siz_is_word(siz): return (SIZ_WORD == siz) | (SIZ_BURST2 == siz) | (SIZ_BURST4 == siz) | (SIZ_BURST8 == siz) | (SIZ_BURST16 == siz) @@ -295,7 +296,7 @@ class SBusFPGABus(Module): wishbone_slave_timeout = Signal(log2_int(wishbone_default_timeout, False)) sbus_slave_timeout = Signal(log2_int(sbus_default_timeout, False)) - sbus_master_throttle = Signal(2) + sbus_master_throttle = Signal(log2_int(sbus_default_master_throttle, False)) #self.submodules.led_display = LedDisplay(platform.request_all("user_led")) @@ -382,20 +383,6 @@ class SBusFPGABus(Module): # slave_fsm.ongoing("Slave_Ack_Reg_Write_HWord_Wait_For_Wishbone") | # slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte") | # slave_fsm.ongoing("Slave_Ack_Reg_Write_Byte_Wait_For_Wishbone")) - - master_error_seen = Signal(4, reset = 0) - self.sync += platform.request("user_led", 0).eq(master_error_seen[0:1]) - self.sync += platform.request("user_led", 1).eq(master_error_seen[1:2]) - self.sync += platform.request("user_led", 2).eq(master_error_seen[2:3]) - self.sync += platform.request("user_led", 3).eq(master_error_seen[3:4]) - master_error_details = Signal(4, reset = 0) - self.sync += platform.request("user_led", 4).eq(master_error_details[0:1]) - self.sync += platform.request("user_led", 5).eq(master_error_details[1:2]) - self.sync += platform.request("user_led", 6).eq(master_error_details[2:3]) - self.sync += platform.request("user_led", 7).eq(master_error_details[3:4]) - - self.sbus_master_last_virtual = Signal(32) # last VDMA address put on the bus in master mode - self.sbus_master_error_virtual = Signal(32) # this gets exported to a Wishbone CSR in exchange_with_mem #self.sync += platform.request("user_led", 5).eq(~slave_fsm.ongoing("Idle")) #self.sync += platform.request("user_led", 6).eq(master_data_src_tosbus_fifo) @@ -411,6 +398,9 @@ class SBusFPGABus(Module): stat_master_error_counter = Signal(32) stat_master_rerun_counter = Signal(32) + sbus_master_last_virtual = Signal(32) # last VDMA address put on the bus in master mode + sbus_master_error_virtual = Signal(32) + slave_fsm.act("Reset", #NextValue(self.led_display.value, 0x0000000000), NextValue(sbus_oe_data, 0), @@ -711,43 +701,43 @@ class SBusFPGABus(Module): NextValue(master_size, SIZ_WORD), NextValue(SBUS_3V3_SIZ_o, SIZ_WORD), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), ], 0x1: [NextValue(master_idx, 3), NextValue(master_size, SIZ_BYTE), NextValue(SBUS_3V3_SIZ_o, SIZ_BYTE), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), ], 0x2: [NextValue(master_idx, 2), NextValue(master_size, SIZ_BYTE), NextValue(SBUS_3V3_SIZ_o, SIZ_BYTE), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 1), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 1), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 1), self.wishbone_slave.adr)), ], 0x4: [NextValue(master_idx, 1), NextValue(master_size, SIZ_BYTE), NextValue(SBUS_3V3_SIZ_o, SIZ_BYTE), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), ], 0x8: [NextValue(master_idx, 0), NextValue(master_size, SIZ_BYTE), NextValue(SBUS_3V3_SIZ_o, SIZ_BYTE), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 3), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 3), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 3), self.wishbone_slave.adr)), ], 0x3: [NextValue(master_idx, 2), NextValue(master_size, SIZ_HWORD), NextValue(SBUS_3V3_SIZ_o, SIZ_HWORD), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 0), self.wishbone_slave.adr)), ], 0xc: [NextValue(master_idx, 0), NextValue(master_size, SIZ_HWORD), NextValue(SBUS_3V3_SIZ_o, SIZ_HWORD), NextValue(SBUS_3V3_D_o, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), + NextValue(sbus_master_last_virtual, Cat(Signal(2, reset = 2), self.wishbone_slave.adr)), ], "default":[NextValue(burst_counter, 0), # FIXME if it happens! NextValue(burst_limit_m1, 0), ## only single word for now @@ -780,7 +770,7 @@ class SBusFPGABus(Module): NextValue(burst_counter, 0), NextValue(burst_limit_m1, 3), ## only quadword word for now NextValue(SBUS_3V3_D_o, Cat(Signal(4, reset = 0), self.master_read_buffer_addr)), - NextValue(self.sbus_master_last_virtual, Cat(Signal(4, reset = 0), self.master_read_buffer_addr)), + NextValue(sbus_master_last_virtual, Cat(Signal(4, reset = 0), self.master_read_buffer_addr)), NextValue(SBUS_3V3_PPRD_o, 1), NextValue(SBUS_3V3_SIZ_o, SIZ_BURST4), NextValue(master_we, 0), @@ -802,7 +792,7 @@ class SBusFPGABus(Module): NextValue(burst_counter, 0), NextValue(burst_limit_m1, burst_size - 1), NextValue(SBUS_3V3_D_o, self.tosbus_fifo.dout[0:32]), - NextValue(self.sbus_master_last_virtual, self.tosbus_fifo.dout[0:32]), + NextValue(sbus_master_last_virtual, self.tosbus_fifo.dout[0:32]), NextValue(master_addr, self.tosbus_fifo.dout[2:32]), NextValue(master_data, self.tosbus_fifo.dout[32:64]), NextValue(fifo_buffer, self.tosbus_fifo.dout[32:]), @@ -838,7 +828,7 @@ class SBusFPGABus(Module): NextValue(burst_counter, 0), NextValue(burst_limit_m1, burst_size - 1), NextValue(SBUS_3V3_D_o, self.fromsbus_req_fifo.dout[blk_addr_width:blk_addr_width+32]), - NextValue(self.sbus_master_last_virtual, self.fromsbus_req_fifo.dout[blk_addr_width:blk_addr_width+32]), + NextValue(sbus_master_last_virtual, self.fromsbus_req_fifo.dout[blk_addr_width:blk_addr_width+32]), NextValue(fifo_blk_addr, self.fromsbus_req_fifo.dout[0:blk_addr_width]), NextValue(master_data_src_fromsbus_fifo, 1), self.fromsbus_req_fifo.re.eq(1), @@ -1274,8 +1264,8 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(master_error_seen, 1), NextValue(stat_master_error_counter, stat_master_error_counter + 1), + NextValue(sbus_master_error_virtual, sbus_master_last_virtual), NextState("Idle")], ACK_RERUN: ### dunno how to handle that yet, [If(~master_data_src_tosbus_fifo & ~master_data_src_fromsbus_fifo, @@ -1333,10 +1323,8 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(master_error_seen, 8), - NextValue(master_error_details, burst_counter), NextValue(stat_master_error_counter, stat_master_error_counter + 1), - NextValue(self.sbus_master_error_virtual, self.sbus_master_last_virtual), + NextValue(sbus_master_error_virtual, sbus_master_last_virtual), NextState("Idle") ], "default": ## other ### burst not handled @@ -1347,9 +1335,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(master_error_seen, 4), NextValue(stat_master_error_counter, stat_master_error_counter + 1), - NextValue(master_error_details, Cat(SBUS_3V3_ACKs_i, Signal(1, reset = 0))), NextState("Idle") ], }) @@ -1396,11 +1382,18 @@ class SBusFPGABus(Module): NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle") ], + ACK_ERR: + [NextValue(sbus_oe_data, 0), + NextValue(sbus_oe_slave_in, 0), + NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), + NextValue(sbus_master_error_virtual, sbus_master_last_virtual), + NextState("Idle") + ], "default": [NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(master_error_seen, 1), NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextState("Idle") ], @@ -1417,6 +1410,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), + NextValue(sbus_master_throttle, sbus_default_master_throttle), NextValue(stat_master_done_counter, stat_master_done_counter + 1), NextState("Idle") ) @@ -1470,11 +1464,18 @@ class SBusFPGABus(Module): NextValue(stat_master_rerun_counter, stat_master_rerun_counter + 1), NextState("Idle") ], - "default": ## ACK_ERRS or other + ACK_ERR: ## ACK_ERRS or other + [NextValue(sbus_oe_data, 0), + NextValue(sbus_oe_slave_in, 0), + NextValue(sbus_oe_master_in, 0), + NextValue(stat_master_error_counter, stat_master_error_counter + 1), + NextValue(sbus_master_error_virtual, sbus_master_last_virtual), + NextState("Idle"), + ], + "default": ## other [NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(master_error_seen, 1), NextValue(stat_master_error_counter, stat_master_error_counter + 1), NextState("Idle"), ], @@ -1485,7 +1486,7 @@ class SBusFPGABus(Module): NextValue(sbus_oe_data, 0), NextValue(sbus_oe_slave_in, 0), NextValue(sbus_oe_master_in, 0), - NextValue(sbus_master_throttle, 3), + NextValue(sbus_master_throttle, sbus_default_master_throttle), NextValue(stat_master_done_counter, stat_master_done_counter + 1), NextState("Idle") ) @@ -1717,6 +1718,7 @@ class SBusFPGABus(Module): self.buf_stat_master_done_counter = Signal(32) self.buf_stat_master_error_counter = Signal(32) self.buf_stat_master_rerun_counter = Signal(32) + self.buf_sbus_master_error_virtual = Signal(32) self.stat_update = Signal() stat_update_prev = Signal() @@ -1733,6 +1735,7 @@ class SBusFPGABus(Module): self.buf_stat_master_done_counter.eq(stat_master_done_counter), self.buf_stat_master_error_counter.eq(stat_master_error_counter), self.buf_stat_master_rerun_counter.eq(stat_master_rerun_counter), + self.buf_sbus_master_error_virtual.eq(sbus_master_error_virtual), self.stat_cycle_counter.eq(0), stat_slave_start_counter.eq(0), stat_slave_done_counter.eq(0), @@ -1742,6 +1745,7 @@ class SBusFPGABus(Module): stat_master_done_counter.eq(0), stat_master_error_counter.eq(0), stat_master_rerun_counter.eq(0), + sbus_master_error_virtual.eq(0), ) self.sync += If(stat_update_prev & ~self.stat_update, ## falling edge: reset buffer self.buf_stat_cycle_counter.eq(0), @@ -1753,4 +1757,5 @@ class SBusFPGABus(Module): self.buf_stat_master_done_counter.eq(0), self.buf_stat_master_error_counter.eq(0), self.buf_stat_master_rerun_counter.eq(0), + self.buf_sbus_master_error_virtual.eq(0), ) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index e3cb722..6b49585 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -275,10 +275,6 @@ class SBusFPGA(SoCCore): self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False)) #self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave) #self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave) - - self.submodules.sbus_master_error_virtual_sync = BusSynchronizer(width=32, idomain="sbus", odomain="sys") - self.comb += self.sbus_master_error_virtual_sync.i.eq(self.sbus_bus.sbus_master_error_virtual) - self.comb += self.exchange_with_mem.sbus_master_error_virtual.status.eq(self.sbus_master_error_virtual_sync.o) #self.add_sdcard()