github.com/rdolbeau.SBusFPGA
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Adding basic AES support (using AES block from https://github.com/mbgh/aes128-hdl)

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This commit is contained in:
Romain Dolbeau
2020-12-19 11:43:56 -05:00
parent 1b25261073
commit 8afe45ea54
3 changed files with 159 additions and 14 deletions
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57
NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.c
View File

@@ -89,16 +89,22 @@ struct rdfpga_128bits_alt {
#define RDFPGA_WH _IOW(0, 2, struct rdfpga_128bits)
#define RDFPGA_WI _IOW(0, 3, struct rdfpga_128bits)
#define RDFPGA_RC _IOR(0, 4, struct rdfpga_128bits)
#define RDFPGA_WL _IOW(0, 1, uint32_t)
#define RDFPGA_WL _IOW(0, 5, uint32_t)
#define RDFPGA_AESWK _IOW(0, 10, struct rdfpga_128bits)
#define RDFPGA_AESWD _IOW(0, 11, struct rdfpga_128bits)
#define RDFPGA_AESRO _IOR(0, 12, struct rdfpga_128bits)
int
rdfpga_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
{
struct rdfpga_softc *sc = device_lookup_private(&rdfpga_cd, minor(dev));
struct rdfpga_128bits_alt *bits = (struct rdfpga_128bits_alt*)data;
int err = 0, i;
int err = 0, i, ctr = 0;
uint32_t ctrl;
switch (cmd) {
/* GCM */
case RDFPGA_WC:
for (i = 0 ; i < 2 ; i++)
bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*8)), bits->x[i] );
@@ -118,6 +124,40 @@ rdfpga_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
case RDFPGA_WL:
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_LED, *(uint32_t*)data);
break;
/* AES */
case RDFPGA_AESWK:
ctrl = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_AES128_CTRL);
if (ctrl)
return EBUSY;
for (i = 0 ; i < 2 ; i++)
bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_AES128_KEY + (i*8)), bits->x[i] );
sc->aes_key_refresh = 1;
break;
case RDFPGA_AESWD:
ctrl = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_AES128_CTRL);
if (ctrl)
return EBUSY;
for (i = 0 ; i < 2 ; i++)
bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_AES128_DATA + (i*8)), bits->x[i] );
ctrl = RDFPGA_MASK_AES128_START;
if (sc->aes_key_refresh) {
ctrl |= RDFPGA_MASK_AES128_NEWKEY;
sc->aes_key_refresh = 0;
}
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_AES128_CTRL, ctrl);
break;
case RDFPGA_AESRO:
ctrl = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_AES128_CTRL);
while (ctrl && (ctr < 3)) {
delay(1);
ctrl = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_REG_AES128_CTRL);
ctr ++;
}
if (ctrl)
return EBUSY;
for (i = 0 ; i < 2 ; i++)
bits->x[i] = bus_space_read_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_AES128_OUT + (i*8)));
break;
default:
err = EINVAL;
break;
@@ -129,32 +169,32 @@ rdfpga_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
int
rdfpga_open(dev_t dev, int flags, int mode, struct lwp *l)
{
#if 0
struct rdfpga_softc *sc = device_lookup_private(&rdfpga_cd, minor(dev));
int i;
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*4)), 0);
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_H + (i*4)), 0);
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + (i*4)), 0);
#endif
return (0);
}
int
rdfpga_close(dev_t dev, int flags, int mode, struct lwp *l)
{
#if 0
struct rdfpga_softc *sc = device_lookup_private(&rdfpga_cd, minor(dev));
int i;
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_C + (i*4)), 0);
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_H + (i*4)), 0);
for (i = 0 ; i < 4 ; i++)
bus_space_write_4(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_GCM_I + (i*4)), 0);
#endif
return (0);
}
@@ -314,6 +354,7 @@ rdfpga_attach(device_t parent, device_t self, void *aux)
struct sbus_softc *sbsc = device_private(parent);
int node;
int sbusburst;
int i;
/* bus_dma_tag_t dt = sa->sa_dmatag; */
sc->sc_bustag = sa->sa_bustag;
@@ -366,4 +407,8 @@ rdfpga_attach(device_t parent, device_t self, void *aux)
} else {
aprint_normal_dev(self, "dmamap: %lu %lu %d (%p)\n", sc->sc_dmamap->dm_maxsegsz, sc->sc_dmamap->dm_mapsize, sc->sc_dmamap->dm_nsegs, sc->sc_dmatag->_dmamap_load);
}
for (i = 0 ; i < 2 ; i++)
bus_space_write_8(sc->sc_bustag, sc->sc_bhregs, (RDFPGA_REG_AES128_KEY + (i*8)), 0ull);
sc->aes_key_refresh = 1;
}

18
NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h
View File

@@ -43,21 +43,25 @@ struct rdfpga_softc {
int sc_bufsiz; /* Size of buffer */
bus_dma_tag_t sc_dmatag;
bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
int aes_key_refresh;
};
/* led */
#define RDFPGA_REG_LED 0x0 /* 1 reg */
/* gcm stuff */
#define RDFGPA_REG_GCM_BASE 0x40
#define RDFPGA_REG_GCM_H (RDFGPA_REG_GCM_BASE + 0x00) /* 4 regs */
#define RDFPGA_REG_GCM_C (RDFGPA_REG_GCM_BASE + 0x10) /* 4 regs */
#define RDFPGA_REG_GCM_I (RDFGPA_REG_GCM_BASE + 0x20) /* 4 regs */
/* dma, currently to read data in GCM */
#define RDFPGA_REG_DMA_BASE 0x80
#define RDFPGA_REG_DMA_ADDR (RDFPGA_REG_DMA_BASE + 0x00)
#define RDFPGA_REG_DMA_CTRL (RDFPGA_REG_DMA_BASE + 0x04)
#define RDFPGA_MASK_DMA_CTRL_START 0x80000000
#define RDFPGA_MASK_DMA_CTRL_BUSY 0x40000000
#define RDFPGA_MASK_DMA_CTRL_BUSY 0x40000000 /* unused */
#define RDFPGA_MASK_DMA_CTRL_ERR 0x20000000
/* #define RDFPGA_MASK_DMA_CTRL_RW 0x10000000 */
#define RDFPGA_MASK_DMA_CTRL_BLKCNT 0x00000FFF
@@ -66,4 +70,16 @@ struct rdfpga_softc {
#define RDFPGA_VAL_DMA_MAX_SZ 65536
/* having a go at AES128 */
#define RDFPGA_REG_AES128_BASE 0xc0
#define RDFPGA_REG_AES128_KEY (RDFPGA_REG_AES128_BASE + 0x00) /* 4 regs */
#define RDFPGA_REG_AES128_DATA (RDFPGA_REG_AES128_BASE + 0x10) /* 4 regs */
#define RDFPGA_REG_AES128_OUT (RDFPGA_REG_AES128_BASE + 0x20) /* 4 regs */
#define RDFPGA_REG_AES128_CTRL (RDFPGA_REG_AES128_BASE + 0x30)
#define RDFPGA_MASK_AES128_START 0x80000000
#define RDFPGA_MASK_AES128_BUSY 0x40000000
#define RDFPGA_MASK_AES128_ERR 0x20000000
#define RDFPGA_MASK_AES128_NEWKEY 0x10000000
#endif /* _RDFPGA_H_ */