diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py index e3204f0..32965a1 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py @@ -175,7 +175,7 @@ LED_M_READ = 0x20 LED_M_CACHE = 0x40 class SBusFPGABus(Module): - def __init__(self, platform, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, burst_size = 8): + def __init__(self, platform, hold_reset, wishbone_slave, wishbone_master, tosbus_fifo, fromsbus_fifo, fromsbus_req_fifo, version, burst_size = 8): self.platform = platform self.hold_reset = hold_reset @@ -217,8 +217,24 @@ class SBusFPGABus(Module): pad_SBUS_3V3_ERRs = platform.request("SBUS_3V3_ERRs") #pad_SBUS_3V3_RSTs = platform.request("SBUS_3V3_RSTs") pad_SBUS_3V3_SELs = platform.request("SBUS_3V3_SELs") - #pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s") - pad_SBUS_3V3_INT7s = platform.request("SBUS_3V3_INT7s") + if (version == "V1.0"): + #pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s") + pad_SBUS_3V3_INT7s = platform.request("SBUS_3V3_INT7s") + #sbus_oe_int1 = Signal(reset=0) + sbus_oe_int7 = Signal(reset=0) + elif (version == "V1.2"): + pad_SBUS_3V3_INT1s = platform.request("SBUS_3V3_INT1s") + pad_SBUS_3V3_INT2s = platform.request("SBUS_3V3_INT2s") + #pad_SBUS_3V3_INT3s = platform.request("SBUS_3V3_INT3s") + pad_SBUS_3V3_INT4s = platform.request("SBUS_3V3_INT4s") + pad_SBUS_3V3_INT5s = platform.request("SBUS_3V3_INT5s") + pad_SBUS_3V3_INT6s = platform.request("SBUS_3V3_INT6s") + sbus_oe_int1 = Signal(reset=0) + sbus_oe_int2 = Signal(reset=0) + #sbus_oe_int3 = Signal(reset=0) + sbus_oe_int4 = Signal(reset=0) + sbus_oe_int5 = Signal(reset=0) + sbus_oe_int6 = Signal(reset=0) pad_SBUS_3V3_PPRD = platform.request("SBUS_3V3_PPRD") pad_SBUS_OE = platform.request("SBUS_OE") pad_SBUS_3V3_ACKs = platform.request("SBUS_3V3_ACKs") @@ -231,8 +247,6 @@ class SBusFPGABus(Module): sbus_oe_data = Signal(reset=0) sbus_oe_slave_in = Signal(reset=0) sbus_oe_master_in = Signal(reset=0) - #sbus_oe_int1 = Signal(reset=0) - sbus_oe_int7 = Signal(reset=0) #sbus_oe_master_br = Signal(reset=0) sbus_last_pa = Signal(28) @@ -254,10 +268,24 @@ class SBusFPGABus(Module): #SBUS_3V3_RSTs = Signal() SBUS_3V3_SELs_i = Signal(reset=1) self.comb += SBUS_3V3_SELs_i.eq(pad_SBUS_3V3_SELs) - #SBUS_3V3_INT1s_o = Signal(reset=1) - #self.specials += Tristate(pad_SBUS_3V3_INT1s, SBUS_3V3_INT1s_o, sbus_oe_int1, None) - SBUS_3V3_INT7s_o = Signal(reset=1) - self.specials += Tristate(pad_SBUS_3V3_INT7s, SBUS_3V3_INT7s_o, sbus_oe_int7, None) + if (version == "V1.0"): + #SBUS_3V3_INT1s_o = Signal(reset=1) + #self.specials += Tristate(pad_SBUS_3V3_INT1s, SBUS_3V3_INT1s_o, sbus_oe_int1, None) + SBUS_3V3_INT7s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT7s, SBUS_3V3_INT7s_o, sbus_oe_int7, None) + elif (version == "V1.2"): + SBUS_3V3_INT1s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT1s, SBUS_3V3_INT1s_o, sbus_oe_int1, None) + SBUS_3V3_INT2s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT2s, SBUS_3V3_INT2s_o, sbus_oe_int2, None) + #SBUS_3V3_INT3s_o = Signal(reset=1) + #self.specials += Tristate(pad_SBUS_3V3_INT3s, SBUS_3V3_INT3s_o, sbus_oe_int3, None) + SBUS_3V3_INT4s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT4s, SBUS_3V3_INT4s_o, sbus_oe_int4, None) + SBUS_3V3_INT5s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT5s, SBUS_3V3_INT5s_o, sbus_oe_int5, None) + SBUS_3V3_INT6s_o = Signal(reset=1) + self.specials += Tristate(pad_SBUS_3V3_INT6s, SBUS_3V3_INT6s_o, sbus_oe_int6, None) SBUS_3V3_PPRD_i = Signal() SBUS_3V3_PPRD_o = Signal() self.specials += Tristate(pad_SBUS_3V3_PPRD, SBUS_3V3_PPRD_o, sbus_oe_slave_in, SBUS_3V3_PPRD_i) diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index 7467382..2c88ff0 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -153,8 +153,21 @@ class SBusFPGA(SoCCore): self.platform = platform = ztex213_sbus.Platform(variant="ztex2.13a", version = version) + xdc_timings_filename = None; if (version == "V1.0"): + xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings.xdc" self.platform.add_extension(ztex213_sbus._usb_io_v1_0) + elif (version == "V1.2"): + xdc_timings_filename = "/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware/sbus-to-ztex-timings-V1_2.xdc" + + if (xdc_timings_filename != None): + xdc_timings_file = open(xdc_timings_filename) + xdc_timings_lines = xdc_timings_file.readlines() + for line in xdc_timings_lines: + if (line[0:3] == "set"): + fix_line = line.strip().replace("{", "{{").replace("}", "}}") + print(fix_line) + platform.add_platform_command(fix_line) SoCCore.__init__(self, platform=platform, @@ -187,7 +200,7 @@ class SBusFPGA(SoCCore): if (version == "V1.0"): self.submodules.leds = LedChaser( - pads = platform.request("SBUS_DATA_OE_LED_2"), #platform.request("user_led", 7), + pads = platform.request("SBUS_DATA_OE_LED_2"), sys_clk_freq = sys_clk_freq) self.add_csr("leds") @@ -280,6 +293,7 @@ class SBusFPGA(SoCCore): tosbus_fifo=self.tosbus_fifo, fromsbus_fifo=self.fromsbus_fifo, fromsbus_req_fifo=self.fromsbus_req_fifo, + version=version, burst_size=burst_size) #self.submodules.sbus_bus = _sbus_bus self.submodules.sbus_bus = ClockDomainsRenamer("sbus")(_sbus_bus)