From b2377276b2f046a862564957054787c6121a37c4 Mon Sep 17 00:00:00 2001 From: Romain Dolbeau Date: Sat, 23 Jul 2022 12:51:43 +0200 Subject: [PATCH] rename blit to blit_cg6 --- sbus-to-ztex-gateware-migen/{blit.c => blit_cg6.c} | 6 +++--- sbus-to-ztex-gateware-migen/{blit.lds => blit_cg6.lds} | 0 sbus-to-ztex-gateware-migen/{blit.sh => blit_cg6.sh} | 8 ++++---- sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) rename sbus-to-ztex-gateware-migen/{blit.c => blit_cg6.c} (99%) rename sbus-to-ztex-gateware-migen/{blit.lds => blit_cg6.lds} (100%) rename sbus-to-ztex-gateware-migen/{blit.sh => blit_cg6.sh} (55%) diff --git a/sbus-to-ztex-gateware-migen/blit.c b/sbus-to-ztex-gateware-migen/blit_cg6.c similarity index 99% rename from sbus-to-ztex-gateware-migen/blit.c rename to sbus-to-ztex-gateware-migen/blit_cg6.c index 97c877e..f492f9d 100644 --- a/sbus-to-ztex-gateware-migen/blit.c +++ b/sbus-to-ztex-gateware-migen/blit_cg6.c @@ -1,7 +1,7 @@ /* - ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -S blit.c -march=rv32ib -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles - ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -o blit -march=rv32ib -mabi=ilp32 -T blit.lds -nostartfiles blit.s - ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objcopy -O binary -j .text blit blit.raw + ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -S blit_cg6.c -march=rv32ib -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles + ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -o blit -march=rv32ib -mabi=ilp32 -T blit_cg6.lds -nostartfiles blit_cg6.s + ~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objcopy -O binary -j .text blit blit_cg6.raw */ #ifndef HRES diff --git a/sbus-to-ztex-gateware-migen/blit.lds b/sbus-to-ztex-gateware-migen/blit_cg6.lds similarity index 100% rename from sbus-to-ztex-gateware-migen/blit.lds rename to sbus-to-ztex-gateware-migen/blit_cg6.lds diff --git a/sbus-to-ztex-gateware-migen/blit.sh b/sbus-to-ztex-gateware-migen/blit_cg6.sh similarity index 55% rename from sbus-to-ztex-gateware-migen/blit.sh rename to sbus-to-ztex-gateware-migen/blit_cg6.sh index 65b8245..50f42f3 100755 --- a/sbus-to-ztex-gateware-migen/blit.sh +++ b/sbus-to-ztex-gateware-migen/blit_cg6.sh @@ -23,8 +23,8 @@ ARCH=rv32i_zba_zbb_zbt PARAM="-DHRES=${HRES} -DVRES=${VRES} -DBASE_FB=${BASE_FB}" if test "x$1" != "xASM"; then - $GCC $OPT -S -o blit.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c + $GCC $OPT -S -o blit_cg6.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_cg6.c fi -$GCC $OPT -c -o blit.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s && -$GCCLINK $OPT -o blit $PARAM -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o && -$OBJCOPY -O binary -j .text -j .rodata blit blit.raw +$GCC $OPT -c -o blit_cg6.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_cg6.s && +$GCCLINK $OPT -o blit_cg6 $PARAM -march=$ARCH -mabi=ilp32 -T blit_cg6.lds -nostartfiles blit_cg6.o && +$OBJCOPY -O binary -j .text -j .rodata blit_cg6 blit_cg6.raw diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py index e1c6ff7..9850d7b 100644 --- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py +++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py @@ -543,7 +543,7 @@ class SBusFPGA(SoCCore): self.bus.add_slave("cg6_alt", self.cg6.bus3, SoCRegion(origin=self.mem_map.get("cg6_alt", None), size=0x2000, cached=False)) self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus) self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus) - cg6_rom_file = "blit.raw" + cg6_rom_file = "blit_cg6.raw" cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little") cg6_rom_len = 4*len(cg6_rom_data); rounded_cg6_rom_len = 2**log2_int(cg6_rom_len, False)