diff --git a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
index f795598..d447122 100644
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
@@ -197,8 +197,8 @@ class SBusFPGA(SoCCore):
 
         self.bus.add_master(name="SBusBridgeToWishbone", master=wishbone_master_sys)
         self.bus.add_slave(name="usb_fake_dma", slave=self.wishbone_slave_sys, region=SoCRegion(origin=self.mem_map.get("usb_fake_dma", None), size=0x03ffffff, cached=False))
-        self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_master)
-        self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_master)
+        self.bus.add_master(name="mem_read_master", master=self.exchange_with_mem.wishbone_r_slave)
+        self.bus.add_master(name="mem_write_master", master=self.exchange_with_mem.wishbone_w_slave)
 
         self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                                                    memtype        = "DDR3",