github.com/rdolbeau.SBusFPGA
1
0
Fork 0
mirror of synced 2026-04-28 21:17:46 +00:00
Code Issues Projects Releases Wiki Activity

more comments

Browse Source
This commit is contained in:
Romain Dolbeau
2020-12-16 05:22:50 -05:00
parent d696ae0209
commit d1e36d05da
1 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
sbus-to-ztex-gateware/sbus_fsm.vhd
View File

@@ -392,6 +392,8 @@ BEGIN
IO => SBUS_3V3_D(i), -- Buffer INOUT PORT (connect directly to top-level PORT) IO => SBUS_3V3_D(i), -- Buffer INOUT PORT (connect directly to top-level PORT)
I => BUF_DATA_O(i), -- Buffer input (warning - data going to SBUS so O) I => BUF_DATA_O(i), -- Buffer input (warning - data going to SBUS so O)
T => DATA_T -- 3-state enable input, high=input, low=output T => DATA_T -- 3-state enable input, high=input, low=output
-- DATA_T is 1 by default, so input from the SBus (e.g. during slave *write* cycle)
-- DATA_T should be set to 1 during slave *read* cycle, when we send data to the SBus (IOBUS is an output)
); );
end generate GENDATABUF; end generate GENDATABUF;