diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h index c021e9b..fe6ffe4 100644 --- a/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga.h @@ -1,12 +1,9 @@ /* $NetBSD$ */ /*- - * Copyright (c) 1998 The NetBSD Foundation, Inc. + * Copyright (c) 2020 Romain Dolbeau * All rights reserved. * - * This code is derived from software contributed to The NetBSD Foundation - * by Paul Kranenburg. - * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.c b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.c new file mode 100644 index 0000000..a894d92 --- /dev/null +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.c @@ -0,0 +1,190 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 Romain Dolbeau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__KERNEL_RCSID(0, "$NetBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#include + +#include + +int rdfpga_trng_print(void *, const char *); +int rdfpga_trng_match(device_t, cfdata_t, void *); +void rdfpga_trng_attach(device_t, device_t, void *); + +CFATTACH_DECL_NEW(rdfpga_trng, sizeof(struct rdfpga_trng_softc), + rdfpga_trng_match, rdfpga_trng_attach, NULL, NULL); + +dev_type_open(rdfpga_trng_open); +dev_type_close(rdfpga_trng_close); +dev_type_ioctl(rdfpga_trng_ioctl); + + + +const struct cdevsw rdfpga_trng_cdevsw = { + .d_open = rdfpga_trng_open, + .d_close = rdfpga_trng_close, + .d_read = noread, + .d_write = nowrite, + .d_ioctl = rdfpga_trng_ioctl, + .d_stop = nostop, + .d_tty = notty, + .d_poll = nopoll, + .d_mmap = nommap, + .d_kqfilter = nokqfilter, + .d_discard = nodiscard, + .d_flag = 0 +}; + +extern struct cfdriver rdfpga_trng_cd; + +#define RDFPGA_TRNG_RD _IOR(0, 1, u_int32_t) +int +rdfpga_trng_ioctl (dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) +{ + struct rdfpga_trng_softc *sc = device_lookup_private(&rdfpga_trng_cd, minor(dev)); + int err = 0; + + switch (cmd) { + case RDFPGA_TRNG_RD: + *((u_int32_t*)data) = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_TRNG_REG_DATA); + break; + default: + err = EINVAL; + break; + } + return(err); +} + + +int +rdfpga_trng_open(dev_t dev, int flags, int mode, struct lwp *l) +{ + return (0); +} + +int +rdfpga_trng_close(dev_t dev, int flags, int mode, struct lwp *l) +{ + return (0); +} + +int +rdfpga_trng_print(void *aux, const char *busname) +{ + + sbus_print(aux, busname); + return (UNCONF); +} + +int +rdfpga_trng_match(device_t parent, cfdata_t cf, void *aux) +{ + struct sbus_attach_args *sa = (struct sbus_attach_args *)aux; + + return (strcmp("RDOL,trng", sa->sa_name) == 0); +} + +static void +rdfpga_trng_getentropy(size_t nbytes, void *cookie) { + struct rdfpga_trng_softc *sc = cookie; + /* aprint_normal_dev(sc->sc_dev, "%s\n", __PRETTY_FUNCTION__); */ + u_int32_t data = bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_TRNG_REG_DATA); + rnd_add_data_sync(&sc->sc_rndsource, &data, 4, 32); +} + +/* + * Attach all the sub-devices we can find + */ +void +rdfpga_trng_attach(device_t parent, device_t self, void *aux) +{ + struct sbus_attach_args *sa = aux; + struct rdfpga_trng_softc *sc = device_private(self); + struct sbus_softc *sbsc = device_private(parent); + int node; + int sbusburst; + + sc->sc_bustag = sa->sa_bustag; + sc->sc_dev = self; + + if (sbus_bus_map(sc->sc_bustag, sa->sa_slot, sa->sa_offset, sa->sa_size, + BUS_SPACE_MAP_LINEAR, &sc->sc_bhregs) != 0) { + aprint_error(": cannot map registers\n"); + return; + } + + //sc->sc_buffer = bus_space_vaddr(sc->sc_bustag, sc->sc_bhregs); + sc->sc_bufsiz = sa->sa_size; + + node = sc->sc_node = sa->sa_node; + + /* + * Get transfer burst size from PROM + */ + sbusburst = sbsc->sc_burst; + if (sbusburst == 0) + sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ + + sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); + if (sc->sc_burst == -1) + /* take SBus burst sizes */ + sc->sc_burst = sbusburst; + + /* Clamp at parent's burst sizes */ + sc->sc_burst &= sbusburst; + + aprint_normal("\n"); + aprint_normal_dev(self, "nid 0x%x, bustag %p, burst 0x%x (parent 0x%0x)\n", + sc->sc_node, + sc->sc_bustag, + sc->sc_burst, + sbsc->sc_burst); + + aprint_normal_dev(self, "garbage 0x%08x\n", bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_TRNG_REG_DATA)); + aprint_normal_dev(self, "random 0x%08x\n", bus_space_read_4(sc->sc_bustag, sc->sc_bhregs, RDFPGA_TRNG_REG_DATA)); + + rndsource_setcb(&sc->sc_rndsource, rdfpga_trng_getentropy, sc); + rnd_attach_source(&sc->sc_rndsource, device_xname(self), RND_TYPE_RNG, RND_FLAG_HASCB | RND_FLAG_COLLECT_VALUE); +} diff --git a/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.h b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.h new file mode 100644 index 0000000..8142a23 --- /dev/null +++ b/NetBSD/9.0/usr/src/sys/dev/sbus/rdfpga_trng.h @@ -0,0 +1,48 @@ +/* $NetBSD$ */ + +/*- + * Copyright (c) 2020 Romain Dolbeau + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RDFPGA_TRNG_H_ +#define _RDFPGA_TRNG_H_ + +struct rdfpga_trng_softc { + device_t sc_dev; /* us as a device */ + u_int sc_rev; /* revision */ + int sc_node; /* PROM node ID */ + int sc_burst; /* DVMA burst size in effect */ + bus_space_tag_t sc_bustag; /* bus tag */ + bus_space_handle_t sc_bhregs; /* bus handle */ + //void * sc_buffer; /* VA of the registers */ + int sc_bufsiz; /* Size of buffer */ + struct krndsource sc_rndsource; +}; + +/* ctrl*/ +#define RDFPGA_TRNG_REG_BASE 0x00 +#define RDFPGA_TRNG_REG_DATA (RDFPGA_TRNG_REG_BASE + 0x00) + +#endif /* _RDFPGA_TRNG_H_ */ diff --git a/sbus-to-ztex-gateware/sbus_fsm.vhd b/sbus-to-ztex-gateware/sbus_fsm.vhd index 7112e18..863ddfe 100644 --- a/sbus-to-ztex-gateware/sbus_fsm.vhd +++ b/sbus-to-ztex-gateware/sbus_fsm.vhd @@ -78,12 +78,15 @@ ENTITY SBusFSM is CONSTANT ADDR_PFX_LENGTH : integer := 12; CONSTANT ROM_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000000"; CONSTANT REG_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000001"; + CONSTANT REGTRNG_ADDR_PFX : std_logic_vector(ADDR_PFX_HIGH downto ADDR_PFX_LOW) := "000000000010"; + + CONSTANT REG_INDEX_LED : integer := 0; CONSTANT REG_INDEX_AES128_CTRL: integer := 1; CONSTANT REG_INDEX_DMA_ADDR : integer := 2; CONSTANT REG_INDEX_DMA_CTRL : integer := 3; - CONSTANT REG_INDEX_DMAW_ADDR : integer := 4; - CONSTANT REG_INDEX_DMAW_CTRL : integer := 5; + CONSTANT REG_INDEX_DMAW_ADDR : integer := 4; + CONSTANT REG_INDEX_DMAW_CTRL : integer := 5; -- starts at 64 so we can do 64 bytes burst (see address wrapping) CONSTANT REG_INDEX_GCM_H1 : integer := 16; CONSTANT REG_INDEX_GCM_H2 : integer := 17; @@ -135,6 +138,8 @@ ENTITY SBusFSM is constant AES128_CTRL_CBCMOD_IDX : integer := 27; constant AES128_CTRL_AES256_IDX : integer := 26; constant AES128_CTRL_DEC_IDX : integer := 25; + + CONSTANT REG_INDEX_TRNG_DATA : integer := 0; -- OFFSET to REGS; (15 downto 0) so 16 bits CONSTANT OFFSET_LENGTH : integer := 16; @@ -210,7 +215,7 @@ ARCHITECTURE RTL OF SBusFSM IS -- cycle we put the data on the bus when reading from Prom -- also ACK goes to idle -- half-word-wide - SBus_Slave_Ack_Read_Prom_HWord, +-- SBus_Slave_Ack_Read_Prom_HWord, -- cycle(s) we put the data on the bus when reading from Prom -- also ACK the next word we will put, or goes to idle for last -- word-wide, burst from 1 to 16 @@ -222,7 +227,7 @@ ARCHITECTURE RTL OF SBusFSM IS -- cycle we put the data on the bus when reading from registers -- also ACK goes to idle -- half-word-wide - SBus_Slave_Ack_Read_Reg_HWord, +-- SBus_Slave_Ack_Read_Reg_HWord, -- cycle(s) we put the data on the bus when reading from registers -- also ACK the next word we will put, or goes to idle for last -- word-wide, burst from 1 to 16 @@ -291,6 +296,14 @@ ARCHITECTURE RTL OF SBusFSM IS signal fifo_fromaes_full : STD_LOGIC; signal fifo_fromaes_empty : STD_LOGIC; + signal fifo_fromstrng_din : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fifo_fromstrng_wr_en : STD_LOGIC; + signal fifo_fromstrng_rd_en : STD_LOGIC; + signal fifo_fromstrng_dout : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal fifo_fromstrng_full : STD_LOGIC; + signal fifo_fromstrng_empty : STD_LOGIC; + + -- SIGNAL LIFE_COUNTER48 : natural range 0 to 48000000 := 300; -- SIGNAL LIFE_COUNTER25 : natural range 0 to 25000000 := 300; SIGNAL RES_COUNTER : natural range 0 to 4 := 4; @@ -301,7 +314,9 @@ ARCHITECTURE RTL OF SBusFSM IS SIGNAL AES_RST_COUNTER : natural range 0 to 31 := 31; SIGNAL AES_TIMEOUT_COUNTER : natural range 0 to 63 := 63; - -- 16 registers for GCM (12 used), 4 for DMA (2 used ATM), 16 for AES (13 used ATM) + -- bank of registers (256 bytes) for cryptoengine (and led) + -- 0-64: 16 for controls (6 used) 16 registers for GCM (12 used), 16 unused, 16 for AES + -- 64-127: are remmaped from TRNG space type REGISTERS_TYPE is array(0 to 64) of std_logic_vector(31 downto 0); SIGNAL REGISTERS : REGISTERS_TYPE; @@ -395,6 +410,11 @@ ARCHITECTURE RTL OF SBusFSM IS begin return true; end function; + + pure function REG_OFFSET_IS_ANYTRNGREAD(value : in std_logic_vector(OFFSET_HIGH downto OFFSET_LOW)) return boolean is + begin + return true; + end function; pure function SIZ_IS_WORD(value : in std_logic_vector(2 downto 0)) return boolean is begin @@ -526,6 +546,18 @@ ARCHITECTURE RTL OF SBusFSM IS empty : out STD_LOGIC ); end component; + component fifo_generator_from_strng is + Port ( + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 31 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 31 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC + ); + end component; component uart_tx is generic ( @@ -566,6 +598,26 @@ ARCHITECTURE RTL OF SBusFSM IS ); end component aes_wrapper; +-- component strng_wrapper is +-- port ( +-- strng_wrapper_rst : in std_logic; +-- strng_wrapper_clk : in std_logic; +-- output_fifo_in : out std_logic_vector(31 downto 0); +-- output_fifo_full : in std_logic; +-- output_fifo_wr_en : out std_logic +-- ); +-- end component strng_wrapper; + + component trivium_wrapper is + port ( + trivium_wrapper_rst : in std_logic; + trivium_wrapper_clk : in std_logic; + output_fifo_in : out std_logic_vector(31 downto 0); + output_fifo_full : in std_logic; + output_fifo_wr_en : out std_logic + ); + end component trivium_wrapper; + PROCEDURE SBus_Set_Default( -- signal SBUS_3V3_ACKs : OUT std_logic_vector(2 downto 0); -- signal SBUS_3V3_ERRs : OUT STD_LOGIC; @@ -635,18 +687,18 @@ BEGIN --label_mas: mastrovito_V2_multiplication PORT MAP( a => mas_a, b => mas_b, c => mas_c ); - label_fifo: fifo_generator_uart port map(rst => fifo_rst, wr_clk => SBUS_3V3_CLK, rd_clk => fxclk_in, + label_fifo_uart: fifo_generator_uart port map(rst => fifo_rst, wr_clk => SBUS_3V3_CLK, rd_clk => fxclk_in, din => fifo_din, wr_en => fifo_wr_en, rd_en => fifo_rd_en, dout => fifo_dout, full => fifo_full, empty => fifo_empty); - - - label_fifo_toaes: fifo_generator_to_aes port map(wr_clk => SBUS_3V3_CLK, rd_clk => aes_clk_out, din => fifo_toaes_din, wr_en => fifo_toaes_wr_en, rd_en => fifo_toaes_rd_en, dout => fifo_toaes_dout, full => fifo_toaes_full, empty => fifo_toaes_empty); label_fifo_fromaes: fifo_generator_from_aes port map(wr_clk => aes_clk_out, rd_clk => SBUS_3V3_CLK, din => fifo_fromaes_din, wr_en => fifo_fromaes_wr_en, rd_en => fifo_fromaes_rd_en, dout => fifo_fromaes_dout, full => fifo_fromaes_full, empty => fifo_fromaes_empty); + label_fifo_fromstrng: fifo_generator_from_strng port map(wr_clk => aes_clk_out, rd_clk => SBUS_3V3_CLK, + din => fifo_fromstrng_din, wr_en => fifo_fromstrng_wr_en, rd_en => fifo_fromstrng_rd_en, + dout => fifo_fromstrng_dout, full => fifo_fromstrng_full, empty => fifo_fromstrng_empty); label_aes_wrapper: aes_wrapper port map( aes_wrapper_rst => aes_wrapper_rst, aes_wrapper_clk => aes_clk_out, @@ -657,7 +709,22 @@ BEGIN output_fifo_full => fifo_fromaes_full, output_fifo_wr_en => fifo_fromaes_wr_en ); - + +-- label_strng_wrapper: strng_wrapper port map ( +-- strng_wrapper_rst => aes_wrapper_rst, +-- strng_wrapper_clk => aes_clk_out, +-- output_fifo_in => fifo_fromstrng_din, +-- output_fifo_full => fifo_fromstrng_full, +-- output_fifo_wr_en => fifo_fromstrng_wr_en +-- ); + label_trivium_wrapper: trivium_wrapper port map ( + trivium_wrapper_rst => aes_wrapper_rst, + trivium_wrapper_clk => aes_clk_out, + output_fifo_in => fifo_fromstrng_din, + output_fifo_full => fifo_fromstrng_full, + output_fifo_wr_en => fifo_fromstrng_wr_en + ); + -- label_clk_wiz: clk_wiz_0 port map(clk_out1 => uart_clk, clk_in1 => fxclk_in); label_aes_clk_wiz: clk_wiz_aes port map(clk_out1 => aes_clk_out, clk_in1 => fxclk_in); @@ -685,6 +752,7 @@ BEGIN variable dma_write : boolean := false; variable dma_ctrl_idx : integer range 0 to 7; variable dma_addr_idx : integer range 0 to 7; + variable reg_bank : integer range 0 to 1 := 0; BEGIN IF (SBUS_3V3_RSTs = '0') THEN State <= SBus_Start; @@ -695,6 +763,7 @@ BEGIN fifo_wr_en <= '0'; fifo_toaes_wr_en <= '0'; fifo_fromaes_rd_en <= '0'; + fifo_fromstrng_rd_en <= '0'; -- LIFE_COUNTER25 <= LIFE_COUNTER25 - 1; CASE State IS @@ -728,6 +797,16 @@ BEGIN -- 32 bits read from aligned memory IN REG space ------------------------------------ BUF_ACKs_O <= ACK_WORD; BUF_ERRs_O <= '1'; -- no late error + reg_bank := 0; + State <= SBus_Slave_Ack_Read_Reg_Burst; + ELSIF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = REGTRNG_ADDR_PFX) AND REG_OFFSET_IS_ANYTRNGREAD(last_pa(OFFSET_HIGH downto OFFSET_LOW)) + -- and (fifo_fromstrng_empty = '0') + ) then + -- 32 bits read from aligned memory IN REG TRNG space ------------------------------------ + -- if FIFO is empty, will fallback to returning an error... + BUF_ACKs_O <= ACK_WORD; + BUF_ERRs_O <= '1'; -- no late error + reg_bank := 1; State <= SBus_Slave_Ack_Read_Reg_Burst; ELSE BUF_ACKs_O <= ACK_ERR; @@ -751,23 +830,23 @@ BEGIN BUF_ERRs_O <= '1'; -- no late error State <= SBus_Slave_Error; END IF; - ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND BUF_SIZ_I = SIZ_HWORD AND BUF_PPRD_I='1' THEN - SMs_T <= '0'; -- ACKs/ERRs buffer in slave mode/output - fifo_wr_en <= '1'; fifo_din <= x"43"; -- "C" - last_pa := SBUS_3V3_PA; - SBUS_DATA_OE_LED <= '1'; - IF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = ROM_ADDR_PFX) and (last_pa(0) = '0')) then - -- 16 bits read from memory IN PROM space ------------------------------------ - BUF_ACKs_O <= ACK_HWORD; - BUF_ERRs_O <= '1'; -- no late error - -- word address goes to the p_addr lines - p_addr <= last_pa(OFFSET_HIGH downto (OFFSET_LOW+2)); - State <= SBus_Slave_Ack_Read_Prom_HWord; - ELSE - BUF_ACKs_O <= ACK_ERR; - BUF_ERRs_O <= '1'; -- no late error - State <= SBus_Slave_Error; - END IF; +-- ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND BUF_SIZ_I = SIZ_HWORD AND BUF_PPRD_I='1' THEN +-- SMs_T <= '0'; -- ACKs/ERRs buffer in slave mode/output +-- fifo_wr_en <= '1'; fifo_din <= x"43"; -- "C" +-- last_pa := SBUS_3V3_PA; +-- SBUS_DATA_OE_LED <= '1'; +-- IF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = ROM_ADDR_PFX) and (last_pa(0) = '0')) then +-- -- 16 bits read from memory IN PROM space ------------------------------------ +-- BUF_ACKs_O <= ACK_HWORD; +-- BUF_ERRs_O <= '1'; -- no late error +-- -- word address goes to the p_addr lines +-- p_addr <= last_pa(OFFSET_HIGH downto (OFFSET_LOW+2)); +-- State <= SBus_Slave_Ack_Read_Prom_HWord; +-- ELSE +-- BUF_ACKs_O <= ACK_ERR; +-- BUF_ERRs_O <= '1'; -- no late error +-- State <= SBus_Slave_Error; +-- END IF; -- WRITE WRITE WRITE -- ELSIF SBUS_3V3_SELs='0' AND SBUS_3V3_ASs='0' AND SIZ_IS_WORD(BUF_SIZ_I) AND BUF_PPRD_I='0' THEN SMs_T <= '0'; -- ACKs/ERRs buffer in slave mode/output @@ -964,7 +1043,7 @@ BEGIN fifo_wr_en <= '1'; fifo_din <= x"4A"; -- "J" DATA_T <= '0'; -- set buffer as output BURST_INDEX := conv_integer(INDEX_WITH_WRAP(BURST_COUNTER, BURST_LIMIT, last_pa(5 downto 2))); - BUF_DATA_O <= REGISTERS(conv_integer(last_pa(OFFSET_HIGH downto (OFFSET_LOW+6)))*16 + BURST_INDEX); + BUF_DATA_O <= REGISTERS(64*reg_bank + conv_integer(last_pa(OFFSET_HIGH downto (OFFSET_LOW+6)))*16 + BURST_INDEX); if (BURST_COUNTER = (BURST_LIMIT-1)) then BUF_ACKs_O <= ACK_IDLE; State <= SBus_Slave_Do_Read; @@ -972,6 +1051,10 @@ BEGIN BUF_ACKs_O <= ACK_WORD; BURST_COUNTER := BURST_COUNTER + 1; end if; + IF (reg_bank = 1) THEN -- reading from trng + fifo_fromstrng_rd_en <= '1'; -- remove one word from FIFO + REGISTERS(64 + REG_INDEX_TRNG_DATA) <= fifo_fromstrng_dout; + END IF; WHEN SBus_Slave_Do_Read => -- this is the (last) cycle IN which the master read fifo_wr_en <= '1'; fifo_din <= x"4B"; -- "K" @@ -1010,27 +1093,27 @@ BEGIN State <= SBus_Slave_Delay_Error; END IF; - WHEN SBus_Slave_Ack_Read_Prom_HWord => - fifo_wr_en <= '1'; fifo_din <= x"4D"; -- "M" - IF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = ROM_ADDR_PFX) and (last_pa(0) = '0'))then -- do we need to re-test ? - BUF_ACKs_O <= ACK_IDLE; - -- put data from PROM on the bus - DATA_T <= '0'; -- set buffer as output - CASE last_pa(1) IS - WHEN '0' => - BUF_DATA_O(31 downto 16) <= p_data(31 downto 16); - BUF_DATA_O(15 downto 0) <= (others => '0'); - WHEN '1' => - BUF_DATA_O(31 downto 16) <= p_data(15 downto 0); - BUF_DATA_O(15 downto 0) <= (others => '0'); - WHEN OTHERS => - BUF_DATA_O(31 downto 0) <= (others => '0'); -- TODO: FIXME, probably should generate an error - END CASE; - State <= SBus_Slave_Do_Read; - ELSE - BUF_ACKs_O <= ACK_IDLE; - State <= SBus_Slave_Delay_Error; - END IF; +-- WHEN SBus_Slave_Ack_Read_Prom_HWord => +-- fifo_wr_en <= '1'; fifo_din <= x"4D"; -- "M" +-- IF ((last_pa(ADDR_PFX_HIGH downto ADDR_PFX_LOW) = ROM_ADDR_PFX) and (last_pa(0) = '0'))then -- do we need to re-test ? +-- BUF_ACKs_O <= ACK_IDLE; +-- -- put data from PROM on the bus +-- DATA_T <= '0'; -- set buffer as output +-- CASE last_pa(1) IS +-- WHEN '0' => +-- BUF_DATA_O(31 downto 16) <= p_data(31 downto 16); +-- BUF_DATA_O(15 downto 0) <= (others => '0'); +-- WHEN '1' => +-- BUF_DATA_O(31 downto 16) <= p_data(15 downto 0); +-- BUF_DATA_O(15 downto 0) <= (others => '0'); +-- WHEN OTHERS => +-- BUF_DATA_O(31 downto 0) <= (others => '0'); -- TODO: FIXME, probably should generate an error +-- END CASE; +-- State <= SBus_Slave_Do_Read; +-- ELSE +-- BUF_ACKs_O <= ACK_IDLE; +-- State <= SBus_Slave_Delay_Error; +-- END IF; WHEN SBus_Slave_Error => fifo_wr_en <= '1'; fifo_din <= x"59"; -- "Y" @@ -1284,7 +1367,7 @@ BEGIN RES_COUNTER <= 4; END IF; - END CASE; + END CASE; -- SBus state machine CASE AES_State IS WHEN AES_IDLE => @@ -1353,7 +1436,18 @@ BEGIN REGISTERS(REG_INDEX_AES128_CTRL) <= (others => '0'); AES_State <= AES_IDLE; END IF; - END CASE; + END CASE; -- AES state machine + + CASE fifo_fromstrng_full IS + WHEN '1' => + fifo_fromstrng_rd_en <= '1'; -- remove one word from FIFO + REGISTERS(64 + REG_INDEX_TRNG_DATA) <= fifo_fromstrng_dout; + + WHEN others => + -- do nothing + + END CASE; --TRNG self-emptying FIFO + END IF; END PROCESS; @@ -1414,6 +1508,7 @@ BEGIN END IF; END PROCESS; + -- process to enable AES block process (aes_clk_out) BEGIN IF RISING_EDGE(aes_clk_out) THEN diff --git a/sbus-to-ztex-gateware/trivium_wrapper.vhd b/sbus-to-ztex-gateware/trivium_wrapper.vhd new file mode 100644 index 0000000..0cf9d2c --- /dev/null +++ b/sbus-to-ztex-gateware/trivium_wrapper.vhd @@ -0,0 +1,116 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity trivium_wrapper is + port ( + trivium_wrapper_rst : in std_logic; + trivium_wrapper_clk : in std_logic; + output_fifo_in : out std_logic_vector(31 downto 0); + output_fifo_full : in std_logic; + output_fifo_wr_en : out std_logic + ); +end trivium_wrapper; + +architecture RTL of trivium_wrapper is + + component rng_trivium is + + generic ( + num_bits: integer range 1 to 64; + init_key: std_logic_vector(79 downto 0); + init_iv: std_logic_vector(79 downto 0) ); + + port ( + clk: in std_logic; + rst: in std_logic; + reseed: in std_logic; + newkey: in std_logic_vector(79 downto 0); + newiv: in std_logic_vector(79 downto 0); + out_ready: in std_logic; + out_valid: out std_logic; + out_data: out std_logic_vector(num_bits-1 downto 0) ); + + end component; + + TYPE TRIVIUM_States IS ( TRIVIUM_IDLE, TRIVIUM_BYTE, TRIVIUM_OUT ); + SIGNAL TRIVIUM_State : TRIVIUM_States := TRIVIUM_IDLE; + + signal trivium_data : std_logic_vector(7 downto 0); + + signal trivium_rst : std_logic; + signal trivium_out_ready : std_logic; + signal trivium_out_valid : std_logic; + +begin + label_trivium_core: rng_trivium + generic map( + num_bits => 8, + init_key => x"01234657890123465789", -- ouch + init_iv => x"98765432109876543210" -- ouch + ) + port map( + clk => trivium_wrapper_clk, + rst => trivium_rst, + reseed => '0', -- ouch + newkey => (others => '0'), -- ouch + newiv => (others => '0'), -- ouch + out_ready => trivium_out_ready, + out_valid => trivium_out_valid, + out_data => trivium_data + ); + + trivium_wrapper: process (trivium_wrapper_rst, trivium_wrapper_clk) + variable byte_index : integer range 0 to 3; + variable buf : std_logic_vector(31 downto 0); + begin -- process trivium_wrapper + IF (trivium_wrapper_rst = '0') THEN + trivium_rst <= '1'; + TRIVIUM_State <= TRIVIUM_IDLE; + byte_index := 0; + + ELSIF RISING_EDGE(trivium_wrapper_clk) then + trivium_rst <= '0'; + output_fifo_wr_en <= '0'; + CASE TRIVIUM_State IS + WHEN TRIVIUM_IDLE => + IF (trivium_out_valid = '1') THEN + TRIVIUM_State <= TRIVIUM_BYTE; + trivium_out_ready <= '1'; + END IF; + -- one byte every cycle, plus 1 cycle for out and 1 idle + -- 6 cycles for 32 bits in the FIFO at most + WHEN TRIVIUM_BYTE => + case byte_index IS + WHEN 0 => + trivium_out_ready <= '1'; + buf(7 downto 0) := trivium_data; + byte_index := 1; + WHEN 1 => + trivium_out_ready <= '1'; + buf(15 downto 8) := trivium_data; + byte_index := 2; + WHEN 2 => + trivium_out_ready <= '1'; + buf(23 downto 16) := trivium_data; + byte_index := 3; + WHEN 3 => + trivium_out_ready <= '0'; + buf(31 downto 24) := trivium_data; + TRIVIUM_State <= TRIVIUM_OUT; + byte_index := 0; + END CASE; + + when TRIVIUM_OUT => + trivium_out_ready <= '0'; + IF (output_fifo_full = '0') THEN + output_fifo_in <= buf; + output_fifo_wr_en <= '1'; + TRIVIUM_State <= TRIVIUM_IDLE; + END IF; + END CASE; + end IF; + + end process trivium_wrapper; + +end RTL; diff --git a/sbus-to-ztex/prom.fc b/sbus-to-ztex/prom.fc new file mode 100644 index 0000000..fe378c7 Binary files /dev/null and b/sbus-to-ztex/prom.fc differ