441 lines
24 KiB
Python
441 lines
24 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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from litedram.common import LiteDRAMNativePort
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from litedram.frontend.wishbone import LiteDRAMWishbone2Native
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#from cg6_blit import CG6Blit
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class CG6Accel(Module): # AutoCSR ?
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def __init__(self, soc, base_fb, hres, vres):
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platform = soc.platform
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# for FBC and TEC
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self.bus = bus = wishbone.Interface()
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self.COORD_BITS = COORD_BITS = 12
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fbc_config = Signal(32, reset = (0x60000000)) # bit 11-12 are for resolution, see the GX manual (seem unused by drivers)
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fbc_mode = Signal(32)
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fbc_clip = Signal(32)
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fbc_s = Signal(32)
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#fbc_font = Signal(32)
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self.fbc_x = fbc_x = Array(Signal(COORD_BITS) for a in range(0, 4))
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self.fbc_y = fbc_y = Array(Signal(COORD_BITS) for a in range(0, 4))
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fbc_offx = Signal(COORD_BITS)
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fbc_offy = Signal(COORD_BITS)
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fbc_incx = Signal(COORD_BITS)
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fbc_incy = Signal(COORD_BITS)
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fbc_clipminx = Signal(COORD_BITS)
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fbc_clipminy = Signal(COORD_BITS)
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fbc_clipmaxx = Signal(COORD_BITS+1) # need the 13th bit as X11 uses 4096 for clipmaxx (console uses 4095)
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fbc_clipmaxy = Signal(COORD_BITS+1) # need the 13th bit as X11 uses 4096 for clipmaxx (console uses 4095)
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fbc_fg = Signal(8)
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fbc_bg = Signal(8)
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self.fbc_alu = fbc_alu = Signal(32)
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self.fbc_pm = fbc_pm = Signal(8)
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fbc_arectx = Signal(COORD_BITS)
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fbc_arecty = Signal(COORD_BITS)
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# extra stuff for the Vex core
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fbc_arectx_prev = Signal(COORD_BITS) # after fbc_arecty (600) - R/O
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fbc_arecty_prev = Signal(COORD_BITS) # after fbc_arectx_prev (601) - R/O
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self.fbc_r5_cmd = fbc_r5_cmd = Signal(32) # to communicate with Vex (602)
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fbc_r5_status = Array(Signal(32) for a in range(0, 4))
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fbc_next_font = Signal(32)
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fbc_next_x0 = Signal(COORD_BITS)
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fbc_next_x1 = Signal(COORD_BITS)
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fbc_next_y0 = Signal(COORD_BITS)
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#self.submodules.cg6_blit = CG6Blit(accel = self, soc = soc, base_fb = base_fb, hres = hres, vres = vres)
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# do-some-work flags
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fbc_do_draw = Signal()
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fbc_do_blit = Signal()
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# for GX global status register fbc_s
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GX_FULL_BIT = 29
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GX_INPROGRESS_BIT = 28
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font_layout = [
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("font", 32),
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("x0", COORD_BITS),
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("x1", COORD_BITS),
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("y0", COORD_BITS),
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]
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# depth is because the current 'font' is a bit slow, so we need to buffer a lot...
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self.submodules.fbc_fifo_font = SyncFIFOBuffered(width=layout_len(font_layout),depth=2048)
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#fifo_overflow = Signal()
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#self.comb += fifo_overflow.eq(self.fbc_fifo_font.we & ~self.fbc_fifo_font.writable)
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#draw_blit_overflow = Signal()
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fbc_fifo_font_in = Record(font_layout)
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fbc_fifo_font_out = Record(font_layout)
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self.comb += [
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self.fbc_fifo_font.din.eq(fbc_fifo_font_in.raw_bits()),
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fbc_fifo_font_out.raw_bits().eq(self.fbc_fifo_font.dout)
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]
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self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
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wishbone_fsm.act("Reset",
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NextValue(bus.ack, 0),
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NextState("Idle"))
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wishbone_fsm.act("Idle",
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self.fbc_fifo_font.we.eq(0),
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If(bus.cyc & bus.stb & bus.we & ~bus.ack, #write
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Case(bus.adr[0:12], { # the thirteenth bit is to match the FBC but not the TEC
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"default": [ ],
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# 0: fbc_config R/O
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1: [ NextValue(fbc_mode, bus.dat_w) ],
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2: [ NextValue(fbc_clip, bus.dat_w) ],
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# 3: <nothing>, pad2
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4: [ # NextValue(fbc_s, bus.dat_w)
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], # 0x010
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# 5: fbc_draw R/O
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# 6: fbc_blit R/O
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7: [ self.fbc_fifo_font.we.eq(1),
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fbc_fifo_font_in.font.eq(bus.dat_w),
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fbc_fifo_font_in.x0.eq(fbc_x[0]),
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fbc_fifo_font_in.x1.eq(fbc_x[1]),
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fbc_fifo_font_in.y0.eq(fbc_y[0]),
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NextValue(fbc_x[0], fbc_x[0] + fbc_incx),
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NextValue(fbc_x[1], fbc_x[1] + fbc_incx),
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NextValue(fbc_y[0], fbc_y[0] + fbc_incy),
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#NextValue(fbc_y[1], fbc_y[1] + fbc_incy),
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],
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# 8-31: <nothing>, pad3
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32: [ NextValue(fbc_x[0], bus.dat_w) ],
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33: [ NextValue(fbc_y[0], bus.dat_w) ],
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#34: presumably fbc_z0
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36: [ NextValue(fbc_x[1], bus.dat_w) ],
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37: [ NextValue(fbc_y[1], bus.dat_w) ],
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#38: presumably fbc_z1
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40: [ NextValue(fbc_x[2], bus.dat_w) ],
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41: [ NextValue(fbc_y[2], bus.dat_w) ],
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#42: presumably fbc_z2
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44: [ NextValue(fbc_x[3], bus.dat_w) ],
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45: [ NextValue(fbc_y[3], bus.dat_w) ],
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#46: presumably fbc_z3
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48: [ NextValue(fbc_offx, bus.dat_w) ],
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49: [ NextValue(fbc_offy, bus.dat_w) ],
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52: [ NextValue(fbc_incx, bus.dat_w) ],
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53: [ NextValue(fbc_incy, bus.dat_w) ],
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# 54-55: pad81
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56: [ NextValue(fbc_clipminx, bus.dat_w) ],
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57: [ NextValue(fbc_clipminy, bus.dat_w) ],
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# 58-59: pad9
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60: [ NextValue(fbc_clipmaxx, bus.dat_w) ],
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61: [ NextValue(fbc_clipmaxy, bus.dat_w) ],
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# 62-63: pad10
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64: [ NextValue(fbc_fg, bus.dat_w) ],
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65: [ NextValue(fbc_bg, bus.dat_w) ],
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66: [ NextValue(fbc_alu, bus.dat_w) ],
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67: [ NextValue(fbc_pm, bus.dat_w) ], # 67: planemask reg
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# 68: pixelmask reg
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# 69-70: <nothing>
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# 71: pattalign reg
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# 72-79: pattern0-7
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# 80-543: big empty space ?
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# 544-546, 548-550: itri[abs,rel][xyz]
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# 560-562, 564-566: iquad[abs,rel][xyz]
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576: [ NextValue(fbc_arectx_prev, fbc_arectx), # 900
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NextValue(fbc_arectx, bus.dat_w),
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],
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577: [ NextValue(fbc_arecty_prev, fbc_arecty),
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NextValue(fbc_arecty, bus.dat_w),
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],
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# 578: fbc_arectz
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# 579: <nothing>
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# 580-582: fbc_relrect[xyz] -> update absolute
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580: [ NextValue(fbc_arectx_prev, fbc_arectx),
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NextValue(fbc_arectx, fbc_arectx + bus.dat_w[0:COORD_BITS]),
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],
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581: [ NextValue(fbc_arecty_prev, fbc_arecty),
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NextValue(fbc_arecty, fbc_arecty + bus.dat_w[0:COORD_BITS]),
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],
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# 600-601: fbc_arect[xy]next, not directly writable
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602: [ NextValue(fbc_r5_cmd, bus.dat_w) ],
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604: [ NextValue(fbc_r5_status[0], bus.dat_w) ], # 0x970
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605: [ NextValue(fbc_r5_status[1], bus.dat_w) ], # 0x971
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606: [ NextValue(fbc_r5_status[2], bus.dat_w) ], # 0x972
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607: [ NextValue(fbc_r5_status[3], bus.dat_w) ], # 0x973
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# 608: fbc_next_font, R/O
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}),
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NextValue(bus.ack, 1),
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).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
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Case(bus.adr[0:12], { # the thirteenth bit is to match the FBC but not the TEC
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"default": [ NextValue(bus.dat_r, 0xDEADBEEF) ],
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0: [ NextValue(bus.dat_r, fbc_config) ],
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1: [ NextValue(bus.dat_r, fbc_mode) ],
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2: [ NextValue(bus.dat_r, fbc_clip) ],
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# 3: pad2
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4: [ NextValue(bus.dat_r, fbc_s),
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#NextValue(bus.dat_r, Replicate(fbc_s[GX_INPROGRESS_BIT] | fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable, 32)) ],
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],
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# 5: fbc_draw R/O -> start a "draw" on R
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5: [ NextValue(fbc_do_draw, ~fbc_s[GX_INPROGRESS_BIT]), # ignore command while working
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NextValue(bus.dat_r, fbc_s), # FIXME, returns the FULL and INPROGRESS bit only
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_do_draw | fbc_do_blit),
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_s[GX_INPROGRESS_BIT]),
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],
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# 6: fbc_blit R/O -> start a "blit" on R
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6: [ NextValue(fbc_do_blit, ~fbc_s[GX_INPROGRESS_BIT]), # ignore command while working
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NextValue(bus.dat_r, fbc_s), # FIXME, returns the FULL and INPROGRESS bit only
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_do_draw | fbc_do_blit),
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#NextValue(draw_blit_overflow, draw_blit_overflow | fbc_s[GX_INPROGRESS_BIT]),
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],
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# 7: fbc_font W/O -> start a "font" on W
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# 8-31: pad3
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32: [ NextValue(bus.dat_r, fbc_x[0]) ], # 0x080
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33: [ NextValue(bus.dat_r, fbc_y[0]) ],
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36: [ NextValue(bus.dat_r, fbc_x[1]) ], # 0x090
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37: [ NextValue(bus.dat_r, fbc_y[1]) ],
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40: [ NextValue(bus.dat_r, fbc_x[2]) ], # 0x0a0
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41: [ NextValue(bus.dat_r, fbc_y[2]) ],
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44: [ NextValue(bus.dat_r, fbc_x[3]) ], # 0x0b0
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45: [ NextValue(bus.dat_r, fbc_y[3]) ], # 0x0b4
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48: [ NextValue(bus.dat_r, fbc_offx) ], # 0x0c0
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49: [ NextValue(bus.dat_r, fbc_offy) ],
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52: [ NextValue(bus.dat_r, fbc_incx) ], # 0x0d0
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53: [ NextValue(bus.dat_r, fbc_incy) ],
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# 54-55: pad81
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56: [ NextValue(bus.dat_r, fbc_clipminx) ], # 0x0e0
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57: [ NextValue(bus.dat_r, fbc_clipminy) ],
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# 58-59: pad9
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60: [ NextValue(bus.dat_r, fbc_clipmaxx) ], # 0x0f0
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61: [ NextValue(bus.dat_r, fbc_clipmaxy) ],
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# 62-63: pad10
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64: [ NextValue(bus.dat_r, fbc_fg) ], # 0x100
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65: [ NextValue(bus.dat_r, fbc_bg) ], # 0x104
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66: [ NextValue(bus.dat_r, fbc_alu) ], # 0x108
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67: [ NextValue(bus.dat_r, fbc_pm) ], # 0x10c # planemask
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#68: pixelmask (written to 0xFFFFFFFF by 510-2325 prom)
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#72-79: patterns (written to 0xFFFFFFFF by 510-2325 prom)
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576: [ NextValue(bus.dat_r, fbc_arectx),
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],
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577: [ NextValue(bus.dat_r, fbc_arecty),
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],
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600: [ NextValue(bus.dat_r, fbc_arectx_prev), # 0x960
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],
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601: [ NextValue(bus.dat_r, fbc_arecty_prev),
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],
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602: [ NextValue(bus.dat_r, fbc_r5_cmd), # 0x968
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],
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# 603
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604: [ NextValue(bus.dat_r, fbc_r5_status[0]), # 0x970
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],
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605: [ NextValue(bus.dat_r, fbc_r5_status[1]), # 0x971
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],
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606: [ NextValue(bus.dat_r, fbc_r5_status[2]), # 0x972
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],
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607: [ NextValue(bus.dat_r, fbc_r5_status[3]), # 0x973
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],
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608: [ NextValue(bus.dat_r, fbc_next_font),
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],
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609: [ NextValue(bus.dat_r, fbc_next_x0),
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],
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610: [ NextValue(bus.dat_r, fbc_next_x1),
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],
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611: [ NextValue(bus.dat_r, fbc_next_y0),
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],
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}),
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NextValue(bus.ack, 1),
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).Else(
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NextValue(bus.ack, 0),
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)
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)
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# also in blit.c, for r5-cmd
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FUN_MASK = 0x0000000F
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FUN_DRAW = 0x00000001
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FUN_BLIT = 0x00000002
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FUN_FONT = 0x40000004 # include FUN_FONT_NEXT_RDY_BIT
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FUN_DONE_BIT = 31
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FUN_FONT_NEXT_RDY_BIT = 30
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FUN_FONT_NEXT_REQ_BIT = 29
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FUN_FONT_NEXT_DONE_BIT = 28
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# to hold the Vex in reset
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# could be sent to fbc_s[GX_INPROGRESS_BIT] ?
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local_reset = Signal(reset = 1)
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#timeout_rst = 0xFFFFFFF
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#timeout = Signal(28, reset = timeout_rst)
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#pad_SBUS_DATA_OE_LED = platform.request("SBUS_DATA_OE_LED")
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#self.comb += pad_SBUS_DATA_OE_LED.eq(~local_reset)
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_r5_cmd[1]) # blitting
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_pm != 0) # planemasking
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fifo_overflow)
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_s[GX_INPROGRESS_BIT])
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_s[GX_INPROGRESS_BIT])
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#self.comb += pad_SBUS_DATA_OE_LED.eq(draw_blit_overflow)
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_draw & fbc_s[GX_INPROGRESS_BIT])
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#self.comb += pad_SBUS_DATA_OE_LED.eq(fbc_do_blit & fbc_s[GX_INPROGRESS_BIT])
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#self.sync += fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable)
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#self.sync += fbc_s[27].eq(fbc_do_draw)
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#self.sync += fbc_s[26].eq(fbc_do_blit)
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#self.sync += fbc_s[25].eq(self.fbc_fifo_font.readable)
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#self.sync += fbc_s[24].eq(~local_reset)
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#self.sync += fbc_s[0].eq(draw_blit_overflow)
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#fbc_s[GX_FULL_BIT].eq(fbc_do_draw | fbc_do_blit | self.fbc_fifo_font.readable)
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self.sync += [
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self.fbc_fifo_font.re.eq(0),
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If(fbc_r5_cmd[FUN_DONE_BIT],
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fbc_r5_cmd.eq(0),
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fbc_s[GX_INPROGRESS_BIT].eq(0),
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fbc_s[GX_FULL_BIT].eq(0),
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local_reset.eq(1),
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#timeout.eq(timeout_rst),
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).Elif(self.fbc_fifo_font.readable & fbc_s[GX_INPROGRESS_BIT] & fbc_r5_cmd[FUN_FONT_NEXT_REQ_BIT] & (fbc_r5_cmd[0:4] == 0x4),
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# the font code request the next line, and one is available: give it
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self.fbc_fifo_font.re.eq(1),
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fbc_next_font.eq(fbc_fifo_font_out.font),
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fbc_next_x0.eq(fbc_fifo_font_out.x0),
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fbc_next_x1.eq(fbc_fifo_font_out.x1),
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fbc_next_y0.eq(fbc_fifo_font_out.y0),
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fbc_r5_cmd[FUN_FONT_NEXT_REQ_BIT].eq(0),
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fbc_r5_cmd[FUN_FONT_NEXT_RDY_BIT].eq(1),
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#timeout.eq(timeout_rst),
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).Elif(~self.fbc_fifo_font.readable & fbc_s[GX_INPROGRESS_BIT] & fbc_r5_cmd[FUN_FONT_NEXT_REQ_BIT] & (fbc_r5_cmd[0:4] == 0x4),
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# the font code request the next line, but none is available; stop
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fbc_r5_cmd[FUN_FONT_NEXT_REQ_BIT].eq(0),
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fbc_r5_cmd[FUN_FONT_NEXT_DONE_BIT].eq(1),
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#timeout.eq(timeout_rst),
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).Elif(self.fbc_fifo_font.readable & ~fbc_s[GX_INPROGRESS_BIT],
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self.fbc_fifo_font.re.eq(1),
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fbc_next_font.eq(fbc_fifo_font_out.font),
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fbc_next_x0.eq(fbc_fifo_font_out.x0),
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fbc_next_x1.eq(fbc_fifo_font_out.x1),
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fbc_next_y0.eq(fbc_fifo_font_out.y0),
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fbc_r5_cmd.eq(FUN_FONT), # includes FUN_FONT_NEXT_RDY_BIT
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(fbc_do_draw & ~fbc_s[GX_INPROGRESS_BIT],
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fbc_do_draw.eq(0),
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fbc_r5_cmd.eq(FUN_DRAW),
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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).Elif(fbc_do_blit & ~fbc_s[GX_INPROGRESS_BIT],
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fbc_do_blit.eq(0),
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fbc_r5_cmd.eq(FUN_BLIT),
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fbc_s[GX_INPROGRESS_BIT].eq(1),
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fbc_s[GX_FULL_BIT].eq(1),
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local_reset.eq(0),
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#timeout.eq(timeout_rst),
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##self.cg6_blit.go.eq(1),
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)
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#).Elif((timeout == 0) & fbc_s[GX_INPROGRESS_BIT], # OUPS
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# fbc_r5_cmd.eq(0),
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# fbc_s[GX_INPROGRESS_BIT].eq(0),
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# fbc_s[GX_FULL_BIT].eq(0),
|
|
# local_reset.eq(1),
|
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# timeout.eq(timeout_rst),
|
|
#),
|
|
#If(fbc_s[GX_INPROGRESS_BIT] & (timeout != 0),
|
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# timeout.eq(timeout - 1)
|
|
#)
|
|
]
|
|
|
|
self.ibus = ibus = wishbone.Interface()
|
|
#self.dbus = dbus = wishbone.Interface()
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|
vex_reset = Signal()
|
|
|
|
dbus_raw = wishbone.Interface(data_width=128, adr_width=28) # wide interface from the Vex, master
|
|
dbus_sys = wishbone.Interface(data_width=128, adr_width=28) # wide interface to system wishbone
|
|
dbus_mem = wishbone.Interface(data_width=128, adr_width=28) # wide interface for direct memory access
|
|
self.dbus = dbus_sys
|
|
|
|
self.comb += [
|
|
If((dbus_raw.adr[24:28] == 0x8),
|
|
dbus_sys.cyc.eq(0),
|
|
dbus_sys.stb.eq(0),
|
|
dbus_mem.cyc.eq(dbus_raw.cyc),
|
|
dbus_mem.stb.eq(dbus_raw.stb),
|
|
|
|
dbus_raw.ack.eq(dbus_mem.ack),
|
|
dbus_raw.err.eq(dbus_mem.err),
|
|
dbus_raw.dat_r.eq(dbus_mem.dat_r),
|
|
).Else(
|
|
dbus_sys.cyc.eq(dbus_raw.cyc),
|
|
dbus_sys.stb.eq(dbus_raw.stb),
|
|
dbus_mem.cyc.eq(0),
|
|
dbus_mem.stb.eq(0),
|
|
|
|
dbus_raw.ack.eq(dbus_sys.ack),
|
|
dbus_raw.err.eq(dbus_sys.err),
|
|
dbus_raw.dat_r.eq(dbus_sys.dat_r),
|
|
),
|
|
dbus_sys.dat_w.eq(dbus_raw.dat_w),
|
|
dbus_mem.dat_w.eq(dbus_raw.dat_w),
|
|
dbus_sys.we.eq(dbus_raw.we),
|
|
dbus_mem.we.eq(dbus_raw.we),
|
|
dbus_sys.adr.eq(dbus_raw.adr),
|
|
dbus_mem.adr.eq(dbus_raw.adr),
|
|
dbus_sys.sel.eq(dbus_raw.sel),
|
|
dbus_mem.sel.eq(dbus_raw.sel),
|
|
dbus_sys.cti.eq(dbus_raw.cti),
|
|
dbus_mem.cti.eq(dbus_raw.cti),
|
|
dbus_sys.bte.eq(dbus_raw.bte),
|
|
dbus_mem.bte.eq(dbus_raw.bte),
|
|
]
|
|
|
|
# now connect the memory
|
|
|
|
# memory port
|
|
port = soc.sdram.crossbar.get_port()
|
|
assert(port.data_width == 128)
|
|
self.submodules.wb2native = LiteDRAMWishbone2Native(
|
|
wishbone = dbus_mem,
|
|
port = port,
|
|
base_address = soc.bus.regions["main_ram"].origin
|
|
)
|
|
|
|
self.comb += vex_reset.eq(ResetSignal("sys") | local_reset)
|
|
self.specials += Instance(self.get_netlist_name(),
|
|
i_clk = ClockSignal("sys"),
|
|
i_reset = vex_reset,
|
|
o_iBusWishbone_CYC = ibus.cyc,
|
|
o_iBusWishbone_STB = ibus.stb,
|
|
i_iBusWishbone_ACK = ibus.ack,
|
|
o_iBusWishbone_WE = ibus.we,
|
|
o_iBusWishbone_ADR = ibus.adr,
|
|
i_iBusWishbone_DAT_MISO = ibus.dat_r,
|
|
o_iBusWishbone_DAT_MOSI = ibus.dat_w,
|
|
o_iBusWishbone_SEL = ibus.sel,
|
|
i_iBusWishbone_ERR = ibus.err,
|
|
o_iBusWishbone_CTI = ibus.cti,
|
|
o_iBusWishbone_BTE = ibus.bte,
|
|
o_dBusWishbone_CYC = dbus_raw.cyc,
|
|
o_dBusWishbone_STB = dbus_raw.stb,
|
|
i_dBusWishbone_ACK = dbus_raw.ack,
|
|
o_dBusWishbone_WE = dbus_raw.we,
|
|
o_dBusWishbone_ADR = dbus_raw.adr,
|
|
i_dBusWishbone_DAT_MISO = dbus_raw.dat_r,
|
|
o_dBusWishbone_DAT_MOSI = dbus_raw.dat_w,
|
|
o_dBusWishbone_SEL = dbus_raw.sel,
|
|
i_dBusWishbone_ERR = dbus_raw.err,
|
|
o_dBusWishbone_CTI = dbus_raw.cti,
|
|
o_dBusWishbone_BTE = dbus_raw.bte,)
|
|
|
|
self.add_sources(platform)
|
|
|
|
def get_netlist_name(self):
|
|
return "VexRiscv"
|
|
|
|
def add_sources(self, platform):
|
|
platform.add_source("/home/dolbeau/SBusFPGA/sbus-to-ztex-gateware-migen/VexRiscv_FbAccel.v", "verilog")
|