536 lines
25 KiB
Plaintext
536 lines
25 KiB
Plaintext
(pcb "/home/dolbeau/SPARC/SBusFPGA/VGA222-PMOD/VGA222-PMOD.dsn"
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "KiCad's Pcbnew")
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(host_version "5.0.2+dfsg1-1~bpo9+1")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 150000 -75177 128000 -75177 128000 -69177 100000 -69177
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100000 -50000 128000 -50000 128000 -44000 150000 -44000 150000 -75177)
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)
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(plane GND (polygon B.Cu 0 100500 -50500 128500 -50500 128500 -44500 149500 -44500
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149500 -74500 128500 -74500 128500 -68500 100500 -68500 100500 -50500))
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(via "Via[0-1]_800:400_um")
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(rule
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(width 250)
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(clearance 200.1)
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(clearance 200.1 (type default_smd))
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(clearance 50 (type smd_smd))
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)
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)
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(placement
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(component Capacitor_THT:CP_Radial_D6.3mm_P2.50mm
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(place C3 128000 -53500 front 180 (PN "1nF (250V)"))
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)
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(component Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical
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(place R25 120500 -61500 front 180 (PN 1k))
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(place R19 120500 -57500 front 180 (PN 1k))
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(place R13 120500 -53500 front 180 (PN 1k))
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(place R9 126500 -67000 front 90 (PN "1M (5% .25W)"))
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(place R10 118500 -66000 front 0 (PN 100))
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)
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(component Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical::1
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(place R24 114000 -60000 front 180 (PN 510))
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(place R18 114000 -56000 front 180 (PN 510))
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(place R12 114000 -52000 front 180 (PN 510))
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(place R11 112000 -67000 front 0 (PN 100))
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)
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(component For_SeeedStudio:L77HDE15SD1CH4RHNVGA
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(place J1 138600 -72080 front 90 (PN DB15_Female_HighDensity_MountingHoles))
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)
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(component Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Horizontal
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(place J2 106604 -66129 front 180 (PN Conn_02x06_Odd_Even))
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)
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)
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(library
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(outline (path signal 120 -2250.24 1839 -1620.24 1839))
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(outline (path signal 120 -1935.24 2154 -1935.24 1524))
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(pin Rect[A]Pad_1600x1600_um 1 0 0)
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(pin Round[A]Pad_1600_um 2 2500 0)
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)
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(image Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical
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(outline (path signal 100 1250 0 1174.62 -427.525 957.556 -803.485 625 -1082.53
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-1174.62 -427.525 -1250 0 -1174.62 427.525 -957.556 803.485
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1174.62 427.525 1250 0))
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(outline (path signal 120 1370 0 1287.38 -468.568 1049.48 -880.619 685 -1186.45
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-1287.38 -468.568 -1370 0 -1287.38 468.568 -1049.48 880.619
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-685 1186.45 -237.898 1349.19 237.898 1349.19 685 1186.45
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(outline (path signal 100 0 0 2540 0))
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(outline (path signal 50 3590 -1500 3590 1500))
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(outline (path signal 50 3590 1500 -1500 1500))
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(pin Round[A]Pad_1600_um 1 0 0)
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(pin Oval[A]Pad_1600x1600_um 2 2540 0)
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)
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(image Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P2.54mm_Vertical::1
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(outline (path signal 50 3590 1500 -1500 1500))
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(outline (path signal 50 3590 -1500 3590 1500))
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(outline (path signal 100 0 0 2540 0))
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-625 1082.53 -217.06 1231.01 217.06 1231.01 625 1082.53 957.556 803.485
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1174.62 427.525 1250 0))
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(pin Oval[A]Pad_1600x1600_um 2 2540 0)
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(pin Round[A]Pad_1600_um 1 0 0)
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)
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(image For_SeeedStudio:L77HDE15SD1CH4RHNVGA
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(outline (path signal 150 -2920 4000 27920 4000))
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(outline (path signal 150 0 -11430 25000 -11430))
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(pin Round[A]Pad_1500_um 15 7670 -2540)
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(pin Round[A]Pad_1500_um 14 9960 -2540)
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(pin Round[A]Pad_1500_um 13 12254 -2540)
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(pin Round[A]Pad_1500_um 12 14540 -2540)
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(pin Round[A]Pad_1500_um 11 16830 -2540)
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(pin Round[A]Pad_1500_um 10 8810 0)
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(pin Round[A]Pad_1500_um 9 11100 0)
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(pin Round[A]Pad_1500_um 8 13390 0)
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(pin Round[A]Pad_1500_um 7 15680 0)
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(pin Round[A]Pad_1500_um 6 17970 0)
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(pin Round[A]Pad_1500_um 5 7670 2540)
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(pin Round[A]Pad_1500_um 4 9960 2540)
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(pin Round[A]Pad_1500_um 3 12250 2540)
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(pin Round[A]Pad_1500_um 2 14540 2540)
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(pin Round[A]Pad_1500_um 1 16830 2540)
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(pin Round[A]Pad_3500_um 0 25000 0)
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(pin Round[A]Pad_3500_um 0@1 0 0)
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)
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(image Connector_PinHeader_2.54mm:PinHeader_2x06_P2.54mm_Horizontal
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(outline (path signal 100 6580 -7940 12580 -7940))
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(outline (path signal 100 -320 -9840 4040 -9840))
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(outline (path signal 100 -320 -9840 -320 -10480))
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(outline (path signal 100 -320 -10480 4040 -10480))
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(outline (path signal 100 6580 -9840 12580 -9840))
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(outline (path signal 100 12580 -9840 12580 -10480))
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(outline (path signal 100 6580 -10480 12580 -10480))
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(outline (path signal 100 -320 -12380 4040 -12380))
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(outline (path signal 100 -320 -12380 -320 -13020))
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(outline (path signal 100 -320 -13020 4040 -13020))
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(outline (path signal 100 6580 -12380 12580 -12380))
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(outline (path signal 100 12580 -12380 12580 -13020))
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(outline (path signal 100 6580 -13020 12580 -13020))
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(outline (path signal 120 3980 1330 3980 -14030))
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(outline (path signal 120 3980 -14030 6640 -14030))
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(outline (path signal 120 6640 -14030 6640 1330))
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(outline (path signal 120 6640 1330 3980 1330))
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(outline (path signal 120 6640 380 12640 380))
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(outline (path signal 120 12640 380 12640 -380))
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(outline (path signal 120 12640 -380 6640 -380))
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(outline (path signal 120 6640 320 12640 320))
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(outline (path signal 120 6640 200 12640 200))
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(outline (path signal 120 6640 80 12640 80))
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(outline (path signal 120 6640 -40 12640 -40))
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(outline (path signal 120 6640 -160 12640 -160))
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(outline (path signal 120 6640 -280 12640 -280))
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(outline (path signal 120 3582.93 380 3980 380))
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(outline (path signal 120 3582.93 -380 3980 -380))
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(outline (path signal 120 1110 380 1497.07 380))
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(outline (path signal 120 1110 -380 1497.07 -380))
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(outline (path signal 120 3980 -1270 6640 -1270))
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(outline (path signal 120 6640 -2160 12640 -2160))
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(outline (path signal 120 12640 -2160 12640 -2920))
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(outline (path signal 120 12640 -2920 6640 -2920))
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(outline (path signal 120 3582.93 -2160 3980 -2160))
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(outline (path signal 120 3582.93 -2920 3980 -2920))
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(outline (path signal 120 1042.93 -2160 1497.07 -2160))
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(outline (path signal 120 1042.93 -2920 1497.07 -2920))
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(outline (path signal 120 3980 -3810 6640 -3810))
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(outline (path signal 120 6640 -4700 12640 -4700))
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(outline (path signal 120 12640 -4700 12640 -5460))
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(outline (path signal 120 12640 -5460 6640 -5460))
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(outline (path signal 120 3582.93 -4700 3980 -4700))
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(outline (path signal 120 3582.93 -5460 3980 -5460))
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(outline (path signal 120 1042.93 -4700 1497.07 -4700))
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(outline (path signal 120 1042.93 -5460 1497.07 -5460))
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(outline (path signal 120 3980 -6350 6640 -6350))
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(outline (path signal 120 6640 -7240 12640 -7240))
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(outline (path signal 120 12640 -7240 12640 -8000))
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(outline (path signal 120 12640 -8000 6640 -8000))
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(outline (path signal 120 3582.93 -7240 3980 -7240))
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(outline (path signal 120 3582.93 -8000 3980 -8000))
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(outline (path signal 120 1042.93 -7240 1497.07 -7240))
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(outline (path signal 120 1042.93 -8000 1497.07 -8000))
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(outline (path signal 120 3980 -8890 6640 -8890))
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(outline (path signal 120 6640 -9780 12640 -9780))
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(outline (path signal 120 12640 -9780 12640 -10540))
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(outline (path signal 120 12640 -10540 6640 -10540))
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(outline (path signal 120 3582.93 -9780 3980 -9780))
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(outline (path signal 120 3582.93 -10540 3980 -10540))
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(outline (path signal 120 1042.93 -9780 1497.07 -9780))
|
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(outline (path signal 120 1042.93 -10540 1497.07 -10540))
|
|
(outline (path signal 120 3980 -11430 6640 -11430))
|
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(outline (path signal 120 6640 -12320 12640 -12320))
|
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(outline (path signal 120 12640 -12320 12640 -13080))
|
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(outline (path signal 120 12640 -13080 6640 -13080))
|
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(outline (path signal 120 3582.93 -12320 3980 -12320))
|
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(outline (path signal 120 3582.93 -13080 3980 -13080))
|
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(outline (path signal 120 1042.93 -12320 1497.07 -12320))
|
|
(outline (path signal 120 1042.93 -13080 1497.07 -13080))
|
|
(outline (path signal 120 -1270 0 -1270 1270))
|
|
(outline (path signal 120 -1270 1270 0 1270))
|
|
(outline (path signal 50 -1800 1800 -1800 -14500))
|
|
(outline (path signal 50 -1800 -14500 13100 -14500))
|
|
(outline (path signal 50 13100 -14500 13100 1800))
|
|
(outline (path signal 50 13100 1800 -1800 1800))
|
|
(pin Rect[A]Pad_1700x1700_um 1 0 0)
|
|
(pin Oval[A]Pad_1700x1700_um 2 2540 0)
|
|
(pin Oval[A]Pad_1700x1700_um 3 0 -2540)
|
|
(pin Oval[A]Pad_1700x1700_um 4 2540 -2540)
|
|
(pin Oval[A]Pad_1700x1700_um 5 0 -5080)
|
|
(pin Oval[A]Pad_1700x1700_um 6 2540 -5080)
|
|
(pin Oval[A]Pad_1700x1700_um 7 0 -7620)
|
|
(pin Oval[A]Pad_1700x1700_um 8 2540 -7620)
|
|
(pin Oval[A]Pad_1700x1700_um 9 0 -10160)
|
|
(pin Oval[A]Pad_1700x1700_um 10 2540 -10160)
|
|
(pin Oval[A]Pad_1700x1700_um 11 0 -12700)
|
|
(pin Oval[A]Pad_1700x1700_um 12 2540 -12700)
|
|
)
|
|
(padstack Round[A]Pad_1500_um
|
|
(shape (circle F.Cu 1500))
|
|
(shape (circle B.Cu 1500))
|
|
(attach off)
|
|
)
|
|
(padstack Round[A]Pad_1600_um
|
|
(shape (circle F.Cu 1600))
|
|
(shape (circle B.Cu 1600))
|
|
(attach off)
|
|
)
|
|
(padstack Round[A]Pad_3500_um
|
|
(shape (circle F.Cu 3500))
|
|
(shape (circle B.Cu 3500))
|
|
(attach off)
|
|
)
|
|
(padstack Oval[A]Pad_1600x1600_um
|
|
(shape (path F.Cu 1600 0 0 0 0))
|
|
(shape (path B.Cu 1600 0 0 0 0))
|
|
(attach off)
|
|
)
|
|
(padstack Oval[A]Pad_1700x1700_um
|
|
(shape (path F.Cu 1700 0 0 0 0))
|
|
(shape (path B.Cu 1700 0 0 0 0))
|
|
(attach off)
|
|
)
|
|
(padstack Rect[A]Pad_1600x1600_um
|
|
(shape (rect F.Cu -800 -800 800 800))
|
|
(shape (rect B.Cu -800 -800 800 800))
|
|
(attach off)
|
|
)
|
|
(padstack Rect[A]Pad_1700x1700_um
|
|
(shape (rect F.Cu -850 -850 850 850))
|
|
(shape (rect B.Cu -850 -850 850 850))
|
|
(attach off)
|
|
)
|
|
(padstack "Via[0-1]_800:400_um"
|
|
(shape (circle F.Cu 800))
|
|
(shape (circle B.Cu 800))
|
|
(attach off)
|
|
)
|
|
)
|
|
(network
|
|
(net GND
|
|
(pins C3-2 R9-2 J1-10 J1-8 J1-7 J1-6 J1-5 J2-3 J2-4)
|
|
)
|
|
(net +3V3
|
|
(pins J2-1 J2-2)
|
|
)
|
|
(net B2
|
|
(pins R25-2 J2-8)
|
|
)
|
|
(net B3
|
|
(pins R24-2 J2-7)
|
|
)
|
|
(net G2
|
|
(pins R19-2 J2-10)
|
|
)
|
|
(net G3
|
|
(pins R18-2 J2-9)
|
|
)
|
|
(net R2
|
|
(pins R13-2 J2-12)
|
|
)
|
|
(net R3
|
|
(pins R12-2 J2-11)
|
|
)
|
|
(net VS
|
|
(pins R10-1 J2-5)
|
|
)
|
|
(net HS
|
|
(pins R11-1 J2-6)
|
|
)
|
|
(net VGA_R
|
|
(pins R13-1 R12-1 J1-1)
|
|
)
|
|
(net VGA_HS
|
|
(pins R10-2 J1-13)
|
|
)
|
|
(net VGA_VS
|
|
(pins R11-2 J1-14)
|
|
)
|
|
(net VGA_B
|
|
(pins R25-1 R24-1 J1-3)
|
|
)
|
|
(net VGA_G
|
|
(pins R19-1 R18-1 J1-2)
|
|
)
|
|
(net "Net-(J1-Pad15)"
|
|
(pins J1-15)
|
|
)
|
|
(net "Net-(J1-Pad12)"
|
|
(pins J1-12)
|
|
)
|
|
(net "Net-(J1-Pad11)"
|
|
(pins J1-11)
|
|
)
|
|
(net "Net-(J1-Pad9)"
|
|
(pins J1-9)
|
|
)
|
|
(net "Net-(J1-Pad4)"
|
|
(pins J1-4)
|
|
)
|
|
(net "Net-(C3-Pad1)"
|
|
(pins C3-1 R9-1 J1-0 J1-0@1)
|
|
)
|
|
(class kicad_default "" +3V3 B2 B3 G2 G3 GND HS "Net-(C3-Pad1)" "Net-(J1-Pad11)"
|
|
"Net-(J1-Pad12)" "Net-(J1-Pad15)" "Net-(J1-Pad4)" "Net-(J1-Pad9)" R2
|
|
R3 VGA_B VGA_G VGA_HS VGA_R VGA_VS VS
|
|
(circuit
|
|
(use_via Via[0-1]_800:400_um)
|
|
)
|
|
(rule
|
|
(width 250)
|
|
(clearance 200.1)
|
|
)
|
|
)
|
|
)
|
|
(wiring
|
|
(wire (path B.Cu 500 138600 -72080 145600 -65080 145600 -54080 138600 -47080)(net "Net-(C3-Pad1)")(type protect))
|
|
(wire (path B.Cu 500 128000 -52450 128000 -53500)(net "Net-(C3-Pad1)")(type protect))
|
|
(wire (path B.Cu 500 133370 -47080 128000 -52450)(net "Net-(C3-Pad1)")(type protect))
|
|
(wire (path B.Cu 500 138600 -47080 133370 -47080)(net "Net-(C3-Pad1)")(type protect))
|
|
(wire (path B.Cu 500 131580 -72080 126500 -67000)(net "Net-(C3-Pad1)")(type protect))
|
|
(wire (path B.Cu 500 138600 -72080 131580 -72080)(net "Net-(C3-Pad1)")(type protect))
|
|
)
|
|
)
|