54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
/* $NetBSD$ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RDFPGA_H_
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#define _RDFPGA_H_
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struct rdfpga_softc {
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device_t sc_dev; /* us as a device */
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u_int sc_rev; /* revision */
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int sc_node; /* PROM node ID */
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int sc_burst; /* DVMA burst size in effect */
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bus_space_tag_t sc_bustag; /* bus tag */
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bus_space_handle_t sc_bhregs; /* bus handle */
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//void * sc_buffer; /* VA of the registers */
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int sc_bufsiz; /* Size of buffer */
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int attached; /* 1: in use by `le' device */
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};
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#define RDFPGA_REG_LED 0x0
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#define RDFPGA_REG_H 0x40
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#define RDFPGA_REG_C 0x50
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#define RDFPGA_REG_I 0x60
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#endif /* _RDFPGA_H_ */
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