1
0
mirror of synced 2026-05-04 15:25:52 +00:00
Files
rdolbeau.SBusFPGA/VGA222-PMOD/VGA222-PMOD-rescue.lib
Romain Dolbeau bd992ad421 add VGA222 Pmod
2021-10-09 11:26:13 +02:00

48 lines
1.5 KiB
Plaintext

EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# VGA222-PMODx-ML-Interface_Ethernet
#
DEF VGA222-PMODx-ML-Interface_Ethernet U 0 20 Y Y 1 F N
F0 "U" -550 950 50 H V L CNN
F1 "VGA222-PMODx-ML-Interface_Ethernet" 200 950 50 H V L CNN
F2 "Package_DFN_QFN:QFN-28-1EP_6x6mm_P0.65mm_EP4.25x4.25mm" 1200 -950 50 H I C CIN
F3 "" 0 0 50 H I C CNN
$FPLIST
QFN*28*1EP*6x6mm*P0.65mm*
$ENDFPLIST
DRAW
S -600 900 600 -900 0 1 10 f
X ~WOL 1 -700 0 100 R 50 50 1 1 O
X RBIAS 10 700 -600 100 L 50 50 1 1 I
X VDDTX 11 700 0 100 L 50 50 1 1 W
X TPOUT- 12 700 -200 100 L 50 50 1 1 O
X TPOUT+ 13 700 -100 100 L 50 50 1 1 O
X VSSTX 14 700 -300 100 L 50 50 1 1 w
X VDDRX 15 700 500 100 L 50 50 1 1 W
X VDDPLL 16 100 1000 100 D 50 50 1 1 W
X VSSPLL 17 100 -1000 100 U 50 50 1 1 W
X VSSOSC 18 -700 -600 100 R 50 50 1 1 W
X OSC1 19 -700 -300 100 R 50 50 1 1 I
X SO 2 -700 500 100 R 50 50 1 1 O
X OSC2 20 -700 -500 100 R 50 50 1 1 O
X VDDOSC 21 -700 -200 100 R 50 50 1 1 W
X LEDB 22 700 700 100 L 50 50 1 1 O
X LEDA 23 700 800 100 L 50 50 1 1 O
X VDD 24 -100 1000 100 D 50 50 1 1 W
X VCAP 25 700 -800 100 L 50 50 1 1 I
X VSS 26 -100 -1000 100 U 50 50 1 1 W
X CLKOUT 27 -700 -800 100 R 50 50 1 1 O
X ~INT 28 -700 100 100 R 50 50 1 1 O
X SI 3 -700 600 100 R 50 50 1 1 I
X SCK 4 -700 400 100 R 50 50 1 1 I
X ~CS 5 -700 300 100 R 50 50 1 1 I
X ~RESET 6 -700 800 100 R 50 50 1 1 I
X VSSRX 7 700 200 100 L 50 50 1 1 w
X TPIN- 8 700 300 100 L 50 50 1 1 I
X TPIN+ 9 700 400 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library