Romain Dolbeau 9e2a84d098 more V1.2

2021-09-06 09:43:16 -04:00

..

engine_code

option to disable upper lane in AES/GCM isntructions; disable them in the code

2021-09-05 09:56:14 -04:00

engine.py

Loops are easier to read...

2021-09-06 03:03:04 -04:00

forth_to_migen_rom.sh

prom

2021-07-14 05:14:19 -04:00

neorv32_trng_patched.vhd

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

netbsd_csr.h

preliminary work on AES256-GCM in the Engine

2021-09-04 05:52:11 -04:00

prom_csr.fth

add an SBus statistics module (and discover a bug in the sbus lave timeouts and a lot of slave re-run)

2021-08-21 07:41:02 -04:00

prom_migen.bth

prom

2021-07-14 05:14:19 -04:00

prom_migen.fth

add an SBus statistics module (and discover a bug in the sbus lave timeouts and a lot of slave re-run)

2021-08-21 07:41:02 -04:00

sbus_to_fpga_blk_dma.py

Enable everything (using a Wishbone Crossbar instead of a Shared), some changes to Sbus timeouts, seems that everything play nice together now, also change Engine code to need fewer inputs

2021-08-22 03:54:00 -04:00

sbus_to_fpga_export.py

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

sbus_to_fpga_fsm.py

more V1.2

2021-09-06 09:43:16 -04:00

sbus_to_fpga_fsmstat.py

CSRs don't support CDC... move Engine to sysclk ; also forgot to commit fsmstat

2021-08-22 10:27:28 -04:00

sbus_to_fpga_soc.py

more V1.2

2021-09-06 09:43:16 -04:00

sbus_to_fpga_trng.py

commit the neorv32trgn-based trng

2021-07-20 07:45:51 -04:00

sbusfpga_stat_ctl.c

ioctl on/off switch on stats + ctrl pgm

2021-08-23 04:48:05 -04:00

sdram_csr.fth

prom

2021-07-14 05:14:19 -04:00

sdram_init.fth

prom

2021-07-14 05:14:19 -04:00

ztex213_sbus.py

prelim work for V1.2

2021-09-04 02:07:37 -04:00