105 lines
4.2 KiB
C
105 lines
4.2 KiB
C
/* $NetBSD$ */
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/*-
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* Copyright (c) 2020 Romain Dolbeau <romain@dolbeau.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RDFPGA_H_
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#define _RDFPGA_H_
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struct rdfpga_cryptosession {
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u_int64_t aeskey[4];
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u_int64_t aesiv[2];
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u_int32_t klen; /* bits */
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u_int8_t *sw_kschedule;
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};
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struct rdfpga_softc {
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device_t sc_dev; /* us as a device */
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u_int sc_rev; /* revision */
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int sc_node; /* PROM node ID */
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int sc_burst; /* DVMA burst size in effect */
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bus_space_tag_t sc_bustag; /* bus tag */
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bus_space_handle_t sc_bhregs; /* bus handle */
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//void * sc_buffer; /* VA of the registers */
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int sc_bufsiz; /* Size of buffer */
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bus_dma_tag_t sc_dmatag;
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bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */
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u_int32_t cr_id;
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u_int16_t sid;
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u_int16_t aes_key_refresh;
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u_int8_t aes_key_bits;
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struct rdfpga_cryptosession sessions[16];
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};
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/* ctrl*/
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#define RDFPGA_REG_CTRL_BASE 0x00
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#define RDFPGA_REG_LED (RDFPGA_REG_CTRL_BASE + 0x00)
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#define RDFPGA_REG_AES128_CTRL (RDFPGA_REG_CTRL_BASE + 0x04)
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#define RDFPGA_REG_GCMDMA_ADDR (RDFPGA_REG_CTRL_BASE + 0x08)
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#define RDFPGA_REG_GCMDMA_CTRL (RDFPGA_REG_CTRL_BASE + 0x0C)
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#define RDFPGA_REG_AESDMA_ADDR (RDFPGA_REG_CTRL_BASE + 0x10)
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#define RDFPGA_REG_AESDMA_CTRL (RDFPGA_REG_CTRL_BASE + 0x14)
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#define RDFPGA_REG_AESDMAW_ADDR (RDFPGA_REG_CTRL_BASE + 0x18)
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#define RDFPGA_REG_AESDMAW_CTRL (RDFPGA_REG_CTRL_BASE + 0x1C)
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/* gcm stuff */
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#define RDFPGA_REG_GCM_BASE 0x40
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#define RDFPGA_REG_GCM_H (RDFPGA_REG_GCM_BASE + 0x00) /* 4 regs */
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#define RDFPGA_REG_GCM_C (RDFPGA_REG_GCM_BASE + 0x10) /* 4 regs */
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#define RDFPGA_REG_GCM_I (RDFPGA_REG_GCM_BASE + 0x20) /* 4 regs */
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/* RDFPGA_REG_DMA_CTRL */
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#define RDFPGA_MASK_DMA_CTRL_START 0x80000000
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#define RDFPGA_MASK_DMA_CTRL_BUSY 0x40000000 /* unused */
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#define RDFPGA_MASK_DMA_CTRL_ERR 0x20000000
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/* #define RDFPGA_MASK_DMA_CTRL_WRITE 0x10000000 */
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/* #define RDFPGA_MASK_DMA_CTRL_GCM 0x08000000 */
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/* #define RDFPGA_MASK_DMA_CTRL_AES 0x04000000 */
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#define RDFPGA_MASK_DMA_CTRL_CBC 0x02000000
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#define RDFPGA_MASK_DMA_CTRL_DEC 0x01000000
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#define RDFPGA_MASK_DMA_CTRL_BLKCNT 0x00000FFF
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#define RDFPGA_VAL_DMA_MAX_BLKCNT 4096
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#define RDFPGA_VAL_DMA_MAX_SZ (RDFPGA_VAL_DMA_MAX_BLKCNT*16)
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/* having a go at AES128 */
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#define RDFPGA_REG_AES128_BASE 0xc0
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#define RDFPGA_REG_AES128_KEY (RDFPGA_REG_AES128_BASE + 0x00) /* 8 regs */
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#define RDFPGA_REG_AES128_DATA (RDFPGA_REG_AES128_BASE + 0x20) /* 4 regs */
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#define RDFPGA_REG_AES128_OUT (RDFPGA_REG_AES128_BASE + 0x30) /* 4 regs */
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/* RDFPGA_REG_AES128_CTRL */
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#define RDFPGA_MASK_AES128_START 0x80000000
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#define RDFPGA_MASK_AES128_BUSY 0x40000000
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#define RDFPGA_MASK_AES128_ERR 0x20000000
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#define RDFPGA_MASK_AES128_NEWKEY 0x10000000
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#define RDFPGA_MASK_AES128_CBCMOD 0x08000000
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#define RDFPGA_MASK_AES128_AES256 0x04000000
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#define RDFPGA_MASK_AES128_DEC 0x02000000
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#define RDFPGA_MASK_AES128_GCMPOSTINC 0x01000000
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#endif /* _RDFPGA_H_ */
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