github.com/rdolbeau.VintageBusFPGA_Common
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move Vex cores to common

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This commit is contained in:
Romain Dolbeau 2022-10-31 17:08:53 +01:00
parent 2a3d6a9db0
commit 4b9a7709fb
3 changed files with 13384 additions and 2 deletions
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6691
VexRiscv_GoblinAccel_NuBus.v Normal file
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6691
VexRiscv_GoblinAccel_SBus.v Normal file
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4
goblin_accel.py
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@ -323,11 +323,11 @@ class GoblinAccel(Module): # AutoCSR ?
class GoblinAccelNuBus(GoblinAccel):
def add_sources(self, platform):
platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_NuBus.v", "verilog")
platform.add_source("VintageBusFPGA_Common/VexRiscv_GoblinAccel_NuBus.v", "verilog")
class GoblinAccelSBus(GoblinAccel):
def add_sources(self, platform):
led0 = platform.request("SBUS_DATA_OE_LED")
self.comb += [ led0.eq(~self.local_reset), ]
platform.add_source("/home/dolbeau/NuBusFPGA/nubus-to-ztex-gateware/VexRiscv_GoblinAccel_SBus.v", "verilog")
platform.add_source("VintageBusFPGA_Common/VexRiscv_GoblinAccel_SBus.v", "verilog")