mirror of
https://github.com/rdolbeau/VintageBusFPGA_Common.git
synced 2026-01-11 23:42:48 +00:00
252 lines
14 KiB
Python
252 lines
14 KiB
Python
import os
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from migen import *
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from migen.genlib.fifo import *
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from migen.fhdl.specials import Tristate
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import litex
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from litex.build.generic_platform import *
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from litex.soc.integration.soc import *
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from litex.soc.integration.soc_core import *
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from litedram.modules import MT41J128M16
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from litedram.modules import IS43TR8512B
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from litedram.phy import s7ddrphy
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from litex.soc.cores.video import VideoS7HDMIPHY
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.video import video_timings
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from VintageBusFPGA_Common.goblin_accel import *
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class MacPeriphSoC(SoCCore):
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# Add SDCard -----------------------------------------------------------------------------------
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# WiP
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def add_sdcard_custom(self, name="sdcard", mode="read+write"):
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# Imports.
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from litesdcard.phy import SDPHY
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from litesdcard.core import SDCore
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# Checks.
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assert mode in ["read", "write", "read+write"]
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# Pads.
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sdcard_pads = self.platform.request(name)
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# Core.
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self.check_if_exists("sdphy")
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self.check_if_exists("sdcore")
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self.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
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self.sdcore = SDCore(self.sdphy)
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def __init__(self,
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platform,
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sys_clk_freq,
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csr_paging=0x800, # default is 0x800
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bus_interconnect = "crossbar",
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goblin = False, hdmi = False, goblin_res = "1920x1080@60", use_goblin_alt = True,
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**kwargs):
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print(f"Building MacPeriphSoC")
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kwargs["cpu_type"] = "None"
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kwargs["integrated_sram_size"] = 0
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kwargs["with_uart"] = False
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kwargs["with_timer"] = False
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self.sys_clk_freq = sys_clk_freq
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SoCCore.__init__(self,
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platform = platform,
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sys_clk_freq = sys_clk_freq,
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clk_freq = sys_clk_freq,
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csr_paging = csr_paging, # default is 0x800
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bus_interconnect = bus_interconnect,
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**kwargs)
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if ((not use_goblin_alt) or (not hdmi)):
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from VintageBusFPGA_Common.goblin_fb import goblin_rounded_size, Goblin
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else:
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from VintageBusFPGA_Common.goblin_alt_fb import goblin_rounded_size, GoblinAlt
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if (goblin):
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hres = int(goblin_res.split("@")[0].split("x")[0])
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vres = int(goblin_res.split("@")[0].split("x")[1])
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self.goblin_fb_size = goblin_fb_size = goblin_rounded_size(hres, vres)
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print(f"Reserving {goblin_fb_size} bytes ({goblin_fb_size//1048576} MiB) for the goblin")
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else:
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hres = 0
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vres = 0
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self.goblin_fb_size = goblin_fb_size = 0
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# litex.soc.cores.video.video_timings.update(goblin_timings)
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# Quoting the doc:
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# * Separate address spaces are reserved for processor access to cards in NuBus slots. For a
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# * device in NuBus slot number s, the address space in 32-bit mode begins at address
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# * $Fs00 0000 and continues through the highest address, $FsFF FFFF (where s is a constant in
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# * the range $9 through $E for the Macintosh II, the Macintosh IIx, and the Macintosh IIfx;
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# * $A through $E for the Macintosh Quadra 900; $9 through $B for the Macintosh IIcx;
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# * $C through $E for the Macintosh IIci; $D and $E for the Macintosh Quadra 700; and
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# * $9 for the Macintosh IIsi).
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# the Q650 is $C through $E like the IIci, $E is the one with the PDS.
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# So at best we get 16 MiB in 32-bits mode, unless using "super slot space"
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# in 24 bits it's only one megabyte, $s0 0000 through $sF FFFF
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# they are translated: '$s0 0000-$sF FFFF' to '$Fs00 0000-$Fs0F FFFF' (for s in range $9 through $E)
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# let's assume we have 32-bits mode, this can be requested in the DeclROM apparently
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self.wb_mem_map = wb_mem_map = {
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# master to map the NuBus access to RAM
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"master": 0x00000000, # to 0x3FFFFFFF
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"main_ram": 0x80000000, # not directly reachable from NuBus
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"video_framebuffer": 0x80000000 + 0x10000000 - goblin_fb_size, # Updated later
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# map everything in slot 0, remapped from the real slot in NuBus2Wishbone
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"goblin_mem": 0xF0000000, # up to 8 MiB of FB memory
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#"END OF FIRST MB" : 0xF00FFFFF,
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#"END OF 8 MB": 0xF07FFFFF,
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"goblin_bt" : 0xF0900000, # BT for goblin (regs)
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"goblin_accel" : 0xF0901000, # accel for goblin (regs)
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"goblin_accel_ram" : 0xF0902000, # accel for goblin (scratch ram)
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"stat" : 0xF0903000, # stat
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"goblin_accel_rom" : 0xF0910000, # accel for goblin (rom)
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"goblin_audio_ram" : 0xF0920000, # audio for goblin (RAM buffers)
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"csr" : 0xF0A00000, # CSR
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"pingmaster": 0xF0B00000,
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"ethmac": 0xF0C00000,
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#"spiflash": 0xF0D00000, # testing
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#"config_spiflash": 0xF0D00000, # testing
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"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
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"spiflash": 0xF0FF8000, # FIXME currently the flash is in the ROM spot, limited to 32 KiB
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"config_spiflash": 0xF0FF8000, # FIXME currently the flash is in the ROM spot, limited to 32 KiB
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#"END OF SLOT SPACE": 0xF0FFFFFF,
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}
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def mac_add_declrom(self, version, flash, config_flash, sector = 40):
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if ((not flash) and (not config_flash)): # so ROM is builtin
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rom_file = "rom_{}.bin".format(version.replace(".", "_"))
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rom_data = get_mem_data(filename_or_regions=rom_file, endianness="little") # "big"
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self.add_ram("rom", origin=self.mem_map["rom"], size=2**15, contents=rom_data, mode="r") ## 32 KiB, must match mmap
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print("$$$$$ ROM must be pre-existing for integration in the bitstream, double-check the ROM file is current for this configuration $$$$$\n");
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if (flash):
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from litespi.modules.generated_modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x",
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clk_freq = self.sys_clk_freq/4, # Fixme; PHY freq ?
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module=W25Q128JV(Codes.READ_1_1_4),
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region_size = 0x00008000, # 32 KiB
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with_mmap=True, with_master=False)
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print("$$$$$ ROM must be put in the external Flash NOR $$$$$\n");
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if (config_flash):
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from litespi.modules.generated_modules import S25FL128S
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from litespi.modules.generated_modules import S25FL256S
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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if ((version == "V1.0") or (version == "V1.2")): # ZTex
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self.add_spi_flash(name="config_spiflash",
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mode="1x",
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clk_freq = self.sys_clk_freq/4, # checkme; PHY freq ?
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module=S25FL128S(Codes.READ_1_1_1),
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region_size = 0x00008000, # 32 KiB,
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region_offset = (sector * 65536),
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with_mmap=True, with_master=False)
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try:
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# get and set the signal if we're on 2.12
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fx2_sloe = self.platform.request("fx2_sloe", 0)
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self.comb += [ fx2_sloe.eq(1), ] # force the FX2 side of the GPIF/FIFO interface to read, so we can access the flash
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except:
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# if the signal is not defined, we're on a 2.13 and don't need it
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self.comb += [ ]
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# ignore
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elif (version == "V2.0"):
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self.add_spi_flash(name="config_spiflash",
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mode="4x",
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clk_freq = self.sys_clk_freq/4, # CHECKME; PHY freq ?
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module=S25FL256S(Codes.READ_1_1_1), # checkme
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region_size = 0x00008000, # 32 KiB,
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region_offset = (sector * 65536), # CHECKME
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with_mmap=True, with_master=False)
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else:
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assert(False)
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print(f"$$$$$ ROM must be put in the config Flash at sector {sector} $$$$$\n");
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def mac_add_sdram(self, hwinit = False, sdram_dfii_base = None, ddrphy_base = None, version = "V1.0"):
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(self.platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = self.sys_clk_freq)
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if ((version == "V1.0") or (version == "V1_2")): # ZTex Boards
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(self.sys_clk_freq, "1:4"),
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l2_cache_size = 0,
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)
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elif (version == "V2.0"): # TE0710 boards
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = IS43TR8512B(self.sys_clk_freq, "1:4"), # TBD
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l2_cache_size = 0,
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)
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self.avail_sdram = self.bus.regions["main_ram"].size
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if (hwinit):
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from VintageBusFPGA_Common.sdram_init import DDR3FBInit
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if ((version == "V1.0") or (version == "V1.2")): # ZTex Boards
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self.submodules.sdram_init = DDR3FBInit(sys_clk_freq = self.sys_clk_freq,
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bitslip = 1, delay = 25, # CHECKME / FIXME: parameters
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sdram_dfii_base = sdram_dfii_base, ddrphy_base = ddrphy_base)
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self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus)
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else:
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assert(False) # HW init TBC for TE0710 boards
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def mac_add_goblin_prelim(self):
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base_fb = self.wb_mem_map["main_ram"] + self.avail_sdram - 1048576 # placeholder
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if (self.avail_sdram >= self.goblin_fb_size):
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self.avail_sdram = self.avail_sdram - self.goblin_fb_size
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base_fb = self.wb_mem_map["main_ram"] + self.avail_sdram
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self.wb_mem_map["video_framebuffer"] = base_fb
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print(f"FrameBuffer base_fb @ {base_fb:x}")
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else:
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print("***** ERROR ***** Can't have a FrameBuffer without main ram\n")
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assert(False)
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def mac_add_goblin(self, use_goblin_alt = True, hdmi = True, goblin_res = None, goblin_irq = None, audio_irq = None):
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if ((not use_goblin_alt) or (not hdmi)):
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from VintageBusFPGA_Common.goblin_fb import goblin_rounded_size, Goblin
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else:
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from VintageBusFPGA_Common.goblin_alt_fb import goblin_rounded_size, GoblinAlt
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if (not hdmi):
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self.submodules.videophy = VideoVGAPHY(self.platform.request("vga"), clock_domain="vga")
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self.submodules.goblin = Goblin(soc=self, phy=self.videophy, timings=goblin_res, clock_domain="vga", irq_line=goblin_irq, endian="little", hwcursor=False, truecolor=True) # clock_domain for the VGA side, goblin is running in cd_sys
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else:
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if (not use_goblin_alt):
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self.submodules.videophy = VideoS7HDMIPHY(self.platform.request("hdmi"), clock_domain="hdmi")
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self.submodules.goblin = Goblin(soc=self, phy=self.videophy, timings=goblin_res, clock_domain="hdmi", irq_line=goblin_irq, endian="little", hwcursor=False, truecolor=True) # clock_domain for the HDMI side, goblin is running in cd_sys
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else:
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# GoblinAlt contains its own PHY
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self.submodules.goblin = GoblinAlt(soc=self, timings=goblin_res, clock_domain="hdmi", irq_line=goblin_irq, endian="little", hwcursor=False, truecolor=True)
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# it also has a bus master so that the audio bit can fetch data from Wishbone
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self.bus.add_master(name="GoblinAudio", master=self.goblin.goblin_audio.busmaster)
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self.add_ram("goblin_audio_ram", origin=self.mem_map["goblin_audio_ram"], size=2**13, mode="rw") # 8 KiB buffer, planned as 2*4KiB
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self.comb += [ audio_irq.eq(self.goblin.goblin_audio.irq), ]
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self.bus.add_slave("goblin_bt", self.goblin.bus, SoCRegion(origin=self.mem_map.get("goblin_bt", None), size=0x1000, cached=False))
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#pad_user_led_0 = platform.request("user_led", 0)
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#pad_user_led_1 = platform.request("user_led", 1)
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#self.comb += pad_user_led_0.eq(self.goblin.video_framebuffer.underflow)
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#self.comb += pad_user_led_1.eq(self.goblin.video_framebuffer.fb_dma.enable)
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if (True):
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self.submodules.goblin_accel = GoblinAccelNuBus(soc = self)
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self.bus.add_slave("goblin_accel", self.goblin_accel.bus, SoCRegion(origin=self.mem_map.get("goblin_accel", None), size=0x1000, cached=False))
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self.bus.add_master(name="goblin_accel_r5_i", master=self.goblin_accel.ibus)
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self.bus.add_master(name="goblin_accel_r5_d", master=self.goblin_accel.dbus)
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goblin_rom_file = "VintageBusFPGA_Common/blit_goblin_nubus.raw"
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goblin_rom_data = get_mem_data(filename_or_regions=goblin_rom_file, endianness="little")
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goblin_rom_len = 4*len(goblin_rom_data);
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rounded_goblin_rom_len = 2**log2_int(goblin_rom_len, False)
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print(f"GOBLIN ROM is {goblin_rom_len} bytes, using {rounded_goblin_rom_len}")
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assert(rounded_goblin_rom_len <= 2**16)
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self.add_ram("goblin_accel_rom", origin=self.mem_map["goblin_accel_rom"], size=rounded_goblin_rom_len, contents=goblin_rom_data, mode="r")
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self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
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