mirror of
https://github.com/rdolbeau/VintageBusFPGA_Common.git
synced 2026-01-13 15:17:19 +00:00
72 lines
3.3 KiB
Python
72 lines
3.3 KiB
Python
from migen import *
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from migen.genlib.fifo import *
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import litex
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from litex.soc.interconnect import wishbone
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from migen.genlib.cdc import BusSynchronizer
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class WishboneDomainCrossingMaster(Module, wishbone.Interface):
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"""Wishbone Clock Domain Crossing [Master]"""
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def __init__(self, platform, slave, cd_master="sys", cd_slave="sys", force_delay = 0):
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# Same Clock Domain, direct connection.
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wishbone.Interface.__init__(self, data_width=slave.data_width, adr_width=slave.adr_width)
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if cd_master == cd_slave:
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raise NameError("Don't use domain crossing for the same domains.")
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# Clock Domain Crossing.
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else:
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self.add_sources(platform)
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delay_stb = Signal()
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if (force_delay == 0):
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self.comb += [ delay_stb.eq(self.stb), ]
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else:
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counter = Signal(max=force_delay+1)
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last_stb = Signal()
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master_sync = getattr(self.sync, cd_master)
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master_sync += [
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If(counter != 0,
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counter.eq(counter - 1),
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),
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last_stb.eq(self.stb),
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If(~self.stb & last_stb, # falling edge, force timeout
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counter.eq(force_delay),
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),
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]
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self.comb += [ delay_stb.eq(self.stb & (counter == 0)) ]
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#fixme: parameters
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self.specials += Instance(self.get_netlist_name(),
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# master side
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i_wbm_clk = ClockSignal(cd_master),
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i_wbm_rst = ResetSignal(cd_master),
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i_wbm_adr_i = self.adr,
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i_wbm_dat_i = self.dat_w,
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o_wbm_dat_o = self.dat_r,
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i_wbm_we_i = self.we,
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i_wbm_sel_i = self.sel,
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i_wbm_stb_i = delay_stb,
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o_wbm_ack_o = self.ack,
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o_wbm_err_o = self.err,
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o_wbm_rty_o = Signal(),
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i_wbm_cyc_i = self.cyc,
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# slave side
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i_wbs_clk = ClockSignal(cd_slave),
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i_wbs_rst = ResetSignal(cd_slave),
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o_wbs_adr_o = slave.adr,
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o_wbs_dat_o = slave.dat_w,
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i_wbs_dat_i = slave.dat_r,
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o_wbs_we_o = slave.we,
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o_wbs_sel_o = slave.sel,
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o_wbs_stb_o = slave.stb,
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i_wbs_ack_i = slave.ack,
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i_wbs_err_i = slave.err,
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i_wbs_rty_i = Signal(),
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o_wbs_cyc_o = slave.cyc)
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def get_netlist_name(self):
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return "wb_async_reg"
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def add_sources(self, platform):
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platform.add_source("VintageBusFPGA_Common/wb_async_reg.v", "verilog")
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