mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Expanding the code
This commit is contained in:
Ross Wilson
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vimlac/.gitignore
vendored
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vimlac/.gitignore
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@@ -1 +1,2 @@
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test_cpu
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_#*#_.*
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401
vimlac/CPU.test
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401
vimlac/CPU.test
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# LAW
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setreg ac 0177777; setreg l 1; setmem 0100 [LAW 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [LAW 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
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setreg ac 0; setreg l 0; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
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# LWC
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setreg ac 0; setreg l 1; setmem 0100 [LWC 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 0; setmem 0100 [LWC 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 1; setmem 0100 [LWC 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0; setreg l 0; setmem 0100 [LWC 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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# JMP
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setreg ac 012345; setreg l 1; setmem 0100 [JMP 0200]; RUN 0100; checkcycles 2; checkreg pc 0200
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setreg ac 012345; setreg l 0; setmem 0100 [JMP 0110]; RUN 0100; checkcycles 2; checkreg pc 0110
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setreg ac 012345; setreg l 1; setmem 0100 [JMP *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0120
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setreg ac 012345; setreg l 0; setmem 0100 [JMP *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0121; checkmem 010 0121
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# DAC
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setreg ac 1; setreg l 1; setreg pc 0100; setmem 0100 [DAC 0110]; RUN; checkcycles 2; checkreg pc 0101; checkmem 0110 1
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setreg ac 0177777; setreg l 0; setmem 0100 [DAC *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
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setreg ac 0177777; setreg l 1; setmem 0100 [DAC *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0121 0177777; checkmem 010 0121
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# XAM
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setreg ac 1; setreg l 0; setmem 0100 [XAM 0110]; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkmem 0110 1
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setreg ac 0100; setreg l 1; setmem 0100 [XAM *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 0120 0100
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setreg ac 0200; setreg l 0; setmem 0100 [XAM *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121; checkmem 0121 0200
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# ISZ
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setreg ac 1; setreg l 0; setmem 0100 [ISZ 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkmem 0110 1
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setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0101; checkmem 0110 0177777
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setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0102; checkmem 0110 0
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setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 1
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setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
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setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 0120 0
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setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 1
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setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 0177777
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setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121; checkmem 0121 0
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# JMS
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setreg ac 1; setreg l 0; setmem 0100 [JMS 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0111; checkmem 0110 0101
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setreg ac 1; setreg l 0; setmem 0100 [JMS *0110]; setmem 0110 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0121; checkmem 0120 0101
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setreg ac 1; setreg l 0; setmem 0100 [JMS *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0122; checkmem 010 0121; checkmem 0121 0101
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# AND
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setreg ac 0; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 1; setmem 0100 [AND 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0125252; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0052525
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setreg ac 0; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 1; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0125252; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0052525
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setreg ac 0; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
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setreg ac 0177777; setreg l 1; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0111
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setreg ac 0125252; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
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setreg ac 0177777; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0052525; checkmem 010 0111
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# IOR
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setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0177777; setreg l 1; setmem 0100 [IOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0125252; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0177000; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0177777; setreg l 1; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0125252; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0177777; setreg l 1; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0125252; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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# XOR
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setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 1; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0125252; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0177000; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 1; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0125252; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 1; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0125252; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0000777; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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# LAC
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setreg ac 1; setmem 0100 [LAC 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setmem 0100 [LAC 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setmem 0100 [LAC 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
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setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
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# ADD
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setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 2
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setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 1; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 0
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setreg ac 2; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 1
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setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 0
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setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177775; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2
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setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 1; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0
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setreg ac 2; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1
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setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0
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setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177775; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
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setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkmem 010 0121
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setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
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setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1; checkmem 010 0121
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setreg ac 1; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0; checkmem 010 0121
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setreg ac 2; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1; checkmem 010 0121
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setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0; checkmem 010 0121
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setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177775; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1; checkmem 010 0121
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# SUB
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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||||
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||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
|
||||
# SAM
|
||||
setreg ac 1; setmem 0100 [SAM 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0102
|
||||
|
||||
setreg ac 1; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0102
|
||||
|
||||
setreg ac 1; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
setreg ac 0177777; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
|
||||
# HLT
|
||||
setmem 0100 [HLT]; RUN 0100; checkcycles 1; checkrun false; checkreg pc 0101
|
||||
|
||||
# NOP
|
||||
setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkrun true; checkreg pc 0101
|
||||
|
||||
# CLA
|
||||
setreg ac 0; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
|
||||
# CMA
|
||||
setreg ac 0; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
|
||||
# STA
|
||||
setreg ac 0; setmem 0100 [STA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setmem 0100 [STA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# IAC
|
||||
setreg ac 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2
|
||||
# bug in microcode, MainCPU.py, line 333
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
|
||||
# CIA
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 0
|
||||
setreg ac 1; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
|
||||
# CLL
|
||||
setreg l 0; setmem 0100 [CLL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
setreg l 1; setmem 0100 [CLL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
|
||||
# CML
|
||||
setreg l 0; setmem 0100 [CML]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [CML]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
|
||||
# CAL
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CAL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CAL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
|
||||
# STL
|
||||
setreg l 0; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
|
||||
# ODA
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0177777; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0777; setreg ac 0177070; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# LDA
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 1; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ds 0177000; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177000
|
||||
setreg ds 0177777; setreg ac 1; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# SAL
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0100001; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100002
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0100001; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100004
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0100001; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100010
|
||||
|
||||
# SAR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 3; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0140000
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 03; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0160000
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 017; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0170000
|
||||
|
||||
# RAL
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177775; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 010; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177773; checkreg l 1
|
||||
|
||||
# RAR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0077777; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0137777; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0020000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0157777; checkreg l 1
|
||||
|
||||
# ASZ
|
||||
setreg ac 1; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# ASN
|
||||
setreg ac 1; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# ASP
|
||||
setreg ac 1; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# ASM
|
||||
setreg ac 1; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# LSZ
|
||||
setreg l 0; setmem 0100 [LSZ]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg l 1; setmem 0100 [LSZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# LSN
|
||||
setreg l 0; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg l 1; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# not tested here, interacting with other hardware
|
||||
# DON
|
||||
# DSF
|
||||
# DSN
|
||||
# KSF
|
||||
# KSN
|
||||
# RSF
|
||||
# RSN
|
||||
# TSF
|
||||
# TSN
|
||||
# SSF
|
||||
# SSN
|
||||
# HSF
|
||||
# HSN
|
||||
#
|
||||
# DLA
|
||||
# CTB
|
||||
# DOF
|
||||
# KRB
|
||||
# KCF
|
||||
# KRC
|
||||
# RRB
|
||||
# RCF
|
||||
# RRC
|
||||
# TPR
|
||||
# TCF
|
||||
# TPC
|
||||
# HRB
|
||||
# HOF
|
||||
# HON
|
||||
# STB
|
||||
# SCF
|
||||
# IOS
|
||||
# PSF
|
||||
# PPC
|
||||
# and lots of IOT instructions
|
||||
@@ -1,7 +1,8 @@
|
||||
DEVFILES = cpu.o dcpu.o ptr.o ptp.o memory.o kb.o ttyin.o ttyout.o trace.o error.o
|
||||
OFILES = vimlac.o $(DEVFILES)
|
||||
|
||||
CFLAGS=-shared -fPIC -O2 -Wall -ansi -pedantic -std=c99 -g
|
||||
#CFLAGS=-fPIC -O2 -Wall -ansi -pedantic -std=c99 -g
|
||||
CFLAGS=-O2 -Wall -ansi -pedantic -std=c99 -g
|
||||
|
||||
test: vimlac.py vimlac
|
||||
#python vimlac.py -ptr test_add.ptp -r 040 -r 0100
|
||||
|
||||
@@ -26,5 +26,3 @@ error(char *fmt, ...)
|
||||
|
||||
exit(10);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -61,6 +61,17 @@
|
||||
#include "error.h"
|
||||
|
||||
|
||||
// constants
|
||||
char *LstFilename = "_#TEST#_.lst";
|
||||
char *AsmFilename = "_#TEST#_.asm";
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Description : Function to provide help to the befuddled user.
|
||||
Parameters : msg - if not NULL, a message to display
|
||||
Returns :
|
||||
Comments :
|
||||
******************************************************************************/
|
||||
void
|
||||
usage(char *msg)
|
||||
{
|
||||
@@ -84,6 +95,100 @@ usage(char *msg)
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Description : Function to return the imlac binary opcode of an instruction.
|
||||
Parameters : addr - address of the instruction
|
||||
: opcode - string containing the instruction
|
||||
Returns :
|
||||
Comments : We generate an ASM file, assemble it and pick out the binary
|
||||
: opcode from the LST file.
|
||||
******************************************************************************/
|
||||
int
|
||||
assemble(WORD addr, char *opcode)
|
||||
{
|
||||
FILE *fd;
|
||||
char buffer[128];
|
||||
WORD result;
|
||||
|
||||
// create the ASM file
|
||||
fd = fopen(AsmFilename, "wb");
|
||||
fprintf(fd, "\torg\t%07o\n", addr);
|
||||
fprintf(fd, "\t%s\n", opcode);
|
||||
fprintf(fd, "\tend\n");
|
||||
fclose(fd);
|
||||
|
||||
// assemble the file
|
||||
sprintf(buffer, "../iasm/iasm -l %s %s", LstFilename, AsmFilename);
|
||||
if (system(buffer) == -1)
|
||||
error("Error doing: %s", buffer);
|
||||
|
||||
// read LST file for opcode on second line
|
||||
fd = fopen(LstFilename, "rb");
|
||||
if (fgets(buffer, sizeof(buffer), fd) == NULL)
|
||||
error("Error reading %s", LstFilename);
|
||||
if (fgets(buffer, sizeof(buffer), fd) == NULL)
|
||||
error("Error reading %s", LstFilename);
|
||||
if (sscanf(buffer, "%o", &result) != 1)
|
||||
error("Badly formatted assembler output: %s", buffer);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Description : Function to execute test script.
|
||||
Parameters : script - path to script file to execute
|
||||
Returns :
|
||||
Comments :
|
||||
******************************************************************************/
|
||||
int
|
||||
execute(char *script)
|
||||
{
|
||||
int errors = 0;
|
||||
|
||||
return errors;
|
||||
}
|
||||
|
||||
#ifdef JUNK
|
||||
def main(self, filename):
|
||||
"""Execute CPU tests from 'filename'."""
|
||||
|
||||
log.debug("Running test file '%s'" % filename)
|
||||
|
||||
# get all tests from file
|
||||
with open(filename, 'rb') as fd:
|
||||
lines = fd.readlines()
|
||||
|
||||
# read lines, join continued, get complete tests
|
||||
tests = []
|
||||
test = ''
|
||||
for line in lines:
|
||||
line = line[:-1] # strip newline
|
||||
if not line:
|
||||
continue # skip blank lines
|
||||
|
||||
if line[0] == '#': # a comment
|
||||
continue
|
||||
|
||||
if line[0] == '\t': # continuation
|
||||
if test:
|
||||
test += '; '
|
||||
test += line[1:]
|
||||
else: # beginning of new test
|
||||
if test:
|
||||
tests.append(test)
|
||||
test = line
|
||||
|
||||
# flush last test
|
||||
if test:
|
||||
tests.append(test)
|
||||
|
||||
# now do each test
|
||||
for test in tests:
|
||||
log.debug('Executing test: %s' % test)
|
||||
#endif
|
||||
|
||||
|
||||
int
|
||||
main(int argc, char *argv[])
|
||||
{
|
||||
@@ -114,12 +219,14 @@ main(int argc, char *argv[])
|
||||
|
||||
// get filename and make sure it's there
|
||||
script = argv[optind];
|
||||
if ((script_fd = fopen(script, "r")) == -1)
|
||||
if ((script_fd = fopen(script, "r")) == NULL)
|
||||
{
|
||||
error("File %s doesn't exist or isn't readable: %s\n",
|
||||
error("File %s doesn't exist or isn't readable: %d\n",
|
||||
script, errno);
|
||||
}
|
||||
|
||||
errors = execute(script);
|
||||
|
||||
printf("%d errors found\n", errors);
|
||||
|
||||
return 0;
|
||||
@@ -127,64 +234,6 @@ main(int argc, char *argv[])
|
||||
|
||||
|
||||
#ifdef JUNK
|
||||
"""
|
||||
Test pymlac CPU opcodes DIRECTLY.
|
||||
|
||||
Usage: test_CPU.py [<options>] <filename>
|
||||
|
||||
where <filename> is a file of test instructions and
|
||||
<options> is one or more of
|
||||
-h prints this help and stops
|
||||
"""
|
||||
|
||||
# We implement a small interpreter to test the CPU. The test code is read in
|
||||
# from a file:
|
||||
#
|
||||
# # LAW
|
||||
# setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
# setreg ac 012345; setreg l 0; setmem 0100 [LAW 0]; RUN 0100
|
||||
# checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
#
|
||||
# The instructions are delimited by ';' characters. A line beginning with a
|
||||
# TAB character is a continuation of the previous line.
|
||||
# Lines with '#' in column 1 are comments.
|
||||
#
|
||||
# The test instructions are:
|
||||
# setreg <name> <value>
|
||||
# where <name> is one of AC, L, PC or DS, value is any value
|
||||
# (all registers are set to 0 initially)
|
||||
#
|
||||
# setmem <addr> <value>
|
||||
# where <addr> is an address and value is any value OR
|
||||
# [<instruction>] where the value is the assembled opcode
|
||||
#
|
||||
# run [<addr>]
|
||||
# execute one instruction, if optional <addr> is used PC := addr before
|
||||
#
|
||||
# checkcycles <number>
|
||||
# check number of executed cycles is <number>
|
||||
#
|
||||
# checkreg <name> <value>
|
||||
# check register (AC, L, PC or DS) has value <value>
|
||||
#
|
||||
# checkmem <addr> <value>
|
||||
# check that memory at <addr> has <value>
|
||||
#
|
||||
# allreg <value>
|
||||
# sets all registers to <value>
|
||||
# a "allreg 0" is assumed before each test
|
||||
#
|
||||
# allmem <value>
|
||||
# sets all of memory to <value>
|
||||
# a "allmem 0" is assumed before each test
|
||||
#
|
||||
# In addition, all of memory is checked for changed values after execution
|
||||
# except where an explicit "checkmem <addr> <value>" has been performed.
|
||||
# Additionally, registers that aren't explicitly checked are tested to make
|
||||
# sure they didn't change.
|
||||
#
|
||||
# If a test line finds no error, just print the fully assembled test line.
|
||||
# If any errors are found, print line followed by all errors.
|
||||
|
||||
|
||||
import os
|
||||
|
||||
Reference in New Issue
Block a user