From 256a996de2bf42e77b914080b2728cd8ec38b409 Mon Sep 17 00:00:00 2001 From: Ross Wilson Date: Wed, 25 Jul 2018 13:58:57 +0700 Subject: [PATCH] Trace now working --- pymlac/DisplayCPU.py | 91 +++++++------ pymlac/MainCPU.py | 295 +++++++++++++++++++++---------------------- pymlac/Trace.py | 120 +++++++++--------- pymlac/pymlac | 11 +- 4 files changed, 260 insertions(+), 257 deletions(-) diff --git a/pymlac/DisplayCPU.py b/pymlac/DisplayCPU.py index b6cba9d..0040c9f 100644 --- a/pymlac/DisplayCPU.py +++ b/pymlac/DisplayCPU.py @@ -148,7 +148,7 @@ class DisplayCPU(object): def execute_one_instruction(self): if not self.Running: - return (0, None) + return 0 self.dot = self.DPC instruction = self.memory.fetch(self.DPC, False) @@ -157,9 +157,10 @@ class DisplayCPU(object): if self.Mode == self.MODE_DEIM: tracestr = self.doDEIMByte(instruction >> 8) if self.Mode == self.MODE_DEIM: - tracestr += ', ' + self.doDEIMByte(instruction & 0xff, True) + tracestr += ',' + self.doDEIMByte(instruction & 0xff, True) log('execute_one_instruction: tracestr=%s' % tracestr) - return (1, tracestr) + Trace.dtrace(self.dot, 'INC ', tracestr) + return 1 opcode = instruction >> 12 address = instruction & 0o07777 @@ -188,37 +189,42 @@ class DisplayCPU(object): def i_DDXM(self): self.DX -= 0o40 - tracestr = Trace.dtrace(self.dot, 'DDXM', None) - return (1, tracestr) + Trace.dtrace(self.dot, 'DDXM', None) + return 1 def i_DDYM(self): self.DY -= 0o40 - tracestr = Trace.dtrace(self.dot, 'DDYM', None) - return (1, tracestr) + Trace.dtrace(self.dot, 'DDYM', None) + return 1 def i_DEIM(self, address): self.Mode = self.MODE_DEIM - tracestr = 'DEIM\t' + self.doDEIMByte(address & 0o377, last=True) - return (1, tracestr) + Trace.dtrace(self.dot, 'DEIM', self.doDEIMByte(address & 0o377, last=True)) + return 1 def i_DHLT(self): self.Running = False - return (1, Trace.dtrace(self.dot, 'DHLT', None)) + Trace.dtrace(self.dot, 'DHLT', None) + return 1 def i_DHVC(self): - return (1, Trace.dtrace(self.dot, 'DHVC', None)) + Trace.dtrace(self.dot, 'DHVC', None) + return 1 def i_DIXM(self): self.DX += 0o4000 - return (1, Trace.dtrace(self.dot, 'DIXM', None)) + Trace.dtrace(self.dot, 'DIXM', None) + return 1 def i_DIYM(self): self.DY += 0o4000 - return (1, Trace.dtrace(self.dot, 'DIYM', None)) + Trace.dtrace(self.dot, 'DIYM', None) + return 1 def i_DJMP(self, address): self.DPC = MASK_MEM(address + (self.DIB << 12)) - return (1, Trace.dtrace(self.dot, 'DJMP', address)) + Trace.dtrace(self.dot, 'DJMP', address) + return 1 def i_DJMS(self, address): if self.DRSindex >= 8: @@ -228,15 +234,18 @@ class DisplayCPU(object): self.DRS[self.DRSindex] = self.DPC self.DRSindex += 1 self.DPC = MASK_MEM(address + (self.DIB << 12)) - return (1, Trace.dtrace(self.dot, 'DJMS', address)) + Trace.dtrace(self.dot, 'DJMS', address) + return 1 def i_DLXA(self, address): self.DX = (address & self.BITS10) << 1 - return (1, Trace.dtrace(self.dot, 'DLXA', address)) + Trace.dtrace(self.dot, 'DLXA', address) + return 1 def i_DLYA(self, address): self.DY = (address & self.BITS10) << 1 - return (1, Trace.dtrace(self.dot, 'DLXA', address)) + Trace.dtrace(self.dot, 'DLXA', address) + return 1 def i_DLVH(self, word1): word2 = self.memory.get(self, DPC, 0) @@ -276,21 +285,22 @@ class DisplayCPU(object): self.DY += N self.display.draw(prevDX, prevDY, self.DX, self.DY, dotted) - return (3, Trace.dtrace(self.dot, 'DLVH', None)) + Trace.dtrace(self.dot, 'DLVH', None) + return 3 def i_DRJM(self): if self.DRSindex <= 0: - Trace.comment('DRS stack underflow at display address %6.6o' - % (self.DPC - 1)) - self.illegal() + Trace.comment(f'DRS stack underflow at display address {self.DPC - 1:6.6o}') + self.illegal() self.DRSindex -= 1 self.DPC = self.DRS[self.DRSindex] - return (1, Trace.dtrace(self.dot, 'DRJM', None)) # FIXME check # cycles used + Trace.dtrace(self.dot, 'DRJM', None) + return 1 # FIXME check # cycles used def i_DSTB(self, block): self.DIB = block - Trace.dtrace('DSTB\t%d' % block) - return (1, Trace.dtrace('DSTB\t%d' % block, None)) + Trace.dtrace(self.dot, f'DSTB {block}', None) + return 1 def i_DSTS(self, scale): if scale == 0: @@ -303,41 +313,42 @@ class DisplayCPU(object): self.Scale = 3.0 else: self.illegal() - return (1, Trace.dtrace('DSTS\t%d' % scale, None)) # FIXME check # cycles used + Trace.dtrace(self.dot, f'DSTS {scale}', None) + return 1 # FIXME check # cycles used def page00(self, instruction): if instruction == 0o00000: # DHLT - (cycles, tracestr) = self.i_DHLT() + cycles = self.i_DHLT() elif instruction == 0o04000: # DNOP cycles = 1 - tracestr = Trace.dtrace('DNOP') + Trace.dtrace(self.dot, 'DNOP') elif instruction == 0o04004: # DSTS 0 - (cycles, tracestr) = self.i_DSTS(0) + cycles = self.i_DSTS(0) elif instruction == 0o04005: # DSTS 1 - (cycles, tracestr) = self.i_DSTS(1) + cycles = self.i_DSTS(1) elif instruction == 0o04006: # DSTS 2 - (cycles, tracestr) = self.i_DSTS(2) + cycles = self.i_DSTS(2) elif instruction == 0o04007: # DSTS 3 - (cycles, tracestr) = self.i_DSTS(3) + cycles = self.i_DSTS(3) elif instruction == 0o04010: # DSTB 0 - (cycles, tracestr) = self.i_DSTB(0) + cycles = self.i_DSTB(0) elif instruction == 0o04011: # DSTB 1 - (cycles, tracestr) = self.i_DSTB(1) + cycles = self.i_DSTB(1) elif instruction == 0o04040: # DRJM - (cycles, tracestr) = self.i_DRJM() + cycles = self.i_DRJM() elif instruction == 0o04100: # DDYM - (cycles, tracestr) = self.i_DDYM() + cycles = self.i_DDYM() elif instruction == 0o04200: # DDXM - (cycles, tracestr) = self.i_DDXM() + cycles = self.i_DDXM() elif instruction == 0o04400: # DIYM - (cycles, tracestr) = self.i_DIYM() + cycles = self.i_DIYM() elif instruction == 0o05000: # DIXM - (cycles, tracestr) = self.i_DIXM() + cycles = self.i_DIXM() elif instruction == 0o06000: # DHVC - (cycles, tracestr) = self.i_DHVC() + cycles = self.i_DHVC() else: self.illegal(instruction) - return (cycles, tracestr) + return cycles def start(self): self.Running = True diff --git a/pymlac/MainCPU.py b/pymlac/MainCPU.py index 70a8fe3..5eaeb7a 100644 --- a/pymlac/MainCPU.py +++ b/pymlac/MainCPU.py @@ -213,34 +213,33 @@ class MainCPU(object): instruction) def i_LAW_LWC(self, indirect, address, instruction): - tracestr = None if indirect: self.AC = (~address+1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'LWC', False, address) + Trace.itrace(self.dot, 'LWC', False, address) else: self.AC = address - tracestr = Trace.itrace(self.dot, 'LAW', False, address) - return (1, tracestr) + Trace.itrace(self.dot, 'LAW', False, address) + return 1 def i_JMP(self, indirect, address, instruction): eff_address = self.memory.eff_address(address, indirect) self.PC = eff_address & PCMASK - tracestr = Trace.itrace(self.dot, 'JMP', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'JMP', indirect, address) + return 3 if indirect else 2 def i_DAC(self, indirect, address, instruction): eff_address = self.memory.eff_address(address, indirect) self.memory.put(self.AC, eff_address, False) - tracestr = Trace.itrace(self.dot, 'DAC', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'DAC', indirect, address) + return 3 if indirect else 2 def i_XAM(self, indirect, address, instruction): eff_address = self.memory.eff_address(address, indirect) tmp = self.memory.fetch(eff_address, False) self.memory.put(self.AC, eff_address, False) self.AC = tmp - tracestr = Trace.itrace(self.dot, 'XAM', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'XAM', indirect, address) + return 3 if indirect else 2 def i_ISZ(self, indirect, address, instruction): eff_address = self.memory.eff_address(address, indirect) @@ -248,43 +247,43 @@ class MainCPU(object): self.memory.put(value, eff_address, False) if value == 0: self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'ISZ', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'ISZ', indirect, address) + return 3 if indirect else 2 def i_JMS(self, indirect, address, instruction): eff_address = self.memory.eff_address(address, indirect) self.memory.put(self.PC, eff_address, False) self.PC = (eff_address + 1) & PCMASK - tracestr = Trace.itrace(self.dot, 'JMS', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'JMS', indirect, address) + return 3 if indirect else 2 def i_AND(self, indirect, address, instruction): self.AC &= self.memory.fetch(address, indirect) - tracestr = Trace.itrace(self.dot, 'AND', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'AND', indirect, address) + return 3 if indirect else 2 def i_IOR(self, indirect, address, instruction): self.AC |= self.memory.fetch(address, indirect) - tracestr = Trace.itrace(self.dot, 'IOR', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'IOR', indirect, address) + return 3 if indirect else 2 def i_XOR(self, indirect, address, instruction): self.AC ^= self.memory.fetch(address, indirect) - tracestr = Trace.itrace(self.dot, 'XOR', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'XOR', indirect, address) + return 3 if indirect else 2 def i_LAC(self, indirect, address, instruction): self.AC = self.memory.fetch(address, indirect) - tracestr = Trace.itrace(self.dot, 'LAC', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'LAC', indirect, address) + return 3 if indirect else 2 def i_ADD(self, indirect, address, instruction): self.AC += self.memory.fetch(self.BLOCKADDR(address), indirect) if self.AC & OVERFLOWMASK: self.L = 0 if self.L else 1 self.AC &= WORDMASK - tracestr = Trace.itrace(self.dot, 'ADD', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'ADD', indirect, address) + return 3 if indirect else 2 def i_SUB(self, indirect, address, instruction): addit = self.memory.fetch(self.BLOCKADDR(address), indirect) @@ -293,15 +292,15 @@ class MainCPU(object): if self.AC & OVERFLOWMASK: self.L = 0 if self.L else 1 self.AC &= WORDMASK - tracestr = Trace.itrace(self.dot, 'SUB', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'SUB', indirect, address) + return 3 if indirect else 2 def i_SAM(self, indirect, address, instruction): samaddr = self.BLOCKADDR(address) if self.AC == self.memory.fetch(samaddr, indirect): self.PC = (self.PC + 1) & PCMASK - tracestr = Trace.itrace(self.dot, 'SAM', indirect, address) - return (3, tracestr) if indirect else (2, tracestr) + Trace.itrace(self.dot, 'SAM', indirect, address) + return 3 if indirect else 2 def microcode(self, instruction): # T1 @@ -342,150 +341,150 @@ class MainCPU(object): if instruction & k: combine.append(op) - tracestr = Trace.itrace(self.dot, '+'.join(combine), False) - return (1, tracestr) + Trace.itrace(self.dot, '+'.join(combine), False) + return 1 def i_DLA(self, indirect, address, instruction): self.displaycpu.DPC = self.AC - tracestr = Trace.itrace(self.dot, 'DLA') - return (1, tracestr) + Trace.itrace(self.dot, 'DLA') + return 1 def i_CTB(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'CTB') - return (1, tracestr) + Trace.itrace(self.dot, 'CTB') + return 1 def i_DOF(self, indirect, address, instruction): log('self.displaycpu=%s' % str(self.displaycpu)) self.displaycpu.stop() - tracestr = Trace.itrace(self.dot, 'DOF') - return (1, tracestr) + Trace.itrace(self.dot, 'DOF') + return 1 def i_KRB(self, indirect, address, instruction): self.AC |= self.kbd.read() - tracestr = Trace.itrace(self.dot, 'KRB') - return (1, tracestr) + Trace.itrace(self.dot, 'KRB') + return 1 def i_KCF(self, indirect, address, instruction): self.kbd.clear() - tracestr = Trace.itrace(self.dot, 'KCF') - return (1, tracestr) + Trace.itrace(self.dot, 'KCF') + return 1 def i_KRC(self, indirect, address, instruction): self.AC |= self.kbd.read() self.kbd.clear() - tracestr = Trace.itrace(self.dot, 'KRC') - return (1, tracestr) + Trace.itrace(self.dot, 'KRC') + return 1 def i_RRB(self, indirect, address, instruction): self.AC |= self.ttyin.read() - tracestr = Trace.itrace(self.dot, 'RRB') - return (1, tracestr) + Trace.itrace(self.dot, 'RRB') + return 1 def i_RCF(self, indirect, address, instruction): self.ttyin.clear() - tracestr = Trace.itrace(self.dot, 'RCF') - return (1, tracestr) + Trace.itrace(self.dot, 'RCF') + return 1 def i_RRC(self, indirect, address, instruction): self.AC |= self.ttyin.read() self.ttyin.clear() - tracestr = Trace.itrace(self.dot, 'RRC') - return (1, tracestr) + Trace.itrace(self.dot, 'RRC') + return 1 def i_TPR(self, indirect, address, instruction): self.ttyout.write(self.AC & 0xff) - tracestr = Trace.itrace(self.dot, 'TPR') - return (1, tracestr) + Trace.itrace(self.dot, 'TPR') + return 1 def i_TCF(self, indirect, address, instruction): self.ttyout.clear() - tracestr = Trace.itrace(self.dot, 'TCF') - return (1, tracestr) + Trace.itrace(self.dot, 'TCF') + return 1 def i_TPC(self, indirect, address, instruction): self.ttyout.write(self.AC & 0xff) self.ttyout.clear() - tracestr = Trace.itrace(self.dot, 'TPC') - return (1, tracestr) + Trace.itrace(self.dot, 'TPC') + return 1 def i_HRB(self, indirect, address, instruction): self.AC |= self.ptrptp.read() - tracestr = Trace.itrace(self.dot, 'HRB') - return (1, tracestr) + Trace.itrace(self.dot, 'HRB') + return 1 def i_HOF(self, indirect, address, instruction): self.ptrptp.stop() - tracestr = Trace.itrace(self.dot, 'HOF') - return (1, tracestr) + Trace.itrace(self.dot, 'HOF') + return 1 def i_HON(self, indirect, address, instruction): self.ptrptp.start() - tracestr = Trace.itrace(self.dot, 'HON') - return (1, tracestr) + Trace.itrace(self.dot, 'HON') + return 1 def i_STB(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'STB') - return (1, tracestr) + Trace.itrace(self.dot, 'STB') + return 1 def i_SCF(self, indirect, address, instruction): self.Sync40Hz = 0 - tracestr = Trace.itrace(self.dot, 'SCF') - return (1, tracestr) + Trace.itrace(self.dot, 'SCF') + return 1 def i_IOS(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOS') - return (1, tracestr) + Trace.itrace(self.dot, 'IOS') + return 1 def i_IOT101(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT101') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT101') + return 1 def i_IOT111(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT111') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT111') + return 1 def i_IOT131(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT131') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT131') + return 1 def i_IOT132(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT132') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT132') + return 1 def i_IOT134(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT134') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT134') + return 1 def i_IOT141(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOT141') - return (1, tracestr) + Trace.itrace(self.dot, 'IOT141') + return 1 def i_IOF(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'IOF') - return (1, tracestr) + Trace.itrace(self.dot, 'IOF') + return 1 def i_ION(self, indirect, address, instruction): - tracestr = Trace.itrace(self.dot, 'ION') - return (1, tracestr) + Trace.itrace(self.dot, 'ION') + return 1 def i_PPC(self, indirect, address, instruction): self.ptrptp.punch(self.AC & 0xff) - tracestr = Trace.itrace(self.dot, 'PPC') - return (1, tracestr) + Trace.itrace(self.dot, 'PPC') + return 1 def i_PSF(self, indirect, address, instruction): if self.ptrptp.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'PSF') - return (1, tracestr) + Trace.itrace(self.dot, 'PSF') + return 1 def i_RAL1(self, indirect, address, instruction): newl = self.AC >> 15 newac = (self.AC << 1) | self.L self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAL', False, 1) - return (1, tracestr) + Trace.itrace(self.dot, 'RAL', False, 1) + return 1 def i_RAL2(self, indirect, address, instruction): newl = self.AC >> 15 @@ -496,8 +495,8 @@ class MainCPU(object): newac = (self.AC << 1) | self.L self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAL', False, 2) - return (1, tracestr) + Trace.itrace(self.dot, 'RAL', False, 2) + return 1 def i_RAL3(self, indirect, address, instruction): newl = self.AC >> 15 @@ -512,16 +511,16 @@ class MainCPU(object): newac = (self.AC << 1) | self.L self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAL', False, 3) - return (1, tracestr) + Trace.itrace(self.dot, 'RAL', False, 3) + return 1 def i_RAR1(self, indirect, address, instruction): newl = self.AC & 1 newac = (self.AC >> 1) | (self.L << 15) self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAR', False, 1) - return (1, tracestr) + Trace.itrace(self.dot, 'RAR', False, 1) + return 1 def i_RAR2(self, indirect, address, instruction): newl = self.AC & 1 @@ -532,8 +531,8 @@ class MainCPU(object): newac = (self.AC >> 1) | (self.L << 15) self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAR', False, 2) - return (1, tracestr) + Trace.itrace(self.dot, 'RAR', False, 2) + return 1 def i_RAR3(self, indirect, address, instruction): newl = self.AC & 1 @@ -548,163 +547,163 @@ class MainCPU(object): newac = (self.AC >> 1) | (self.L << 15) self.L = newl self.AC = newac & WORDMASK - tracestr = Trace.itrace(self.dot, 'RAR', False, 3) - return (1, tracestr) + Trace.itrace(self.dot, 'RAR', False, 3) + return 1 def i_SAL1(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK value = self.AC & 0o37777 self.AC = (value << 1) | high_bit - tracestr = Trace.itrace(self.dot, 'SAL', False, 1) - return (1, tracestr) + Trace.itrace(self.dot, 'SAL', False, 1) + return 1 def i_SAL2(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK value = self.AC & 0o17777 self.AC = (value << 2) | high_bit - tracestr = Trace.itrace(self.dot, 'SAL', False, 2) - return (1, tracestr) + Trace.itrace(self.dot, 'SAL', False, 2) + return 1 def i_SAL3(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK value = self.AC & 0o07777 self.AC = (value << 3) | high_bit - tracestr = Trace.itrace(self.dot, 'SAL', False, 3) - return (1, tracestr) + Trace.itrace(self.dot, 'SAL', False, 3) + return 1 def i_SAR1(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK self.AC = (self.AC >> 1) | high_bit - tracestr = Trace.itrace(self.dot, 'SAR', False, 1) - return (1, tracestr) + Trace.itrace(self.dot, 'SAR', False, 1) + return 1 def i_SAR2(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK self.AC = (self.AC >> 1) | high_bit self.AC = (self.AC >> 1) | high_bit - tracestr = Trace.itrace(self.dot, 'SAR', False, 2) - return (1, tracestr) + Trace.itrace(self.dot, 'SAR', False, 2) + return 1 def i_SAR3(self, indirect, address, instruction): high_bit = self.AC & HIGHBITMASK self.AC = (self.AC >> 1) | high_bit self.AC = (self.AC >> 1) | high_bit self.AC = (self.AC >> 1) | high_bit - tracestr = Trace.itrace(self.dot, 'SAR', False, 3) - return (1, tracestr) + Trace.itrace(self.dot, 'SAR', False, 3) + return 1 def i_DON(self, indirect, address, instruction): self.display.clear() self.displaycpu.DRSindex = 0 self.displaycpu.start() - tracestr = Trace.itrace(self.dot, 'DON') - return (1, tracestr) + Trace.itrace(self.dot, 'DON') + return 1 def i_ASZ(self): if self.AC == 0: self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'ASZ') - return (1, tracestr) + Trace.itrace(self.dot, 'ASZ') + return 1 def i_ASN(self): if self.AC != 0: self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'ASN') - return (1, tracestr) + Trace.itrace(self.dot, 'ASN') + return 1 def i_ASP(self): if not (self.AC & HIGHBITMASK): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'ASP') - return (1, tracestr) + Trace.itrace(self.dot, 'ASP') + return 1 def i_ASM(self): if (self.AC & HIGHBITMASK): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'ASM') - return (1, tracestr) + Trace.itrace(self.dot, 'ASM') + return 1 def i_LSZ(self): if self.L == 0: self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'LSZ') - return (1, tracestr) + Trace.itrace(self.dot, 'LSZ') + return 1 def i_LSN(self): if self.L != 0: self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'LSN') - return (1, tracestr) + Trace.itrace(self.dot, 'LSN') + return 1 def i_DSF(self): if self.displaycpu.ison(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'DSF') - return (1, tracestr) + Trace.itrace(self.dot, 'DSF') + return 1 def i_DSN(self): if not self.displaycpu.ison(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'DSN') - return (1, tracestr) + Trace.itrace(self.dot, 'DSN') + return 1 def i_KSF(self): if self.kbd.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'KSF') - return (1, tracestr) + Trace.itrace(self.dot, 'KSF') + return 1 def i_KSN(self): if not self.kbd.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'KSN') - return (1, tracestr) + Trace.itrace(self.dot, 'KSN') + return 1 def i_RSF(self): if self.ttyin.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'RSF') - return (1, tracestr) + Trace.itrace(self.dot, 'RSF') + return 1 def i_RSN(self): if not self.ttyin.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'RSN') - return (1, tracestr) + Trace.itrace(self.dot, 'RSN') + return 1 def i_TSF(self): if self.ttyout.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'TSF') - return (1, tracestr) + Trace.itrace(self.dot, 'TSF') + return 1 def i_TSN(self): if not self.ttyout.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'TSN') - return (1, tracestr) + Trace.itrace(self.dot, 'TSN') + return 1 def i_SSF(self): if self.display.ready(): # skip if 40Hz sync on self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'SSF') - return (1, tracestr) + Trace.itrace(self.dot, 'SSF') + return 1 def i_SSN(self): if not self.display.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'SSN') - return (1, tracestr) + Trace.itrace(self.dot, 'SSN') + return 1 def i_HSF(self): if self.ptrptp.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'HSF') - return (1, tracestr) + Trace.itrace(self.dot, 'HSF') + return 1 def i_HSN(self): if not self.ptrptp.ready(): self.PC = (self.PC + 1) & WORDMASK - tracestr = Trace.itrace(self.dot, 'HSN') - return (1, tracestr) + Trace.itrace(self.dot, 'HSN') + return 1 diff --git a/pymlac/Trace.py b/pymlac/Trace.py index 3754cab..407218e 100644 --- a/pymlac/Trace.py +++ b/pymlac/Trace.py @@ -31,9 +31,9 @@ TrafeFilename = None TraceFile = None CPU = None DCPU = None -TraceMap = None -CPUInst = None -DCPUInst = None +TraceMap = collections.defaultdict(bool) +CPUInst = '' +DCPUInst = '' CPU_PC = None DCPU_PC = None @@ -46,8 +46,8 @@ def init(filename, maincpu=None, displaycpu=None): displaycpu the display CPU object (may be added later) """ - global CPU, DCPU, TraceMap, CPUInst, DCPUInst - global TraceFile, TraceFilename + global Tracing, TraceFile, TraceFilename, TraceMap + global CPU, DCPU, CPUInst, DCPUInst # set internal state Tracing = True @@ -57,24 +57,18 @@ def init(filename, maincpu=None, displaycpu=None): except: pass TraceFile = open(filename, 'w') - TraceFile.write(f"{PYMLAC_VERSION} trace\n{'-'*60}\n") + TraceFile.write(f"{PYMLAC_VERSION} trace\n{'-'*97}\n") CPU = maincpu DCPU = displaycpu - TraceMap = collections.defaultdict(bool) - log(f'Trace.init: Tracing={Tracing}, TraceFilename={TraceFilename}') - - CPUInst = None - DCPUInst = None - def start(): """Prepare trace system for new execution.""" global CPU_PC, DCPU_PC, CPUInst, DCPUInst - CPUInst = None - DCPUInst = None + CPUInst = '' + DCPUInst = '' CPU_PC = CPU.PC DCPU_PC = DCPU.DPC @@ -108,17 +102,17 @@ def close(): TraceFile = None Tracing = False -def deimtrace(opcode, code): - """Trace the DEIM instruction. - - opcode DEIM opcode - code the operation - """ - - log(f"deimtrace: Tracing={Tracing}, writing '{opcode} {code}'") - if Tracing: - TraceFile.write('%s\t%s\t' % (opcode, code)) - TraceFile.flush() +#def deimtrace(opcode, code): +# """Trace the DEIM instruction. +# +# opcode DEIM opcode +# code the operation +# """ +# +# log(f"deimtrace: Tracing={Tracing}, writing '{opcode} {code}'") +# if Tracing: +# TraceFile.write('%s %s\t' % (opcode, code)) +# TraceFile.flush() def dtrace(ddot, opcode, address=None): """Trace the display CPU. @@ -127,21 +121,24 @@ def dtrace(ddot, opcode, address=None): opcode display opcode address address for the opcode - Returns the trace string or None if not tracing. + Places the final trace string into DCPUInst. """ - log(f'Trace.dtrace: Tracing={Tracing}') - result = None + global DCPUInst + + log(f'Trace.dtrace: ddot={ddot}, opcode={opcode}, address={address}') + + # convert an int address to a string + if isinstance(address, int): + address = f'{address:05o}' if Tracing: if address is None: - result = '%s: %s\t' % (ddot, opcode) + DCPUInst = '%04o %s' % (ddot, opcode) else: - result = '%04o: %s\t%5.5o' % (ddot, opcode, address) + DCPUInst = '%04o %s %s' % (ddot, opcode, address) - log(f"dtrace: result='{result}'") - DCPUInst = result - return result + log(f"dtrace: DCPUInst='{DCPUInst}'") def itrace(dot, opcode, indirect=False, address=None): """Main CPU trace. @@ -151,53 +148,50 @@ def itrace(dot, opcode, indirect=False, address=None): indirect True if instruction was indirect address address for the instruction (if any) - Returns the trace string or None if not tracing. + Places the final trace string in CPUInst. """ - result = None + global CPUInst + + log(f'itrace: dot={dot}, opcode={opcode}, indirect={indirect}, address={address}') + log(f'itrace: Tracing={Tracing}, TraceMap[dot]={TraceMap[dot]}') if Tracing and TraceMap[dot]: char = '*' if indirect else '' if address is None: - result = '%04o\t%s\t%s' % (dot, opcode, char) + CPUInst = '%04o %s %s' % (dot, opcode, char) else: - result = '%04o\t%s\t%s%5.5o' % (dot, opcode, char, address) + CPUInst = '%04o %s %s%5.5o' % (dot, opcode, char, address) - log(f"itrace: result='{result}'") - CPUInst = result - return result + log(f"itrace: CPUInst='{CPUInst}'") -def itraceend(dispon): - """Trace at the end of one execution cycle. - - dispon True if the display was on - - Returns the trace string. - """ - - result = ('L=%1.1o AC=%6.6o PC=%6.6o' % (CPU.L, CPU.AC, CPU.PC)) - - if dispon: - result += ' DX=%5.5o DY=%5.5o' % (DCPU.DX, DCPU.DY) - - return result +#def itraceend(dispon): +# """Trace at the end of one execution cycle. +# +# dispon True if the display was on +# +# Places the final trace string in DCPUInst. +# """ +# +# global DCPUInst +# +# DCPUInst = f'L={CPU.L:1.1o} AC={CPU.AC:6.6oi} PC={CPU.PC:6.6o}' +# +# if dispon: +# DCPUInst += ' DX=%5.5o DY=%5.5o' % (DCPU.DX, DCPU.DY) def end_line(): """Write the line for this set of I/D instructions.""" - registers = ('L=%1.1o AC=%6.6o PC=%6.6o' % (CPU.L, CPU.AC, CPU.PC)) + registers = f'L={CPU.L:1o} AC={CPU.AC:6o} PC={CPU.PC:6o}' if DCPU.Running: - registers += ' DX=%5.5o DY=%5.5o' % (DCPU.DX, DCPU.DY) + registers += f' DX={DCPU.DX:5o} DY={DCPU.DY:5o}' - CPUInst = None - DCPUInst = None + TraceFile.write('%-25s %-30s%s\n' % (CPUInst, DCPUInst, registers)) - #TraceFile.write(f'{CPUInst:-50s}{DCPUInst:-40s} {registers}\n') - TraceFile.write('%-50s %-40s %s\n' % (CPUInst, DCPUInst, registers)) - -#def flush(self): -# TraceFile.flush() +def flush(): + TraceFile.flush() def comment(msg): """Write a line to the trace file.""" diff --git a/pymlac/pymlac b/pymlac/pymlac index d8a02f3..235407a 100755 --- a/pymlac/pymlac +++ b/pymlac/pymlac @@ -90,17 +90,16 @@ def start_running(cpu, dcpu, memory, ptrptp, ttyin): Trace.start() log(f'cpu.PC={cpu.PC}') - (cycles, tracestr) = cpu.execute_one_instruction() - log(f"start_running: cpu.execute_one_instruction returned ({cycles}, '{tracestr}')") - #Trace.itrace(tracestr) - (dcycles, dtracestr) = dcpu.execute_one_instruction() - log(f"start_running: dcpu.execute_one_instruction returned ({dcycles}, '{dtracestr}')") - #Trace.dtrace(dtracestr) + cycles = cpu.execute_one_instruction() + log(f'start_running: cpu.execute_one_instruction returned {cycles}') + dcycles = dcpu.execute_one_instruction() + log(f'start_running: dcpu.execute_one_instruction returned {dcycles}') ptrptp.ptr_tick(cycles) ptrptp.ptp_tick(cycles) ttyin.tick(cycles) Trace.end_line() + Trace.flush() Trace.close()