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Working on trace

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This commit is contained in:
Ross Wilson
2018-07-25 10:15:42 +07:00
parent 0452a7cf7d
commit 2dfdad6066
5 changed files with 265 additions and 292 deletions
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153
pymlac/MainCPU.py
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@@ -5,14 +5,11 @@ The Imlac main CPU.
import sys
from Globals import *
import Trace
from Globals import *
import log
log = log.Log('test.log', log.Log.DEBUG)
trace = Trace.Trace(TRACE_FILENAME)
class MainCPU(object):
@@ -219,22 +216,22 @@ class MainCPU(object):
tracestr = None
if indirect:
self.AC = (~address+1) & WORDMASK
tracestr = trace.itrace(self.dot, 'LWC', False, address)
tracestr = Trace.itrace(self.dot, 'LWC', False, address)
else:
self.AC = address
tracestr = trace.itrace(self.dot, 'LAW', False, address)
tracestr = Trace.itrace(self.dot, 'LAW', False, address)
return (1, tracestr)
def i_JMP(self, indirect, address, instruction):
eff_address = self.memory.eff_address(address, indirect)
self.PC = eff_address & PCMASK
tracestr = trace.itrace(self.dot, 'JMP', indirect, address)
tracestr = Trace.itrace(self.dot, 'JMP', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_DAC(self, indirect, address, instruction):
eff_address = self.memory.eff_address(address, indirect)
self.memory.put(self.AC, eff_address, False)
tracestr = trace.itrace(self.dot, 'DAC', indirect, address)
tracestr = Trace.itrace(self.dot, 'DAC', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_XAM(self, indirect, address, instruction):
@@ -242,7 +239,7 @@ class MainCPU(object):
tmp = self.memory.fetch(eff_address, False)
self.memory.put(self.AC, eff_address, False)
self.AC = tmp
tracestr = trace.itrace(self.dot, 'XAM', indirect, address)
tracestr = Trace.itrace(self.dot, 'XAM', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_ISZ(self, indirect, address, instruction):
@@ -251,34 +248,34 @@ class MainCPU(object):
self.memory.put(value, eff_address, False)
if value == 0:
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'ISZ', indirect, address)
tracestr = Trace.itrace(self.dot, 'ISZ', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_JMS(self, indirect, address, instruction):
eff_address = self.memory.eff_address(address, indirect)
self.memory.put(self.PC, eff_address, False)
self.PC = (eff_address + 1) & PCMASK
tracestr = trace.itrace(self.dot, 'JMS', indirect, address)
tracestr = Trace.itrace(self.dot, 'JMS', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_AND(self, indirect, address, instruction):
self.AC &= self.memory.fetch(address, indirect)
tracestr = trace.itrace(self.dot, 'AND', indirect, address)
tracestr = Trace.itrace(self.dot, 'AND', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_IOR(self, indirect, address, instruction):
self.AC |= self.memory.fetch(address, indirect)
tracestr = trace.itrace(self.dot, 'IOR', indirect, address)
tracestr = Trace.itrace(self.dot, 'IOR', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_XOR(self, indirect, address, instruction):
self.AC ^= self.memory.fetch(address, indirect)
tracestr = trace.itrace(self.dot, 'XOR', indirect, address)
tracestr = Trace.itrace(self.dot, 'XOR', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_LAC(self, indirect, address, instruction):
self.AC = self.memory.fetch(address, indirect)
tracestr = trace.itrace(self.dot, 'LAC', indirect, address)
tracestr = Trace.itrace(self.dot, 'LAC', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_ADD(self, indirect, address, instruction):
@@ -286,7 +283,7 @@ class MainCPU(object):
if self.AC & OVERFLOWMASK:
self.L = 0 if self.L else 1
self.AC &= WORDMASK
tracestr = trace.itrace(self.dot, 'ADD', indirect, address)
tracestr = Trace.itrace(self.dot, 'ADD', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_SUB(self, indirect, address, instruction):
@@ -296,14 +293,14 @@ class MainCPU(object):
if self.AC & OVERFLOWMASK:
self.L = 0 if self.L else 1
self.AC &= WORDMASK
tracestr = trace.itrace(self.dot, 'SUB', indirect, address)
tracestr = Trace.itrace(self.dot, 'SUB', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def i_SAM(self, indirect, address, instruction):
samaddr = self.BLOCKADDR(address)
if self.AC == self.memory.fetch(samaddr, indirect):
self.PC = (self.PC + 1) & PCMASK
tracestr = trace.itrace(self.dot, 'SAM', indirect, address)
tracestr = Trace.itrace(self.dot, 'SAM', indirect, address)
return (3, tracestr) if indirect else (2, tracestr)
def microcode(self, instruction):
@@ -345,141 +342,141 @@ class MainCPU(object):
if instruction & k:
combine.append(op)
tracestr = trace.itrace(self.dot, '+'.join(combine), False)
tracestr = Trace.itrace(self.dot, '+'.join(combine), False)
return (1, tracestr)
def i_DLA(self, indirect, address, instruction):
self.displaycpu.DPC = self.AC
tracestr = trace.itrace(self.dot, 'DLA')
tracestr = Trace.itrace(self.dot, 'DLA')
return (1, tracestr)
def i_CTB(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'CTB')
tracestr = Trace.itrace(self.dot, 'CTB')
return (1, tracestr)
def i_DOF(self, indirect, address, instruction):
log('self.displaycpu=%s' % str(self.displaycpu))
self.displaycpu.stop()
tracestr = trace.itrace(self.dot, 'DOF')
tracestr = Trace.itrace(self.dot, 'DOF')
return (1, tracestr)
def i_KRB(self, indirect, address, instruction):
self.AC |= self.kbd.read()
tracestr = trace.itrace(self.dot, 'KRB')
tracestr = Trace.itrace(self.dot, 'KRB')
return (1, tracestr)
def i_KCF(self, indirect, address, instruction):
self.kbd.clear()
tracestr = trace.itrace(self.dot, 'KCF')
tracestr = Trace.itrace(self.dot, 'KCF')
return (1, tracestr)
def i_KRC(self, indirect, address, instruction):
self.AC |= self.kbd.read()
self.kbd.clear()
tracestr = trace.itrace(self.dot, 'KRC')
tracestr = Trace.itrace(self.dot, 'KRC')
return (1, tracestr)
def i_RRB(self, indirect, address, instruction):
self.AC |= self.ttyin.read()
tracestr = trace.itrace(self.dot, 'RRB')
tracestr = Trace.itrace(self.dot, 'RRB')
return (1, tracestr)
def i_RCF(self, indirect, address, instruction):
self.ttyin.clear()
tracestr = trace.itrace(self.dot, 'RCF')
tracestr = Trace.itrace(self.dot, 'RCF')
return (1, tracestr)
def i_RRC(self, indirect, address, instruction):
self.AC |= self.ttyin.read()
self.ttyin.clear()
tracestr = trace.itrace(self.dot, 'RRC')
tracestr = Trace.itrace(self.dot, 'RRC')
return (1, tracestr)
def i_TPR(self, indirect, address, instruction):
self.ttyout.write(self.AC & 0xff)
tracestr = trace.itrace(self.dot, 'TPR')
tracestr = Trace.itrace(self.dot, 'TPR')
return (1, tracestr)
def i_TCF(self, indirect, address, instruction):
self.ttyout.clear()
tracestr = trace.itrace(self.dot, 'TCF')
tracestr = Trace.itrace(self.dot, 'TCF')
return (1, tracestr)
def i_TPC(self, indirect, address, instruction):
self.ttyout.write(self.AC & 0xff)
self.ttyout.clear()
tracestr = trace.itrace(self.dot, 'TPC')
tracestr = Trace.itrace(self.dot, 'TPC')
return (1, tracestr)
def i_HRB(self, indirect, address, instruction):
self.AC |= self.ptrptp.read()
tracestr = trace.itrace(self.dot, 'HRB')
tracestr = Trace.itrace(self.dot, 'HRB')
return (1, tracestr)
def i_HOF(self, indirect, address, instruction):
self.ptrptp.stop()
tracestr = trace.itrace(self.dot, 'HOF')
tracestr = Trace.itrace(self.dot, 'HOF')
return (1, tracestr)
def i_HON(self, indirect, address, instruction):
self.ptrptp.start()
tracestr = trace.itrace(self.dot, 'HON')
tracestr = Trace.itrace(self.dot, 'HON')
return (1, tracestr)
def i_STB(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'STB')
tracestr = Trace.itrace(self.dot, 'STB')
return (1, tracestr)
def i_SCF(self, indirect, address, instruction):
self.Sync40Hz = 0
tracestr = trace.itrace(self.dot, 'SCF')
tracestr = Trace.itrace(self.dot, 'SCF')
return (1, tracestr)
def i_IOS(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOS')
tracestr = Trace.itrace(self.dot, 'IOS')
return (1, tracestr)
def i_IOT101(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT101')
tracestr = Trace.itrace(self.dot, 'IOT101')
return (1, tracestr)
def i_IOT111(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT111')
tracestr = Trace.itrace(self.dot, 'IOT111')
return (1, tracestr)
def i_IOT131(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT131')
tracestr = Trace.itrace(self.dot, 'IOT131')
return (1, tracestr)
def i_IOT132(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT132')
tracestr = Trace.itrace(self.dot, 'IOT132')
return (1, tracestr)
def i_IOT134(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT134')
tracestr = Trace.itrace(self.dot, 'IOT134')
return (1, tracestr)
def i_IOT141(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOT141')
tracestr = Trace.itrace(self.dot, 'IOT141')
return (1, tracestr)
def i_IOF(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'IOF')
tracestr = Trace.itrace(self.dot, 'IOF')
return (1, tracestr)
def i_ION(self, indirect, address, instruction):
tracestr = trace.itrace(self.dot, 'ION')
tracestr = Trace.itrace(self.dot, 'ION')
return (1, tracestr)
def i_PPC(self, indirect, address, instruction):
self.ptrptp.punch(self.AC & 0xff)
tracestr = trace.itrace(self.dot, 'PPC')
tracestr = Trace.itrace(self.dot, 'PPC')
return (1, tracestr)
def i_PSF(self, indirect, address, instruction):
if self.ptrptp.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'PSF')
tracestr = Trace.itrace(self.dot, 'PSF')
return (1, tracestr)
def i_RAL1(self, indirect, address, instruction):
@@ -487,7 +484,7 @@ class MainCPU(object):
newac = (self.AC << 1) | self.L
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAL', False, 1)
tracestr = Trace.itrace(self.dot, 'RAL', False, 1)
return (1, tracestr)
def i_RAL2(self, indirect, address, instruction):
@@ -499,7 +496,7 @@ class MainCPU(object):
newac = (self.AC << 1) | self.L
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAL', False, 2)
tracestr = Trace.itrace(self.dot, 'RAL', False, 2)
return (1, tracestr)
def i_RAL3(self, indirect, address, instruction):
@@ -515,7 +512,7 @@ class MainCPU(object):
newac = (self.AC << 1) | self.L
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAL', False, 3)
tracestr = Trace.itrace(self.dot, 'RAL', False, 3)
return (1, tracestr)
def i_RAR1(self, indirect, address, instruction):
@@ -523,7 +520,7 @@ class MainCPU(object):
newac = (self.AC >> 1) | (self.L << 15)
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAR', False, 1)
tracestr = Trace.itrace(self.dot, 'RAR', False, 1)
return (1, tracestr)
def i_RAR2(self, indirect, address, instruction):
@@ -535,7 +532,7 @@ class MainCPU(object):
newac = (self.AC >> 1) | (self.L << 15)
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAR', False, 2)
tracestr = Trace.itrace(self.dot, 'RAR', False, 2)
return (1, tracestr)
def i_RAR3(self, indirect, address, instruction):
@@ -551,41 +548,41 @@ class MainCPU(object):
newac = (self.AC >> 1) | (self.L << 15)
self.L = newl
self.AC = newac & WORDMASK
tracestr = trace.itrace(self.dot, 'RAR', False, 3)
tracestr = Trace.itrace(self.dot, 'RAR', False, 3)
return (1, tracestr)
def i_SAL1(self, indirect, address, instruction):
high_bit = self.AC & HIGHBITMASK
value = self.AC & 0o37777
self.AC = (value << 1) | high_bit
tracestr = trace.itrace(self.dot, 'SAL', False, 1)
tracestr = Trace.itrace(self.dot, 'SAL', False, 1)
return (1, tracestr)
def i_SAL2(self, indirect, address, instruction):
high_bit = self.AC & HIGHBITMASK
value = self.AC & 0o17777
self.AC = (value << 2) | high_bit
tracestr = trace.itrace(self.dot, 'SAL', False, 2)
tracestr = Trace.itrace(self.dot, 'SAL', False, 2)
return (1, tracestr)
def i_SAL3(self, indirect, address, instruction):
high_bit = self.AC & HIGHBITMASK
value = self.AC & 0o07777
self.AC = (value << 3) | high_bit
tracestr = trace.itrace(self.dot, 'SAL', False, 3)
tracestr = Trace.itrace(self.dot, 'SAL', False, 3)
return (1, tracestr)
def i_SAR1(self, indirect, address, instruction):
high_bit = self.AC & HIGHBITMASK
self.AC = (self.AC >> 1) | high_bit
tracestr = trace.itrace(self.dot, 'SAR', False, 1)
tracestr = Trace.itrace(self.dot, 'SAR', False, 1)
return (1, tracestr)
def i_SAR2(self, indirect, address, instruction):
high_bit = self.AC & HIGHBITMASK
self.AC = (self.AC >> 1) | high_bit
self.AC = (self.AC >> 1) | high_bit
tracestr = trace.itrace(self.dot, 'SAR', False, 2)
tracestr = Trace.itrace(self.dot, 'SAR', False, 2)
return (1, tracestr)
def i_SAR3(self, indirect, address, instruction):
@@ -593,121 +590,121 @@ class MainCPU(object):
self.AC = (self.AC >> 1) | high_bit
self.AC = (self.AC >> 1) | high_bit
self.AC = (self.AC >> 1) | high_bit
tracestr = trace.itrace(self.dot, 'SAR', False, 3)
tracestr = Trace.itrace(self.dot, 'SAR', False, 3)
return (1, tracestr)
def i_DON(self, indirect, address, instruction):
self.display.clear()
self.displaycpu.DRSindex = 0
self.displaycpu.start()
tracestr = trace.itrace(self.dot, 'DON')
tracestr = Trace.itrace(self.dot, 'DON')
return (1, tracestr)
def i_ASZ(self):
if self.AC == 0:
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'ASZ')
tracestr = Trace.itrace(self.dot, 'ASZ')
return (1, tracestr)
def i_ASN(self):
if self.AC != 0:
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'ASN')
tracestr = Trace.itrace(self.dot, 'ASN')
return (1, tracestr)
def i_ASP(self):
if not (self.AC & HIGHBITMASK):
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'ASP')
tracestr = Trace.itrace(self.dot, 'ASP')
return (1, tracestr)
def i_ASM(self):
if (self.AC & HIGHBITMASK):
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'ASM')
tracestr = Trace.itrace(self.dot, 'ASM')
return (1, tracestr)
def i_LSZ(self):
if self.L == 0:
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'LSZ')
tracestr = Trace.itrace(self.dot, 'LSZ')
return (1, tracestr)
def i_LSN(self):
if self.L != 0:
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'LSN')
tracestr = Trace.itrace(self.dot, 'LSN')
return (1, tracestr)
def i_DSF(self):
if self.displaycpu.ison():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'DSF')
tracestr = Trace.itrace(self.dot, 'DSF')
return (1, tracestr)
def i_DSN(self):
if not self.displaycpu.ison():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'DSN')
tracestr = Trace.itrace(self.dot, 'DSN')
return (1, tracestr)
def i_KSF(self):
if self.kbd.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'KSF')
tracestr = Trace.itrace(self.dot, 'KSF')
return (1, tracestr)
def i_KSN(self):
if not self.kbd.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'KSN')
tracestr = Trace.itrace(self.dot, 'KSN')
return (1, tracestr)
def i_RSF(self):
if self.ttyin.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'RSF')
tracestr = Trace.itrace(self.dot, 'RSF')
return (1, tracestr)
def i_RSN(self):
if not self.ttyin.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'RSN')
tracestr = Trace.itrace(self.dot, 'RSN')
return (1, tracestr)
def i_TSF(self):
if self.ttyout.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'TSF')
tracestr = Trace.itrace(self.dot, 'TSF')
return (1, tracestr)
def i_TSN(self):
if not self.ttyout.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'TSN')
tracestr = Trace.itrace(self.dot, 'TSN')
return (1, tracestr)
def i_SSF(self):
if self.display.ready(): # skip if 40Hz sync on
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'SSF')
tracestr = Trace.itrace(self.dot, 'SSF')
return (1, tracestr)
def i_SSN(self):
if not self.display.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'SSN')
tracestr = Trace.itrace(self.dot, 'SSN')
return (1, tracestr)
def i_HSF(self):
if self.ptrptp.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'HSF')
tracestr = Trace.itrace(self.dot, 'HSF')
return (1, tracestr)
def i_HSN(self):
if not self.ptrptp.ready():
self.PC = (self.PC + 1) & WORDMASK
tracestr = trace.itrace(self.dot, 'HSN')
tracestr = Trace.itrace(self.dot, 'HSN')
return (1, tracestr)