mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Got trace working
This commit is contained in:
Ross Wilson
@@ -10,6 +10,7 @@ import sys
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from Globals import *
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import Trace
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trace = Trace.Trace(TRACE_FILENAME)
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class MainCPU(object):
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@@ -181,7 +182,6 @@ class MainCPU(object):
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return self.main_decode.get(opcode, self.illegal)(indirect,
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address,
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instruction)
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def illegal(self, indirect, address, instruction):
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"""Handle an illegal instruction."""
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@@ -205,22 +205,22 @@ class MainCPU(object):
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def i_LAW_LWC(self, indirect, address, instruction):
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if indirect:
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self.AC = ~address & WORDMASK
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Trace.itrace('LWC', False, address)
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trace.itrace('LWC', False, address)
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else:
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self.AC = address
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Trace.itrace('LAW', False, address)
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trace.itrace('LAW', False, address)
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return 1
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def i_JMP(self, indirect, address, instruction):
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address = self.memory.eff_address(address, indirect)
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self.PC = address & PCMASK
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Trace.itrace('JMP', indirect, address)
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trace.itrace('JMP', indirect, address)
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return 3 if indirect else 2
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def i_DAC(self, indirect, address, instruction):
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address = self.memory.eff_address(address, indirect)
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self.memory.put(self.AC, address, False)
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Trace.itrace('DAC', indirect, address)
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trace.itrace('DAC', indirect, address)
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return 3 if indirect else 2
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def i_XAM(self, indirect, address, instruction):
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@@ -228,7 +228,7 @@ class MainCPU(object):
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tmp = self.memory.fetch(address, False)
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self.memory.put(self.AC, address, False)
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self.AC = tmp
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Trace.itrace('XAM', indirect, address)
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trace.itrace('XAM', indirect, address)
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return 3 if indirect else 2
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def i_ISZ(self, indirect, address, instruction):
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@@ -237,34 +237,34 @@ class MainCPU(object):
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self.memory.put(value, address, False)
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if value == 0:
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('ISZ', indirect, address)
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trace.itrace('ISZ', indirect, address)
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return 3 if indirect else 2
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def i_JMS(self, indirect, address, instruction):
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address = self.memory.eff_address(address, indirect)
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self.memory.put(self.PC, address, False)
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self.PC = (address + 1) & PCMASK
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Trace.itrace('JMS', indirect, address)
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trace.itrace('JMS', indirect, address)
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return 3 if indirect else 2
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def i_AND(self, indirect, address, instruction):
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self.AC &= self.memory.fetch(address, indirect)
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Trace.itrace('AND', indirect, address)
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trace.itrace('AND', indirect, address)
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return 3 if indirect else 2
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def i_IOR(self, indirect, address, instruction):
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self.AC |= self.memory.fetch(address, indirect)
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Trace.itrace('IOR', indirect, address)
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trace.itrace('IOR', indirect, address)
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return 3 if indirect else 2
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def i_XOR(self, indirect, address, instruction):
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self.AC ^= self.memory.fetch(address, indirect)
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Trace.itrace('XOR', indirect, address)
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trace.itrace('XOR', indirect, address)
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return 3 if indirect else 2
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def i_LAC(self, indirect, address, instruction):
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self.AC = self.memory.fetch(address, indirect)
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Trace.itrace('LAC', indirect, address)
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trace.itrace('LAC', indirect, address)
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return 3 if indirect else 2
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def i_ADD(self, indirect, address, instruction):
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@@ -272,7 +272,7 @@ class MainCPU(object):
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if self.AC & OVERFLOWMASK:
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self.L = (~self.L) & 01
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self.AC &= WORDMASK
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Trace.itrace('ADD', indirect, address)
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trace.itrace('ADD', indirect, address)
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return 3 if indirect else 2
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def i_SUB(self, indirect, address, instruction):
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@@ -282,14 +282,14 @@ class MainCPU(object):
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if self.AC & OVERFLOWMASK:
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self.L = ~self.L
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self.AC &= WORDMASK
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Trace.itrace('SUB', indirect, address)
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trace.itrace('SUB', indirect, address)
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return 3 if indirect else 2
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def i_SAM(self, indirect, address, instruction):
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samaddr = self.BLOCKADDR(address)
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if self.AC == self.memory.fetch(samaddr, indirect):
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self.PC = (self.PC + 1) & PCMASK
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Trace.itrace('SAM', indirect, address)
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trace.itrace('SAM', indirect, address)
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return 3 if indirect else 2
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def microcode(self, instruction):
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@@ -331,140 +331,140 @@ class MainCPU(object):
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if instruction & k:
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combine.append(op)
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Trace.itrace('+'.join(combine), False)
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trace.itrace('+'.join(combine), False)
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return 1
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def i_DLA(self, indirect, address, instruction):
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self.displaycpu.DPC = self.AC
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Trace.itrace('DLA')
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trace.itrace('DLA')
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return 1
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def i_CTB(self, indirect, address, instruction):
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Trace.itrace('CTB')
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trace.itrace('CTB')
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return 1
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def i_DOF(self, indirect, address, instruction):
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self.displaycpu.stop()
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Trace.itrace('DOF')
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trace.itrace('DOF')
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return 1
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def i_KRB(self, indirect, address, instruction):
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self.AC |= self.kbd.read()
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Trace.itrace('KRB')
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trace.itrace('KRB')
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return 1
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def i_KCF(self, indirect, address, instruction):
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self.kbd.clear()
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Trace.itrace('KCF')
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trace.itrace('KCF')
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return 1
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def i_KRC(self, indirect, address, instruction):
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self.AC |= self.kbd.read()
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self.kbd.clear()
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Trace.itrace('KRC')
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trace.itrace('KRC')
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return 1
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def i_RRB(self, indirect, address, instruction):
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self.AC |= self.ttyin.read()
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Trace.itrace('RRB')
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trace.itrace('RRB')
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return 1
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def i_RCF(self, indirect, address, instruction):
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self.ttyin.clear()
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Trace.itrace('RCF')
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trace.itrace('RCF')
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return 1
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def i_RRC(self, indirect, address, instruction):
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self.AC |= self.ttyin.read()
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self.ttyin.clear()
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Trace.itrace('RRC')
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trace.itrace('RRC')
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return 1
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def i_TPR(self, indirect, address, instruction):
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self.ttyout.write(self.AC & 0xff)
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Trace.itrace('TPR')
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trace.itrace('TPR')
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return 1
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def i_TCF(self, indirect, address, instruction):
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self.ttyout.clear()
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Trace.itrace('TCF')
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trace.itrace('TCF')
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return 1
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def i_TPC(self, indirect, address, instruction):
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self.ttyout.write(self.AC & 0xff)
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self.ttyout.clear()
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Trace.itrace('TPC')
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trace.itrace('TPC')
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return 1
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def i_HRB(self, indirect, address, instruction):
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self.AC |= self.ptrptp.read()
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Trace.itrace('HRB')
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trace.itrace('HRB')
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return 1
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def i_HOF(self, indirect, address, instruction):
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self.ptrptp.stop()
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Trace.itrace('HOF')
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trace.itrace('HOF')
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return 1
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def i_HON(self, indirect, address, instruction):
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self.ptrptp.start()
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Trace.itrace('HON')
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trace.itrace('HON')
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return 1
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def i_STB(self, indirect, address, instruction):
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Trace.itrace('STB')
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trace.itrace('STB')
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return 1
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def i_SCF(self, indirect, address, instruction):
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self.Sync40Hz = 0
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Trace.itrace('SCF')
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trace.itrace('SCF')
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return 1
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def i_IOS(self, indirect, address, instruction):
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Trace.itrace('IOS')
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trace.itrace('IOS')
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return 1
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def i_IOT101(self, indirect, address, instruction):
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Trace.itrace('IOT101')
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trace.itrace('IOT101')
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return 1
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def i_IOT111(self, indirect, address, instruction):
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Trace.itrace('IOT111')
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trace.itrace('IOT111')
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return 1
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def i_IOT131(self, indirect, address, instruction):
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Trace.itrace('IOT131')
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trace.itrace('IOT131')
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return 1
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def i_IOT132(self, indirect, address, instruction):
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Trace.itrace('IOT132')
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trace.itrace('IOT132')
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return 1
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def i_IOT134(self, indirect, address, instruction):
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Trace.itrace('IOT134')
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trace.itrace('IOT134')
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return 1
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def i_IOT141(self, indirect, address, instruction):
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Trace.itrace('IOT141')
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trace.itrace('IOT141')
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return 1
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def i_IOF(self, indirect, address, instruction):
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Trace.itrace('IOF')
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trace.itrace('IOF')
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return 1
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def i_ION(self, indirect, address, instruction):
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Trace.itrace('ION')
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trace.itrace('ION')
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return 1
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def i_PPC(self, indirect, address, instruction):
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self.ptrptp.punch(self.AC & 0xff)
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Trace.itrace('PPC')
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trace.itrace('PPC')
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return 1
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def i_PSF(self, indirect, address, instruction):
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if self.ptrptp.ready():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('PSF')
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trace.itrace('PSF')
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return 1
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def i_RAL1(self, indirect, address, instruction):
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@@ -472,7 +472,7 @@ class MainCPU(object):
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAL', False, 1)
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trace.itrace('RAL', False, 1)
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return 1
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def i_RAL2(self, indirect, address, instruction):
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@@ -484,7 +484,7 @@ class MainCPU(object):
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAL', False, 2)
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trace.itrace('RAL', False, 2)
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return 1
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def i_RAL3(self, indirect, address, instruction):
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@@ -500,7 +500,7 @@ class MainCPU(object):
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAL', False, 3)
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trace.itrace('RAL', False, 3)
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return 1
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def i_RAR1(self, indirect, address, instruction):
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@@ -508,7 +508,7 @@ class MainCPU(object):
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAR', False, 1)
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trace.itrace('RAR', False, 1)
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return 1
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def i_RAR2(self, indirect, address, instruction):
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@@ -520,7 +520,7 @@ class MainCPU(object):
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAR', False, 2)
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trace.itrace('RAR', False, 2)
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return 1
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def i_RAR3(self, indirect, address, instruction):
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@@ -536,41 +536,41 @@ class MainCPU(object):
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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Trace.itrace('RAR', False, 3)
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trace.itrace('RAR', False, 3)
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return 1
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def i_SAL1(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
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value = self.AC & 037777
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self.AC = (value << 1) | high_bit
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Trace.itrace('SAL', False, 1)
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trace.itrace('SAL', False, 1)
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return 1
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def i_SAL2(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
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value = self.AC & 017777
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self.AC = (value << 2) | high_bit
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Trace.itrace('SAL', False, 2)
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trace.itrace('SAL', False, 2)
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return 1
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def i_SAL3(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
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value = self.AC & 007777
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self.AC = (value << 3) | high_bit
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Trace.itrace('SAL', False, 3)
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trace.itrace('SAL', False, 3)
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return 1
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def i_SAR1(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
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self.AC = (self.AC >> 1) | high_bit
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Trace.itrace('SAR', False, 1)
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trace.itrace('SAR', False, 1)
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return 1
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def i_SAR2(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
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self.AC = (self.AC >> 1) | high_bit
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self.AC = (self.AC >> 1) | high_bit
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Trace.itrace('SAR', False, 2)
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trace.itrace('SAR', False, 2)
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return 1
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def i_SAR3(self, indirect, address, instruction):
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@@ -578,120 +578,120 @@ class MainCPU(object):
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self.AC = (self.AC >> 1) | high_bit
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self.AC = (self.AC >> 1) | high_bit
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self.AC = (self.AC >> 1) | high_bit
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Trace.itrace('SAR', False, 3)
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trace.itrace('SAR', False, 3)
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return 1
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def i_DON(self, indirect, address, instruction):
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self.displaycpu.DRSindex = 0
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self.displaycpu.start()
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Trace.itrace('DON')
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trace.itrace('DON')
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return 1
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def i_ASZ(self):
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if self.AC == 0:
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('ASZ')
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trace.itrace('ASZ')
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return 1
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def i_ASN(self):
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if self.AC != 0:
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('ASN')
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trace.itrace('ASN')
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return 1
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def i_ASP(self):
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if not (self.AC & HIGHBITMASK):
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('ASP')
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trace.itrace('ASP')
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return 1
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def i_ASM(self):
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if (self.AC & HIGHBITMASK):
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('ASM')
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trace.itrace('ASM')
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return 1
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def i_LSZ(self):
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if self.L == 0:
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('LSZ')
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trace.itrace('LSZ')
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return 1
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def i_LSN(self):
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if self.L != 0:
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('LSN')
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trace.itrace('LSN')
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return 1
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def i_DSF(self):
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if self.displaycpu.ison():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('DSF')
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trace.itrace('DSF')
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return 1
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def i_DSN(self):
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if not self.displaycpu.ison():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('DSN')
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trace.itrace('DSN')
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return 1
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def i_KSF(self):
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if self.kbd.ready():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('KSF')
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trace.itrace('KSF')
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return 1
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def i_KSN(self):
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if not self.kbd.ready():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('KSN')
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trace.itrace('KSN')
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return 1
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def i_RSF(self):
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if self.ttyin.ready():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('RSF')
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trace.itrace('RSF')
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return 1
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def i_RSN(self):
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if not self.ttyin.ready():
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self.PC = (self.PC + 1) & WORDMASK
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Trace.itrace('RSN')
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trace.itrace('RSN')
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return 1
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def i_TSF(self):
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if self.ttyout.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('TSF')
|
||||
trace.itrace('TSF')
|
||||
return 1
|
||||
|
||||
def i_TSN(self):
|
||||
if not self.ttyout.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('TSN')
|
||||
trace.itrace('TSN')
|
||||
return 1
|
||||
|
||||
def i_SSF(self):
|
||||
if self.display.ready(): # skip if 40Hz sync on
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('SSF')
|
||||
trace.itrace('SSF')
|
||||
return 1
|
||||
|
||||
def i_SSN(self):
|
||||
if not self.display.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('SSN')
|
||||
trace.itrace('SSN')
|
||||
return 1
|
||||
|
||||
def i_HSF(self):
|
||||
if self.ptrptp.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('HSF')
|
||||
trace.itrace('HSF')
|
||||
return 1
|
||||
|
||||
def i_HSN(self):
|
||||
if not self.ptrptp.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
Trace.itrace('HSN')
|
||||
trace.itrace('HSN')
|
||||
return 1
|
||||
|
||||
|
||||
172
pymlac/Trace.py
172
pymlac/Trace.py
@@ -2,89 +2,129 @@
|
||||
|
||||
"""
|
||||
The Imlac trace stuff.
|
||||
|
||||
Simple usage:
|
||||
import Trace
|
||||
trace = Trace.Trace('my_log.log', maincpu, dispcpu)
|
||||
trace.itrace(msg)
|
||||
|
||||
Based on the 'borg' recipe from [http://code.activestate.com/recipes/66531/].
|
||||
"""
|
||||
|
||||
|
||||
import time
|
||||
import datetime
|
||||
import os
|
||||
|
||||
from Globals import *
|
||||
|
||||
# module-level state variables
|
||||
tracing = False
|
||||
tracefile = None
|
||||
cpu = None
|
||||
dcpu = None
|
||||
|
||||
class Trace(object):
|
||||
|
||||
def init(filename, maincpu, displaycpu):
|
||||
global tracing, tracefile, cpu, dcpu
|
||||
__shared_state = {} # this __dict__ shared by ALL instances
|
||||
|
||||
tracing = True
|
||||
tracefile = open(filename, 'wa')
|
||||
trace('%s trace\n%s\n' % (PYMLAC_VERSION, '-'*60))
|
||||
tracing = False
|
||||
comment = None
|
||||
def __init__(self, filename, maincpu=None, displaycpu=None):
|
||||
"""Initialize the trace:
|
||||
|
||||
cpu = maincpu
|
||||
dcpu = displaycpu
|
||||
filename name of the trace file
|
||||
maincpu the main CPU object (may be added later)
|
||||
displaycpu the display CPU object (may be added later)
|
||||
"""
|
||||
|
||||
def close():
|
||||
global tracing, tracefile
|
||||
# ensure same state as all other instances
|
||||
self.__dict__ = Trace.__shared_state
|
||||
|
||||
tracefile.close()
|
||||
tracing = False
|
||||
tracefile = None
|
||||
# set internal state
|
||||
self.tracing = True
|
||||
self.tracefile = filename
|
||||
try:
|
||||
os.remove(filename)
|
||||
except:
|
||||
pass
|
||||
self.tracefile = open(filename, 'wb')
|
||||
self.tracefile.write('%s trace\n%s\n' % (PYMLAC_VERSION, '-'*60))
|
||||
|
||||
def trace(msg):
|
||||
if tracing:
|
||||
tracefile.write(msg)
|
||||
|
||||
def deimtrace(opcode, code):
|
||||
if tracing:
|
||||
tracefile.write('%s\t%s\t' % (opcode, code))
|
||||
tracefile.flush()
|
||||
self.cpu = maincpu
|
||||
self.dcpu = displaycpu
|
||||
|
||||
def dtrace(opcode, address=None):
|
||||
if tracing:
|
||||
if address is None:
|
||||
tracefile.write('%s\t\t' % opcode)
|
||||
else:
|
||||
tracefile.write('%s\t%5.5o\t' % (opcode, address))
|
||||
tracefile.flush()
|
||||
def add_maincpu(self, maincpu):
|
||||
"""Add the main CPU object."""
|
||||
|
||||
def itrace(opcode, indirect=False, address=None):
|
||||
if tracing:
|
||||
char = '*' if indirect else ''
|
||||
if address is None:
|
||||
tracefile.write('%s\t%s\t' % (opcode, char))
|
||||
else:
|
||||
tracefile.write('%s\t%s%5.5o\t' % (opcode, char, address))
|
||||
tracefile.flush()
|
||||
self.cpu = maincpu
|
||||
|
||||
def itraceend(dispon):
|
||||
if dispon:
|
||||
trace('L=%1.1o AC=%6.6o DX=%5.5o DY=%6.6o\n' %
|
||||
(cpu.L, cpu.AC, dcpu.DX, dcpu.DY))
|
||||
else:
|
||||
trace('L=%1.1o AC=%6.6o\n' % (cpu.L, cpu.AC))
|
||||
def add_dispcpu(self, dispcpu):
|
||||
"""Add the display CPU object."""
|
||||
|
||||
# time the instruction execution
|
||||
# # get time
|
||||
# to = datetime.datetime.now()
|
||||
# hr = to.hour
|
||||
# min = to.minute
|
||||
# sec = to.second
|
||||
# msec = to.microsecond
|
||||
# trace(' %02d:%02d:%02d.%06d' % (hr, min, sec, msec))
|
||||
self.dcpu = dispcpu
|
||||
|
||||
tracefile.flush()
|
||||
def close(self):
|
||||
"""Close trace."""
|
||||
|
||||
def comment(msg):
|
||||
tracefile.write(msg+'\n')
|
||||
tracefile.flush()
|
||||
self.tracefile.close()
|
||||
self.tracing = False
|
||||
self.tracefile = None
|
||||
|
||||
def settrace(new_tracing):
|
||||
global tracing
|
||||
def deimtrace(self, opcode, code):
|
||||
"""Trace the DEIM instruction.
|
||||
|
||||
tracing = new_tracing
|
||||
opcode DEIM opcode
|
||||
code the operation
|
||||
"""
|
||||
|
||||
if self.tracing:
|
||||
self.tracefile.write('%s\t%s\t' % (opcode, code))
|
||||
self.tracefile.flush()
|
||||
|
||||
def dtrace(self, opcode, address=None):
|
||||
"""Trace the display CPU.
|
||||
|
||||
opcode display opcode
|
||||
address address for the opcode
|
||||
"""
|
||||
|
||||
if self.tracing:
|
||||
if address is None:
|
||||
self.tracefile.write('%s\t\t' % opcode)
|
||||
else:
|
||||
self.tracefile.write('%s\t%5.5o\t' % (opcode, address))
|
||||
self.tracefile.flush()
|
||||
|
||||
def itrace(self, opcode, indirect=False, address=None):
|
||||
"""Main CPU trace.
|
||||
|
||||
opcode the main CPU opcode
|
||||
indirect True if instruction was indirect
|
||||
adress address for the instruction (if any)
|
||||
"""
|
||||
|
||||
if self.tracing:
|
||||
char = '*' if indirect else ''
|
||||
if address is None:
|
||||
self.tracefile.write('%s\t%s\t' % (opcode, char))
|
||||
else:
|
||||
self.tracefile.write('%s\t%s%5.5o\t' % (opcode, char, address))
|
||||
self.tracefile.flush()
|
||||
|
||||
def itraceend(self, dispon):
|
||||
"""Trace at the end of one execution cycle.
|
||||
|
||||
dispon True if the display was on
|
||||
"""
|
||||
|
||||
self.tracefile.write('L=%1.1o AC=%6.6o PC=%6.6o'
|
||||
% (self.cpu.L, self.cpu.AC, self.cpu.PC))
|
||||
|
||||
if dispon:
|
||||
self.tracefile.write(' DX=%5.5o DY=%6.6o'
|
||||
% (self.dcpu.DX, self.dcpu.DY))
|
||||
self.tracefile.write('\n')
|
||||
|
||||
self.tracefile.flush()
|
||||
|
||||
def comment(self, msg):
|
||||
"""Add a comment to the trace."""
|
||||
|
||||
self.tracefile.write(msg+'\n')
|
||||
self.tracefile.flush()
|
||||
|
||||
def settrace(self, new_tracing):
|
||||
"""Set the trace ON or OFF."""
|
||||
|
||||
self.tracing = new_tracing
|
||||
|
||||
@@ -26,8 +26,7 @@ import Memory
|
||||
import PtrPtp
|
||||
import Trace
|
||||
|
||||
import log
|
||||
log = log.Log('test_CPU.log', log.Log.DEBUG)
|
||||
trace = Trace.Trace(TRACE_FILENAME)
|
||||
|
||||
|
||||
class TestCPU(object):
|
||||
@@ -247,6 +246,7 @@ class TestCPU(object):
|
||||
self.used_cycles= 0
|
||||
for _ in range(number):
|
||||
cycles = self.cpu.execute_one_instruction()
|
||||
trace.itraceend(False)
|
||||
self.ptrptp.ptr_tick(cycles)
|
||||
self.ptrptp.ptp_tick(cycles)
|
||||
self.used_cycles += cycles
|
||||
@@ -269,6 +269,7 @@ class TestCPU(object):
|
||||
self.used_cycles= 0
|
||||
while True:
|
||||
cycles = self.cpu.execute_one_instruction()
|
||||
trace.itraceend(False)
|
||||
self.ptrptp.ptr_tick(cycles)
|
||||
self.ptrptp.ptp_tick(cycles)
|
||||
self.used_cycles += cycles
|
||||
@@ -472,17 +473,6 @@ class TestCPU(object):
|
||||
else:
|
||||
raise Exception('setd: bad state: %s' % str(state))
|
||||
|
||||
def debug_operation(self, op, var1, var2):
|
||||
"""Write operation to log file."""
|
||||
|
||||
if var1:
|
||||
if var2:
|
||||
log.debug('Operation: %s %s %s' % (op, var1, var2))
|
||||
else:
|
||||
log.debug('Operation: %s %s' % (op, var1))
|
||||
else:
|
||||
log.debug('Operation: %s' % op)
|
||||
|
||||
def execute(self, test, filename):
|
||||
"""Execute test string in 'test'."""
|
||||
|
||||
@@ -501,13 +491,18 @@ class TestCPU(object):
|
||||
self.cpu.running = True
|
||||
self.display_state = False
|
||||
|
||||
trace_filename = filename + '.trace'
|
||||
Trace.init(trace_filename, self.cpu, None)
|
||||
# prepare the trace
|
||||
trace.add_maincpu(self.cpu)
|
||||
|
||||
# clear registers and memory to 0 first
|
||||
self.allreg(self.reg_all_value, None)
|
||||
self.allmem(self.mem_all_value, None)
|
||||
|
||||
# show the DSL we are about execute
|
||||
trace.comment('')
|
||||
trace.comment(test)
|
||||
trace.comment('-'*80)
|
||||
|
||||
# interpret the test instructions
|
||||
suite = test.split(';')
|
||||
for instruction in suite:
|
||||
@@ -525,8 +520,6 @@ class TestCPU(object):
|
||||
fld1 = fields[1].strip().lower()
|
||||
fld2 = fields[2].strip().lower()
|
||||
|
||||
self.debug_operation(opcode, fld1, fld2)
|
||||
|
||||
# cll the correct DSL primitive
|
||||
if opcode == 'setreg':
|
||||
r = self.setreg(fld1, fld2)
|
||||
@@ -600,8 +593,6 @@ class TestCPU(object):
|
||||
def main(self, filename):
|
||||
"""Execute CPU tests from 'filename'."""
|
||||
|
||||
log.debug("Running test file '%s'" % filename)
|
||||
|
||||
# get all tests from file
|
||||
with open(filename, 'rb') as fd:
|
||||
lines = fd.readlines()
|
||||
@@ -622,8 +613,9 @@ class TestCPU(object):
|
||||
|
||||
if line[0] in ('\t', ' '): # continuation
|
||||
if test:
|
||||
test += '; '
|
||||
test += line[1:]
|
||||
if not test.endswith(';'):
|
||||
test += ';'
|
||||
test += ' ' + line[1:].strip()
|
||||
else: # beginning of new test
|
||||
if test:
|
||||
tests.append(test)
|
||||
@@ -636,7 +628,6 @@ class TestCPU(object):
|
||||
# now do each test
|
||||
for test in tests:
|
||||
self.show_progress()
|
||||
log.debug('Executing test: %s' % test)
|
||||
self.execute(test, filename)
|
||||
|
||||
################################################################################
|
||||
|
||||
Reference in New Issue
Block a user