mirror of
https://github.com/rzzzwilson/pymlac.git
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Change to a class
This commit is contained in:
Ross Wilson
parent
acf9417352
commit
6abce2fa8e
445
pymlac/Memory.py
445
pymlac/Memory.py
@ -10,273 +10,254 @@ import struct
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from Globals import *
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ROM_START = 040
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ROM_SIZE = 040
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ROM_END = ROM_START + ROM_SIZE - 1
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class Memory(object):
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# this PTR bootstrap from "Loading The PDS-1" (loading.pdf)
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PTR_ROM_IMAGE = [ 0060077, # start lac base ;40 get load address
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0020010, # dac 10 ;41 put into auto-inc reg
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0104100, # lwc 0100 ;42 -0100 into AC
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0020020, # dac 20 ;43 put into memory
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0001061, # hon ;44 start PTR
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0100011, # wait cal ;45 clear AC+LINK
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0002400, # hsf ;46 skip if PTR has data
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0010046, # jmp .-1 ;47 wait until is data
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0001051, # hrb ;50 read PTR -> AC
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0074075, # sam what ;51 skip if AC == 2
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0010045, # jmp wait ;52 wait until PTR return 0
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0002400, # loop hsf ;53 skip if PTR has data
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0010053, # jmp .-1 ;54 wait until is data
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0001051, # hrb ;55 read PTR -> AC
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0003003, # ral 3 ;56 move byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0102400, # hsn ;61 wait until PTR moves
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0010061, # jmp .-1 ;62
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0002400, # hsf ;63 skip if PTR has data
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0010063, # jmp .-1 ;64 wait until is data
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0001051, # hrb ;65 read PTR -> AC
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0120010, # dac *10 ;66 store word, inc pointer
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0102400, # hsn ;67 wait until PTR moves
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0010067, # jmp .-1 ;70
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0100011, # cal ;71 clear AC & LINK
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0030020, # isz 20 ;72 inc mem and skip zero
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0010053, # jmp loop ;73 if not finished, jump
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0110076, # jmp *go ;74 execute loader
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0000002, # what data 2 ;75
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0003700, # go word 03700H;76
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0003677 # base word 03677H;77
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]
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TTY_ROM_IMAGE = [ 0060077, # start lac base ;40 get load address
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0020010, # dac 10 ;41 put into auto-inc reg
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0104076, # lwc 076 ;42 -076 into AC (loader size)
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0020020, # dac 20 ;43 put into memory
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0001032, # rcf ;44 clear TTY flag
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0100011, # wait cal ;45 clear AC+LINK
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0002040, # rsf ;46 skip if TTY has data
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0010046, # jmp .-1 ;47 wait until there is data
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0001031, # rrb ;50 read TTY -> AC
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0074075, # sam 75 ;51 first non-zero must be 02
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0010044, # jmp 044 ;52 wait until TTY return == 02
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0002040, # loop rsf ;53 skip if TTY has data
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0010053, # jmp .-1 ;54 wait until there is data
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0001033, # rrc ;55 read TTY -> AC
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0003003, # ral 3 ;56 move TTY byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0002040, # rsf ;61 wait until there is data
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0010061, # jmp .-1 ;62
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0001033, # rrc ;63 read TTY -> AC, clear flag
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0120010, # dac *10 ;64 store word, inc pointer
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0100011, # cal ;65 clear AC & LINK
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0030020, # isz 20 ;66 inc mem and skip if zero
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0010053, # jmp loop ;67 if not finished, next word
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0110076, # jmp *go ;70 else execute block loader
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0000000, # hlt ;71
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0000000, # hlt ;72
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0000000, # hlt ;73
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0000000, # hlt ;74
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0000002, # data 2 ;75
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0037700, # go word 037700 ;76 block loader base address
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0037677 # base word 037677 ;77 init value for 010 auto inc
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]
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ROM_START = 040
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ROM_SIZE = 040
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ROM_END = ROM_START + ROM_SIZE - 1
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# module-level variables
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corefile = None
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memory = []
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using_rom = True
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boot_rom = None
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# this PTR bootstrap from "Loading The PDS-1" (loading.pdf)
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PTR_ROM_IMAGE = [ 0060077, # start lac base ;40 get load address
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0020010, # dac 10 ;41 put into auto-inc reg
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0104100, # lwc 0100 ;42 -0100 into AC
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0020020, # dac 20 ;43 put into memory
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0001061, # hon ;44 start PTR
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0100011, # wait cal ;45 clear AC+LINK
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0002400, # hsf ;46 skip if PTR has data
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0010046, # jmp .-1 ;47 wait until is data
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0001051, # hrb ;50 read PTR -> AC
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0074075, # sam what ;51 skip if AC == 2
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0010045, # jmp wait ;52 wait until PTR return 0
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0002400, # loop hsf ;53 skip if PTR has data
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0010053, # jmp .-1 ;54 wait until is data
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0001051, # hrb ;55 read PTR -> AC
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0003003, # ral 3 ;56 move byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0102400, # hsn ;61 wait until PTR moves
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0010061, # jmp .-1 ;62
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0002400, # hsf ;63 skip if PTR has data
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0010063, # jmp .-1 ;64 wait until is data
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0001051, # hrb ;65 read PTR -> AC
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0120010, # dac *10 ;66 store word, inc pointer
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0102400, # hsn ;67 wait until PTR moves
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0010067, # jmp .-1 ;70
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0100011, # cal ;71 clear AC & LINK
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0030020, # isz 20 ;72 inc mem and skip zero
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0010053, # jmp loop ;73 if not finished, jump
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0110076, # jmp *go ;74 execute loader
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0000002, # what data 2 ;75
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0003700, # go word 03700H;76
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0003677 # base word 03677H;77
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]
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TTY_ROM_IMAGE = [ 0060077, # start lac base ;40 get load address
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0020010, # dac 10 ;41 put into auto-inc reg
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0104076, # lwc 076 ;42 -076 into AC (loader size)
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0020020, # dac 20 ;43 put into memory
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0001032, # rcf ;44 clear TTY flag
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0100011, # wait cal ;45 clear AC+LINK
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0002040, # rsf ;46 skip if TTY has data
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0010046, # jmp .-1 ;47 wait until there is data
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0001031, # rrb ;50 read TTY -> AC
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0074075, # sam 75 ;51 first non-zero must be 02
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0010044, # jmp 044 ;52 wait until TTY return == 02
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0002040, # loop rsf ;53 skip if TTY has data
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0010053, # jmp .-1 ;54 wait until there is data
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0001033, # rrc ;55 read TTY -> AC
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0003003, # ral 3 ;56 move TTY byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0002040, # rsf ;61 wait until there is data
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0010061, # jmp .-1 ;62
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0001033, # rrc ;63 read TTY -> AC, clear flag
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0120010, # dac *10 ;64 store word, inc pointer
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0100011, # cal ;65 clear AC & LINK
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0030020, # isz 20 ;66 inc mem and skip if zero
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0010053, # jmp loop ;67 if not finished, next word
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0110076, # jmp *go ;70 else execute block loader
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0000000, # hlt ;71
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0000000, # hlt ;72
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0000000, # hlt ;73
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0000000, # hlt ;74
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0000002, # data 2 ;75
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0037700, # go word 037700 ;76 block loader base address
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0037677 # base word 037677 ;77 init value for 010 auto inc
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]
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def init(boot=ROM_PTR, core=None):
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global corefile, boot_rom, memory
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corefile = core
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boot_rom = boot
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# class instance variables
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corefile = None
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memory = []
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using_rom = boot_rom in [ROM_PTR, ROM_TTY]
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using_rom = True
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boot_rom = None
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if corefile:
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try:
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loadcore(corefile)
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except IOError:
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clear_core()
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else:
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clear_core()
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set_ROM(boot_rom)
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def __init__(self, boot_rom=ROM_PTR, core=None):
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""" """
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self.corefile = core
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self.boot_rom = boot_rom
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self.memory = []
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self.using_rom = boot_rom in [ROM_PTR, ROM_TTY]
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if self.corefile:
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try:
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loadcore(self.corefile)
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except IOError:
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self.clear_core()
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else:
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self.clear_core()
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self.set_ROM(self.boot_rom)
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def clear_core():
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"""Clears memory to all zeros.
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def clear_core(self):
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"""Clears memory to all zeros.
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If using ROM, that is unchanged.
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"""
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If using ROM, that is unchanged.
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"""
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global memory
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for i in range(MEMORY_SIZE):
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self.memory.append(0)
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self.set_ROM(self.boot_rom)
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for i in range(MEMORY_SIZE):
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memory.append(0)
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set_ROM(boot_rom)
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def loadcore(self, filename=None):
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"""Load core from a file. Read 16 bit values as big-endian."""
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def loadcore(filename=None):
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"""Load core from a file. Read 16 bit values as big-endian."""
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if filename is None:
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filename = self.corefile
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if filename:
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self.memory = []
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try:
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with open(filename, 'rb') as fd:
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while True:
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data = fd.read(1)
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if data == '':
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break
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high = struct.unpack('B', data)[0]
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low = struct.unpack('B', fd.read(1))[0]
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val = (high << 8) + low
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self.memory.append(val)
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except struct.error:
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raise RuntimeError('Core file %s is corrupt!' % filename)
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global memory
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def savecore(self, filename=None):
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"""Save core in a file. Write 16 bit values as big-endian."""
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if filename is None:
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filename = corefile
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if filename:
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memory = []
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try:
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with open(filename, 'rb') as fd:
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while True:
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data = fd.read(1)
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if data == '':
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break
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high = struct.unpack('B', data)[0]
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low = struct.unpack('B', fd.read(1))[0]
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val = (high << 8) + low
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memory.append(val)
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except struct.error:
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raise RuntimeError('Core file %s is corrupt!' % filename)
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if filename is None:
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filename = self.corefile
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if filename:
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with open(filename, 'wb') as fd:
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for val in self.memory:
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high = val >> 8
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low = val & 0xff
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data = struct.pack('B', high)
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fd.write(data)
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data = struct.pack('B', low)
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fd.write(data)
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def savecore(filename=None):
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"""Save core in a file. Write 16 bit values as big-endian."""
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def set_PTR_ROM(self):
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"""Set addresses 040 to 077 as PTR ROM."""
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if filename is None:
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filename = corefile
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if filename:
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with open(filename, 'wb') as fd:
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for val in memory:
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high = val >> 8
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low = val & 0xff
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data = struct.pack('B', high)
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fd.write(data)
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data = struct.pack('B', low)
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fd.write(data)
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def set_PTR_ROM():
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"""Set addresses 040 to 077 as PTR ROM."""
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global memory
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i = ROM_START
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for ptr_value in PTR_ROM_IMAGE:
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memory[i] = ptr_value
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i += 1
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def set_TTY_ROM():
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"""Set addresses 040 to 077 as TTY ROM."""
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global memory
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i = ROM_START
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for tty_value in TTY_ROM_IMAGE:
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memory[i] = tty_value
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i += 1
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def set_ROM(romtype=None):
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"""Set ROM to either PTR or TTY, or disable ROM."""
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global memory, using_rom
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if romtype == 'ptr':
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using_rom = True
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i = ROM_START
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for ptr_value in PTR_ROM_IMAGE:
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memory[i] = ptr_value
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i += 1
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elif romtype == 'tty':
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using_rom = True
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i = ROM_START
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for ptr_value in TTY_ROM_IMAGE:
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memory[i] = ptr_value
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i += 1
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else:
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using_rom = False
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i = ROM_START
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for _ in PTR_ROM_IMAGE:
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memory[i] = 0
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i = self.ROM_START
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for ptr_value in self.PTR_ROM_IMAGE:
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self.memory[i] = ptr_value
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i += 1
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def fetch(address, indirect):
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"""Get a value from a memory address.
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def set_TTY_ROM(self):
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"""Set addresses 040 to 077 as TTY ROM."""
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The read can be indirect, and may be through an
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auto-increment address.
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"""
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i = self.ROM_START
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for tty_value in self.TTY_ROM_IMAGE:
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self.memory[i] = tty_value
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i += 1
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global memory
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def set_ROM(self, romtype=None):
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"""Set ROM to either PTR or TTY, or disable ROM."""
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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address = address & (MEMORY_SIZE - 1)
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if ISAUTOINC(address):
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# indirect on auto-inc register, add one to it before use
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memory[address] = MASK_MEM(memory[address] + 1)
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address = memory[address]
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indirect = bool(address & 0100000)
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if romtype == 'ptr':
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self.using_rom = True
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i = self.ROM_START
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for ptr_value in self.PTR_ROM_IMAGE:
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self.memory[i] = ptr_value
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i += 1
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elif romtype == 'tty':
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self.using_rom = True
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i = self.ROM_START
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for ptr_value in self.TTY_ROM_IMAGE:
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self.memory[i] = ptr_value
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i += 1
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else:
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self.using_rom = False
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i = self.ROM_START
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for _ in self.PTR_ROM_IMAGE:
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self.memory[i] = 0
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i += 1
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return memory[address]
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def fetch(self, address, indirect):
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"""Get a value from a memory address.
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def eff_address(address, indirect):
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"""Get an effective memory address.
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The read can be indirect, and may be through an
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auto-increment address.
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"""
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The address can be indirect, and may be through an
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auto-increment address.
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"""
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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address = address & (MEMORY_SIZE - 1)
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if ISAUTOINC(address):
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# indirect on auto-inc register, add one to it before use
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self.memory[address] = MASK_MEM(self.memory[address] + 1)
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address = self.memory[address]
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indirect = bool(address & 0100000)
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global memory
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return self.memory[address]
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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if ISAUTOINC(address):
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# indirect on auto-inc register, add one to it before use
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memory[address] = MASK_MEM(memory[address] + 1)
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address = memory[address]
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indirect = bool(address & 0100000)
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def eff_address(self, address, indirect):
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"""Get an effective memory address.
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return address
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The address can be indirect, and may be through an
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auto-increment address.
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"""
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#def str_trace(msg=None):
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# """Get a traceback string."""
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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if ISAUTOINC(address):
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# indirect on auto-inc register, add one to it before use
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self.memory[address] = MASK_MEM(self.memory[address] + 1)
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address = self.memory[address]
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indirect = bool(address & 0100000)
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return address
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# def str_trace(msg=None):
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# """Get a traceback string."""
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#
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# import traceback
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# import traceback
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#
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# result = []
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# result = []
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#
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# if msg:
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# result.append(msg+'\n')
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# if msg:
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# result.append(msg+'\n')
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#
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# result.extend(traceback.format_stack())
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# result.extend(traceback.format_stack())
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#
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# return ''.join(result)
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# return ''.join(result)
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def put(value, address, indirect):
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"""Put a value into a memory address.
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def put(self, value, address, indirect):
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"""Put a value into a memory address.
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The store can be indirect, and may be through an
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auto-increment address.
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"""
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The store can be indirect, and may be through an
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auto-increment address.
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"""
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# if address == 0 and value != 0:
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# print str_trace('Writing %07o to address 0!?' % value)
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if indirect:
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address = self.memory[address] & ADDRMASK
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global memory
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if self.using_rom and self.ROM_START <= address <= self.ROM_END:
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Trace.comment('Attempt to write to ROM')
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return
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|
||||
if indirect:
|
||||
# if ISAUTOINC(address):
|
||||
# memory[address] = MASK_MEM(memory[address] + 1)
|
||||
address = memory[address] & ADDRMASK
|
||||
|
||||
if using_rom and ROM_START <= address <= ROM_END:
|
||||
Trace.comment('Attempt to write to ROM')
|
||||
return
|
||||
|
||||
try:
|
||||
memory[address] = MASK_16(value)
|
||||
except IndexError:
|
||||
raise RuntimeError('Bad address: %06o (max mem=%06o, ADDRMASK=%06o)'
|
||||
% (address, len(memory), ADDRMASK))
|
||||
try:
|
||||
self.memory[address] = MASK_16(value)
|
||||
except IndexError:
|
||||
raise RuntimeError('Bad address: %06o (max mem=%06o, ADDRMASK=%06o)'
|
||||
% (address, len(self.memory), ADDRMASK))
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user