From 7307b89179bbce63536cfada0c8cd4c6d8f1b89d Mon Sep 17 00:00:00 2001 From: Ross Wilson Date: Thu, 11 Jun 2015 17:22:08 +0700 Subject: [PATCH] All implemented tests working --- pymlac/test_pymlac_CPU.py | 45 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/pymlac/test_pymlac_CPU.py b/pymlac/test_pymlac_CPU.py index ad482fa..85b18c3 100644 --- a/pymlac/test_pymlac_CPU.py +++ b/pymlac/test_pymlac_CPU.py @@ -11,6 +11,51 @@ Execute opcode, test result. We DON'T try to load from papertape, use core files, etc. """ +# We implement a small interpreter to test the CPU. The test code is read in +# from a file: +# +# # LAW +# setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0 +# setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LAW 0]; RUN +# checkcycles 1; checkreg pc 0101; checkreg ac 0 +# +# The instructions are delimited by ';' characters. A line beginning with a +# TAB character is a continuation of the previous. Lines with '#' in column +# 1 are comments +# +# The test instructions are: +# +# setreg +# where is one of AC, L or PC, value is any value +# (all registers are set to 0 initially) +# +# setmem +# where is an address and value is any value OR +# [] where the value is the assembled opcode +# +# run [] +# starts execution, optional is used PC := addr before +# +# checkcycles +# check number of executed cycles is +# +# checkreg +# check register (AC, L or PC) has value +# +# checkmem +# check that memory at has +# +# memset +# sets all of memory to +# a "memset 0" is assumed before each test +# +# In addition, all of memory is checked for changed values after execution +# except where an explicit "checkmem " has been performed. +# Additionally, registers that aren't explicitly checked are tested to make +# sure they didn't change. +# + + import unittest