From 9e8beacc64f594f9d04f7cfbb8b97bc173266dba Mon Sep 17 00:00:00 2001
From: Ross Wilson <rzzzwilson@gmail.com>
Date: Mon, 14 Mar 2016 18:47:18 +1000
Subject: [PATCH] Getting blockpunch.ptp to run

---
 pymlac/Memory.py   |  6 ++++++
 pymlac/TtyOut.py   | 12 ++++++++++--
 pymlac/test_CPU.py | 39 +++++++++++++++++++++++++++++++++------
 3 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/pymlac/Memory.py b/pymlac/Memory.py
index ee297d0..35fba3c 100644
--- a/pymlac/Memory.py
+++ b/pymlac/Memory.py
@@ -290,9 +290,15 @@ class Memory(object):
         auto-increment address.
         """
 
+        # limit memory to available range
+        address = address & PCMASK
+
         if indirect:
             address = self.memory[address] & ADDRMASK
 
+        # limit memory to available range
+        address = address & PCMASK
+
         if self.rom_protected and self.ROM_START <= address <= self.ROM_END:
             print('Attempt to write to ROM address %07o' % address)
             Trace.comment('Attempt to write to ROM address %07o' % address)
diff --git a/pymlac/TtyOut.py b/pymlac/TtyOut.py
index 7310931..970b2cf 100644
--- a/pymlac/TtyOut.py
+++ b/pymlac/TtyOut.py
@@ -21,6 +21,9 @@ open_file = 0
 cycle_count = 0
 state = DEVICE_NOT_READY
 
+import log
+log = log.Log('test.log', log.Log.DEBUG)
+
 
 class TtyOut(object):
 
@@ -43,19 +46,24 @@ class TtyOut(object):
         self.state = DEVICE_NOT_READY
 
     def write(self, char):
+        log('TTYOUT: writing byte %03o, .open_file=%s' % (char, self.open_file))
         if self.open_file:
-            self.open_file.write(char)
+            self.open_file.write(chr(char))
+            self.state = DEVICE_NOT_READY
             self.cycle_count = DEVICE_NOT_READY_CYCLES
+            log('TTYOUT: device -> DEVICE_NOT_READY, .cycle_count=%d' % self.cycle_count)
 
     def ready(self):
         return (self.state != DEVICE_NOT_READY)
 
     def clear(self):
-        self.state = DEVICE_NOT_READY
+        self.state = DEVICE_READY
 
     def tick(self, cycles):
         if (self.state == DEVICE_NOT_READY):
             self.cycle_count -= cycles
+            log('TTYOUT: tick: .cycle_count set to %d' % self.cycle_count)
             if self.cycle_count <= 0:
+                log('TTYOUT: tick: device set to DEVICE_READY')
                 self.state = DEVICE_READY
 
diff --git a/pymlac/test_CPU.py b/pymlac/test_CPU.py
index 5dbf5d9..e73d1a0 100755
--- a/pymlac/test_CPU.py
+++ b/pymlac/test_CPU.py
@@ -187,6 +187,8 @@ class TestCPU(object):
 #   checkfile <file1> <file2>
 #   dumpmem file begin,end
 #   cmpmem file
+#   trace <range>[:<range>:...]
+#       where <range> ::= <addr>,<addr>
 
     def setreg(self, name, value):
         """Set register to a value.
@@ -500,9 +502,6 @@ class TestCPU(object):
             if begin is None or end is None:
                 return "dumpmem: dump limits are bad: %s" % addresses
 
-        log('dumpmem: filename=%s, begin=%06o, end=%06o'
-            % (filename, begin, end))
-
         # create octdump-like text file with required memory locations
         with open(filename, 'wb') as handle:
             addr = begin
@@ -551,6 +550,34 @@ class TestCPU(object):
                             % (address, expected, actual))
                 address += 1
 
+    def trace(self, ranges, ignore):
+        """Set the trace range(s).
+
+        ranges  trace ranges of the form <range>[:<range>:...]
+                where <range> ::= <addr>,<addr>
+
+        Puts the trace range(s) into the Trace object.
+        """
+
+        log('trace: ranges=%s' % ranges)
+
+        trace_map = collections.defaultdict(bool)
+        for rng in ranges.split(':'):
+            be = rng.split(',')
+            if len(be) != 2:
+                return("Trace ranges must have the form 'begin,end'")
+            (begin, end) = be
+            begin = self.str2int(begin)
+            end = self.str2int(end)
+            if begin > end:
+                return("Trace begin address must be <= end address.  Got: %s" % rng)
+            for addr in range(begin, end+1):
+                trace_map[addr] = True
+
+        trace.set_trace_map(trace_map)
+ 
+        log('trace: trace_map=%s' % str(trace_map))
+
 # end of DSL primitives
 
     def check_all_mem(self):
@@ -639,10 +666,8 @@ class TestCPU(object):
         self.ttyout = TtyOut.TtyOut()
         self.cpu = MainCPU.MainCPU(self.memory, None, None,
                                    None, self.ttyin, self.ttyout, self.ptrptp)
-        # trace at all addresses
+        # turn yrace OFF, initially
         trace_map = collections.defaultdict(bool)
-        for addr in range(0, 03777+1):
-            trace_map[addr] = True
         trace.set_trace_map(trace_map)
 
         self.cpu.running = True
@@ -716,6 +741,8 @@ class TestCPU(object):
                 r = self.dumpmem(fld1, fld2)
             elif opcode == 'cmpmem':
                 r = self.cmpmem(fld1, fld2)
+            elif opcode == 'trace':
+                r = self.trace(fld1, fld2)
             else:
                 print("Unrecognized opcode '%s' in: %s" % (opcode, test))
                 raise Exception("Unrecognized opcode '%s' in: %s" % (opcode, test))