diff --git a/pymlac/Globals.py b/pymlac/Globals.py
index 17e3020..d3445f8 100644
--- a/pymlac/Globals.py
+++ b/pymlac/Globals.py
@@ -157,7 +157,9 @@ LOADTTY_RADIO_RECT = (SCREEN_BOOTROM_LOADTTY_RADIO_POSN, (19, 19))
 
 # 'core' size (words) and save filename
 CORE_FILENAME = 'pymlac.core'
-MEMORY_SIZE = 040000	# 16K words memory size
+#MEMORY_SIZE = 040000	# 16K words memory size
+MEMORY_SIZE = 04000	# 2K words memory size - while debugging
+                        # removes some block address bugs
 PCMASK = MEMORY_SIZE - 1
 
 # Trace stuff
@@ -171,7 +173,7 @@ ROM_PTR = 1
 ROM_TTY = 2
 ROM_NONE = 3
 
-# The 4K 'local' mask
+# The 4K 'local' mask to remove high bits
 ADDRHIGHMASK = 0x7800
 
 # word overflow and value masks
@@ -200,6 +202,6 @@ def MASK_MEM(address):
 
 # A function to decide if an address is an auto-increment address
 def ISAUTOINC(address):
-    maskaddr = address & 0x7ff
-    return (maskaddr >= 8) and (maskaddr <= 17)
+    maskaddr = address & 03777
+    return (maskaddr >= 010) and (maskaddr <= 017)
 
diff --git a/pymlac/MainCPU.py b/pymlac/MainCPU.py
index bb628c5..8f2825e 100644
--- a/pymlac/MainCPU.py
+++ b/pymlac/MainCPU.py
@@ -155,7 +155,7 @@ def init():
 
     running = False
 
-def EFFADDR(address):
+def BLOCKADDR(address):
     return BlockBase | address
 
 def execute_one_instruction():
@@ -168,13 +168,13 @@ def execute_one_instruction():
         return 0
 
     # get instruction word to execute, advance PC
-    instruction = Memory.get(PC, False)
+    instruction = Memory.fetch(PC, False)
     BlockBase = PC & ADDRHIGHMASK
     PC = MASK_MEM(PC + 1)
 
     # get instruction opcode, indirect bit and address
     opcode = (instruction >> 11) & 017
-    indirect = (instruction & 0100000)
+    indirect = bool(instruction & 0100000)
     address = (instruction & 03777)
 
     return main_decode.get(opcode, illegal)(indirect, address, instruction)
@@ -210,25 +210,22 @@ def i_LAW_LWC(indirect, address, instruction):
 def i_JMP(indirect, address, instruction):
     global PC
 
-    jmpaddr = EFFADDR(address)
-    if indirect:
-        jmpaddr = Memory.get(jmpaddr, False)
-    PC = jmpaddr & PCMASK
+    address = Memory.eff_address(address, indirect)
+    PC = address & PCMASK
     Trace.itrace('JMP', indirect, address)
     return 3 if indirect else 2
 
 def i_DAC(indirect, address, instruction):
-    address = EFFADDR(address)
-    Memory.put(AC, address, indirect)
+    address = Memory.eff_address(address, indirect)
+    Memory.put(AC, address, False)
     Trace.itrace('DAC', indirect, address)
     return 3 if indirect else 2
 
 def i_XAM(indirect, address, instruction):
     global AC
 
-    if indirect:
-        address = Memory.get(address, False)
-    tmp = Memory.get(address, False)
+    address = Memory.eff_address(address, indirect)
+    tmp = Memory.fetch(address, False)
     Memory.put(AC, address, False)
     AC = tmp
     Trace.itrace('XAM', indirect, address)
@@ -237,8 +234,9 @@ def i_XAM(indirect, address, instruction):
 def i_ISZ(indirect, address, instruction):
     global PC
 
-    value = (Memory.get(address, indirect) + 1) & WORDMASK
-    Memory.put(value, address, indirect)
+    address = Memory.eff_address(address, indirect)
+    value = (Memory.fetch(address, False) + 1) & WORDMASK
+    Memory.put(value, address, False)
     if value == 0:
         PC = (PC + 1) & WORDMASK
     Trace.itrace('ISZ', indirect, address)
@@ -247,11 +245,9 @@ def i_ISZ(indirect, address, instruction):
 def i_JMS(indirect, address, instruction):
     global PC
 
-    jmsaddr = EFFADDR(address)
-    if indirect:
-        jmsaddr = Memory.get(jmsaddr, False)
-    Memory.put(PC, jmsaddr, False)
-    PC = (jmsaddr + 1) & PCMASK
+    address = Memory.eff_address(address, indirect)
+    Memory.put(PC, address, False)
+    PC = (address + 1) & PCMASK
     Trace.itrace('JMS', indirect, address)
     return 3 if indirect else 2
 
@@ -286,8 +282,7 @@ def i_LAC(indirect, address, instruction):
 def i_ADD(indirect, address, instruction):
     global AC, L
 
-    effaddress = EFFADDR(address)
-    AC += Memory.get(address, indirect)
+    AC += Memory.fetch(BLOCKADDR(address), indirect)
     if AC & OVERFLOWMASK:
         L = not L
         AC &= WORDMASK
@@ -297,8 +292,7 @@ def i_ADD(indirect, address, instruction):
 def i_SUB(indirect, address, instruction):
     global AC, L
 
-    effaddr = EFFADDR(address)
-    AC -= Memory.get(address, indirect)
+    AC -= Memory.fetch(BLOCKADDR(address), indirect)
     if AC & OVERFLOWMASK:
         L = not L
         AC &= WORDMASK
@@ -308,7 +302,7 @@ def i_SUB(indirect, address, instruction):
 def i_SAM(indirect, address, instruction):
     global PC
 
-    samaddr = EFFADDR(address)
+    samaddr = BLOCKADDR(address)
     if indirect:
         samaddr = Memory.get(samaddr, False)
     if AC == Memory.get(samaddr, False):
diff --git a/pymlac/Memory.py b/pymlac/Memory.py
index d4ab4b4..f8e424e 100644
--- a/pymlac/Memory.py
+++ b/pymlac/Memory.py
@@ -200,7 +200,7 @@ def set_ROM(romtype=None):
             memory[i] = 0
             i += 1
 
-def get(address, indirect):
+def fetch(address, indirect):
     """Get a value from a memory address.
 
     The read can be indirect, and may be through an
@@ -209,12 +209,37 @@ def get(address, indirect):
 
     global memory
 
-    if indirect:
+    # the Imlac can get into infinite defer loops, and so can we!
+    while indirect:
+        address = address & (MEMORY_SIZE - 1)
         if ISAUTOINC(address):
+            # indirect on auto-inc register, add one to it before use
             memory[address] = MASK_MEM(memory[address] + 1)
         address = memory[address]
+        indirect = bool(address & 0100000)
+
     return memory[address]
 
+def eff_address(address, indirect):
+#def get(address, indirect):
+    """Get an effective memory address.
+
+    The address can be indirect, and may be through an
+    auto-increment address.
+    """
+
+    global memory
+
+    # the Imlac can get into infinite defer loops, and so can we!
+    while indirect:
+        if ISAUTOINC(address):
+            # indirect on auto-inc register, add one to it before use
+            memory[address] = MASK_MEM(memory[address] + 1)
+        address = memory[address]
+        indirect = bool(address & 0100000)
+
+    return address
+
 def put(value, address, indirect):
     """Put a value into a memory address.
 
diff --git a/pymlac/test_pymlac_CPU.py b/pymlac/test_pymlac_CPU.py
index 5cc0c31..ad482fa 100644
--- a/pymlac/test_pymlac_CPU.py
+++ b/pymlac/test_pymlac_CPU.py
@@ -36,12 +36,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LAW 0" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LAW 0" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"LAW 0" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"LAW 0" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"LAW 0" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LAW 0" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         Memory.memory[0100] = 004000    # LAW 0
         MainCPU.AC = 012345
@@ -52,12 +52,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LAW 0" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LAW 0" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"LAW 0" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"LAW 0" modified L to %01o, should be 0' % MainCPU.L
         self.assertTrue(MainCPU.L == 0, msg)
-        msg = '"LAW 0" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LAW 0" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         # test "LAW 0377"
         Memory.memory[0100] = 004377    # LAW 0377
@@ -70,12 +70,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LAW 0377" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LAW 0377" left AC containing %06o, should be 0377' % MainCPU.AC
+        msg = '"LAW 0377" left AC containing %07o, should be 0377' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0377, msg)
         msg = '"LAW 0377" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"LAW 0377" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LAW 0377" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         Memory.memory[0100] = 004377    # LAW 0377
         MainCPU.AC = 012345
@@ -86,12 +86,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LAW 0377" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LAW 0377" left AC containing %06o, should be 0377' % MainCPU.AC
+        msg = '"LAW 0377" left AC containing %07o, should be 0377' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0377, msg)
         msg = '"LAW 0377" modified L to %01o, should be 0' % MainCPU.L
         self.assertTrue(MainCPU.L == 0, msg)
-        msg = '"LAW 0377" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LAW 0377" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
     def test_LWC(self):
         Trace.init('test_LWC.trace')
@@ -109,12 +109,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LWC 0" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LWC 0" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"LWC 0" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"LWC 0" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"LWC 0" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LWC 0" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         Memory.memory[0100] = 0104000    # LWC 0
         MainCPU.AC = 012345
@@ -125,12 +125,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LWC 0" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LWC 0" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"LWC 0" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"LWC 0" modified L to %01o, should be 0' % MainCPU.L
         self.assertTrue(MainCPU.L == 0, msg)
-        msg = '"LWC 0" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LWC 0" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         # test "LWC 1"
         Memory.memory[0100] = 0104001    # LWC 1
@@ -143,12 +143,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LWC 1" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LWC 1" left AC containing %06o, should be 0177776' % MainCPU.AC
+        msg = '"LWC 1" left AC containing %07o, should be 0177776' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177776, msg)
         msg = '"LWC 1" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"LWC 1" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LWC 1" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         Memory.memory[0100] = 0104001    # LWC 1
         MainCPU.AC = 012345
@@ -159,20 +159,20 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"LWC 1" used %d cycles, should be 1' % cycles
         self.assertTrue(cycles == 1, msg)
-        msg = '"LWC 1" left AC containing %06o, should be 0177776' % MainCPU.AC
+        msg = '"LWC 1" left AC containing %07o, should be 0177776' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177776, msg)
         msg = '"LWC 1" modified L to %01o, should be 0' % MainCPU.L
         self.assertTrue(MainCPU.L == 0, msg)
-        msg = '"LWC 1" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"LWC 1" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
     def test_JMP(self):
         Trace.init('test_JMP.trace')
         Trace.settrace(True)
         Memory.init()
 
-        # test "JMP 0100"
-        Memory.memory[0100] = 0010100    # JMP 0100
+        # test "JMP 0200"
+        Memory.memory[0100] = 0010200    # JMP 0200
         MainCPU.init()
         MainCPU.AC = 012345
         MainCPU.L = 1
@@ -180,32 +180,32 @@ class TestPymlac(unittest.TestCase):
         MainCPU.running = True
         cycles = MainCPU.execute_one_instruction()
         Trace.itraceend(False)
-        msg = '"JMP 0100" used %d cycles, should be 2' % cycles
+        msg = '"JMP 0200" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"JMP 0100" left AC containing %06o, should be 012345' % MainCPU.AC
+        msg = '"JMP 0200" left AC containing %07o, should be 012345' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 012345, msg)
-        msg = '"JMP 0100" modified L to %01o, should be 1' % MainCPU.L
+        msg = '"JMP 0200" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"JMP 0100" modified PC to %06o, should be 0100' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0100, msg)
+        msg = '"JMP 0200" modified PC to %07o, should be 0200' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0200, msg)
 
         # test "JMP 0110"
         Memory.memory[0100] = 0010110    # JMP 0110
         MainCPU.init()
         MainCPU.AC = 012345
-        MainCPU.L = 1
+        MainCPU.L = 0
         MainCPU.PC = 0100
         MainCPU.running = True
         cycles = MainCPU.execute_one_instruction()
         Trace.itraceend(False)
         msg = '"JMP 0110" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"JMP 0110" left AC containing %06o, should be 012345' % MainCPU.AC
+        msg = '"JMP 0110" left AC containing %07o, should be 012345' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 012345, msg)
-        msg = '"JMP 0110" modified L to %01o, should be 1' % MainCPU.L
-        self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"JMP 0110" modified PC to %06o, should be 0110' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0110, msg)
+        msg = '"JMP 0110" modified L to %01o, should be 0' % MainCPU.L
+        self.assertTrue(MainCPU.L == 0, msg)
+        msg = '"JMP 0110" modified PC to %07o, should be 0110' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0110, msg)
 
         # test "JMP *0110"
         Memory.memory[0100] = 0110110    # JMP *0110
@@ -219,12 +219,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"JMP *0110" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"JMP *0110" left AC containing %06o, should be 012345' % MainCPU.AC
+        msg = '"JMP *0110" left AC containing %07o, should be 012345' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 012345, msg)
         msg = '"JMP *0110" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"JMP *0110" modified PC to %06o, should be 0120' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0120, msg)
+        msg = '"JMP *0110" modified PC to %07o, should be 0120' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0120, msg)
 
     def test_DAC(self):
         Trace.init('test_DAC.trace')
@@ -243,14 +243,14 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"DAC 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"DAC 0101" left AC containing %06o, should be 1' % MainCPU.AC
+        msg = '"DAC 0101" left AC containing %07o, should be 1' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 1, msg)
         msg = '"DAC 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"DAC 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"DAC 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
+        msg = '"DAC 0101" modified memory[0101] to %07o, should be 1' % Memory.memory[0101]
         self.assertTrue(Memory.memory[0101] == 1, msg)
+        msg = '"DAC 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         # test "DAC *0101"
         Memory.memory[0100] = 0120101    # DAC *0101
@@ -265,14 +265,39 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"DAC *0101" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"DAC *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"DAC *0101" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"DAC *0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"DAC *0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"DAC *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
+        msg = '"DAC *0101" modified memory[0102] to %07o, should be 0177777' % Memory.memory[0102]
         self.assertTrue(Memory.memory[0102] == 0177777, msg)
+        msg = '"DAC *0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+
+        # test "DAC *010"
+        Memory.memory[0100] = 0120010    # DAC *010
+        Memory.memory[010] = 0102        # address of cell we are storing into
+        Memory.memory[0102] = 0
+        Memory.memory[0103] = 0
+        MainCPU.init()
+        MainCPU.AC = 0177777
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"DAC *010" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"DAC *010" left AC containing %07o, should be 0177777' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0177777, msg)
+        msg = '"DAC *010" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"DAC *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
+        self.assertTrue(Memory.memory[0102] == 0, msg)
+        msg = '"DAC *010" modified memory[0103] to %07o, should be 0177777' % Memory.memory[0103]
+        self.assertTrue(Memory.memory[0103] == 0177777, msg)
+        msg = '"DAC *010" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
     def test_XAM(self):
         Trace.init('test_XAM.trace')
@@ -291,13 +316,13 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"XAM 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"XAM 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"XAM 0101" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"XAM 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"XAM 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"XAM 0101" modified memory[0101] to %06o, should be 2' % Memory.memory[0101]
+        msg = '"XAM 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"XAM 0101" modified memory[0101] to %07o, should be 2' % Memory.memory[0101]
         self.assertTrue(Memory.memory[0101] == 2, msg)
 
         # test "XAM *0101"
@@ -313,13 +338,13 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"XAM *0101" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"XAM *0101" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"XAM *0101" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"XAM *0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"XAM *0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"XAM *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
+        msg = '"XAM *0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"XAM *0101" modified memory[0102] to %07o, should be 0177777' % Memory.memory[0102]
         self.assertTrue(Memory.memory[0102] == 0177777, msg)
 
     def test_ISZ(self):
@@ -332,8 +357,6 @@ class TestPymlac(unittest.TestCase):
         Memory.memory[0101] = 0          # value we are incrementing/testing
         MainCPU.init()
         MainCPU.AC = 2
-        msg = 'Before, AC contains %06o, should be 2' % MainCPU.AC
-        self.assertTrue(MainCPU.AC == 2, msg)
         MainCPU.L = 1
         MainCPU.PC = 0100
         MainCPU.running = True
@@ -341,13 +364,13 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ISZ 0101" left AC containing %06o, should be 2' % MainCPU.AC
+        msg = '"ISZ 0101" left AC containing %07o, should be 2' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 2, msg)
         msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"ISZ 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
+        msg = '"ISZ 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"ISZ 0101" modified memory[0101] to %07o, should be 1' % Memory.memory[0101]
         self.assertTrue(Memory.memory[0101] == 1, msg)
 
         # test "ISZ *0101"
@@ -363,13 +386,13 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ *0101" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"ISZ *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"ISZ *0101" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"ISZ *0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ *0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"ISZ *0101" modified memory[0102] to %06o, should be 1' % Memory.memory[0102]
+        msg = '"ISZ *0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"ISZ *0101" modified memory[0102] to %07o, should be 1' % Memory.memory[0102]
         self.assertTrue(Memory.memory[0102] == 1, msg)
 
         # test "ISZ 0101"
@@ -384,36 +407,36 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ISZ 0101" left AC containing %06o, should be 2' % MainCPU.AC
+        msg = '"ISZ 0101" left AC containing %07o, should be 2' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 2, msg)
         msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ 0101" modified PC to %06o, should be 0102' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0102, msg)
-        msg = '"ISZ 0101" modified memory[0101] to %06o, should be 0' % Memory.memory[0101]
+        msg = '"ISZ 0101" modified PC to %07o, should be 0102' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0102, msg)
+        msg = '"ISZ 0101" modified memory[0101] to %07o, should be 0' % Memory.memory[0101]
         self.assertTrue(Memory.memory[0101] == 0, msg)
 
-        # test "ISZ *0101"
-        Memory.memory[0100] = 0130101    # ISZ *0101
-        Memory.memory[0101] = 0102       # address of cell we are storing into
-        Memory.memory[0102] = 0177777
+        # test "ISZ *0200"
+        Memory.memory[0100] = 0130200    # ISZ *0200
+        Memory.memory[0200] = 0201       # address of cell we are storing into
+        Memory.memory[0201] = 0177777
         MainCPU.init()
-        MainCPU.AC = 0177777
+        MainCPU.AC = 0177776
         MainCPU.L = 1
         MainCPU.PC = 0100
         MainCPU.running = True
         cycles = MainCPU.execute_one_instruction()
         Trace.itraceend(False)
-        msg = '"ISZ *0101" used %d cycles, should be 3' % cycles
+        msg = '"ISZ *0200" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"ISZ *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
-        self.assertTrue(MainCPU.AC == 0177777, msg)
-        msg = '"ISZ *0101" modified L to %01o, should be 1' % MainCPU.L
+        msg = '"ISZ *0200" left AC containing %07o, should be 0177776' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0177776, msg)
+        msg = '"ISZ *0200" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ *0101" modified PC to %06o, should be 0102' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0102, msg)
-        msg = '"ISZ *0101" modified memory[0102] to %06o, should be 0' % Memory.memory[0102]
-        self.assertTrue(Memory.memory[0102] == 0, msg)
+        msg = '"ISZ *0200" modified memory[0201] to %07o, should be 0' % Memory.memory[0201]
+        self.assertTrue(Memory.memory[0201] == 0, msg)
+        msg = '"ISZ *0200" modified PC to %07o, should be 0102' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0102, msg)
 
         # test "ISZ 010"        check auto-increment locations
         Memory.memory[0100] = 0030010    # ISZ 010
@@ -427,13 +450,13 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ 010" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ISZ 010" left AC containing %06o, should be 2' % MainCPU.AC
+        msg = '"ISZ 010" left AC containing %07o, should be 2' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 2, msg)
         msg = '"ISZ 010" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ 010" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"ISZ 010" modified memory[010] to %06o, should be 1' % Memory.memory[010]
+        msg = '"ISZ 010" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"ISZ 010" modified memory[010] to %07o, should be 1' % Memory.memory[010]
         self.assertTrue(Memory.memory[010] == 1, msg)
 
         # test "ISZ *010"    no skip
@@ -450,17 +473,17 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ *010" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"ISZ *010" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"ISZ *010" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"ISZ *010" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ *010" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
-        msg = '"ISZ *010" modified memory[010] to %06o, should be 0103' % Memory.memory[010]
+        msg = '"ISZ *010" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
+        msg = '"ISZ *010" modified memory[010] to %07o, should be 0103' % Memory.memory[010]
         self.assertTrue(Memory.memory[010] == 0103, msg)
-        msg = '"ISZ *010" modified memory[0102] to %06o, should be 0' % Memory.memory[0102]
+        msg = '"ISZ *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
         self.assertTrue(Memory.memory[0102] == 0, msg)
-        msg = '"ISZ *010" modified memory[0103] to %06o, should be 2' % Memory.memory[0103]
+        msg = '"ISZ *010" modified memory[0103] to %07o, should be 2' % Memory.memory[0103]
         self.assertTrue(Memory.memory[0103] == 2, msg)
 
         # test "ISZ *010"    should skip
@@ -477,19 +500,91 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ISZ *010" used %d cycles, should be 3' % cycles
         self.assertTrue(cycles == 3, msg)
-        msg = '"ISZ *010" left AC containing %06o, should be 0177777' % MainCPU.AC
+        msg = '"ISZ *010" left AC containing %07o, should be 0177777' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0177777, msg)
         msg = '"ISZ *010" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ISZ *010" modified PC to %06o, should be 0102' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0102, msg)
-        msg = '"ISZ *010" modified memory[010] to %06o, should be 0103' % Memory.memory[010]
+        msg = '"ISZ *010" modified PC to %07o, should be 0102' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0102, msg)
+        msg = '"ISZ *010" modified memory[010] to %07o, should be 0103' % Memory.memory[010]
         self.assertTrue(Memory.memory[010] == 0103, msg)
-        msg = '"ISZ *010" modified memory[0102] to %06o, should be 0' % Memory.memory[0102]
+        msg = '"ISZ *010" modified memory[0102] to %07o, should be 0' % Memory.memory[0102]
         self.assertTrue(Memory.memory[0102] == 0, msg)
-        msg = '"ISZ *010" modified memory[0103] to %06o, should be 0' % Memory.memory[0103]
+        msg = '"ISZ *010" modified memory[0103] to %07o, should be 0' % Memory.memory[0103]
         self.assertTrue(Memory.memory[0103] == 0, msg)
 
+    def test_JMS(self):
+        Trace.init('test_JMS.trace')
+        Trace.settrace(True)
+        Memory.init()
+
+        # test "JMS 0101"
+        Memory.memory[0100] = 0034101    # JMS 0101
+        Memory.memory[0101] = 0          # location we are storing PC into
+        MainCPU.init()
+        MainCPU.AC = 2
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"JMS 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"JMS 0101" left AC containing %07o, should be 2' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 2, msg)
+        msg = '"JMS 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"JMS 0101" modified PC to %07o, should be 0102' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0102, msg)
+        msg = '"JMS 0101" modified memory[0101] to %07o, should be 0101' % Memory.memory[0101]
+        self.assertTrue(Memory.memory[0101] == 0101, msg)
+
+        # test "JMS *0101"
+        Memory.memory[0100] = 0134101    # JMS *0101
+        Memory.memory[0101] = 0200
+        Memory.memory[0200] = 1          # location we are storing PC into
+        MainCPU.init()
+        MainCPU.AC = 2
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"JMS *0101" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"JMS *0101" left AC containing %07o, should be 2' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 2, msg)
+        msg = '"JMS *0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"JMS *0101" modified memory[0200] to %07o, should be 0101' % Memory.memory[0200]
+        self.assertTrue(Memory.memory[0200] == 0101, msg)
+        msg = '"JMS *0101" modified PC to %07o, should be 0201' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0201, msg)
+
+        # test "JMS *010
+        Memory.memory[0100] = 0134010    # JMS *010
+        Memory.memory[010] = 0200
+        Memory.memory[0201] = 0          # location we are storing PC into
+        MainCPU.init()
+        MainCPU.AC = 2
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"JMS *010" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"JMS *010" left AC containing %07o, should be 2' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 2, msg)
+        msg = '"JMS *010" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"JMS *010" modified PC to %07o, should be 0202' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0202, msg)
+        msg = '"JMS *010" modified memory[010] to %07o, should be 0201' % Memory.memory[010]
+        self.assertTrue(Memory.memory[010] == 0201, msg)
+        msg = '"JMS *010" modified memory[0201] to %07o, should be 0101' % Memory.memory[0201]
+        self.assertTrue(Memory.memory[0201] == 0101, msg)
+
     def test_ADD(self):
         Trace.init('test_ADD.trace')
         Trace.settrace(True)
@@ -507,12 +602,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ADD 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"ADD 0101" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         # test "ADD 0101"       add 1 to 0
         Memory.memory[0100] = 0064101    # ADD 0101
@@ -526,12 +621,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ADD 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ADD 0101" left AC containing %06o, should be 1' % MainCPU.AC
+        msg = '"ADD 0101" left AC containing %07o, should be 1' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 1, msg)
         msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
         self.assertTrue(MainCPU.L == 1, msg)
-        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
         # test "ADD 0101"       add 1 to 0177777, L=1 before
         Memory.memory[0100] = 0064101    # ADD 0101
@@ -545,12 +640,12 @@ class TestPymlac(unittest.TestCase):
         Trace.itraceend(False)
         msg = '"ADD 0101" used %d cycles, should be 2' % cycles
         self.assertTrue(cycles == 2, msg)
-        msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        msg = '"ADD 0101" left AC containing %07o, should be 0' % MainCPU.AC
         self.assertTrue(MainCPU.AC == 0, msg)
         msg = '"ADD 0101" modified L to %01o, should be 0' % MainCPU.L
         self.assertTrue(MainCPU.L == 0, msg)
-        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
-        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"ADD 0101" modified PC to %07o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC == 0101, msg)
 
 
 
@@ -558,6 +653,7 @@ class TestPymlac(unittest.TestCase):
 
 if __name__ == '__main__':
     suite = unittest.makeSuite(TestPymlac, 'test')
+    #suite = unittest.makeSuite(TestPymlac, 'test_JMS')
     runner = unittest.TextTestRunner()
     runner.run(suite)