mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Finished tests upto conditional skip instructions
This commit is contained in:
Ross Wilson
145
pymlac/CPU.test
145
pymlac/CPU.test
@@ -123,9 +123,9 @@ setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 0; RUN 0100; checkcycles 2; che
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setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 2
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setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 1; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 1; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 0
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setreg ac 2; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 1
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setreg ac 2; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 1
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setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 0
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setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177775; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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@@ -153,37 +153,31 @@ setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 01
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# SUB
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
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setreg ac 1; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 2; checkreg l 1
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setreg ac 1; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 2; checkreg l 0
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setreg ac 2; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 3; checkreg l 1
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setreg ac 2; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 3; checkreg l 0
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setreg ac 2; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 02; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
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setreg ac 1; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkreg l 1
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setreg ac 1; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkreg l 0
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setreg ac 2; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 3; checkreg l 1
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setreg ac 2; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 3; checkreg l 0
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setreg ac 2; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 02; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
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setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
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setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
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setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
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setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
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setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1; checkmem 010 0121
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setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
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setreg ac 1; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkreg l 1; checkmem 010 0121
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setreg ac 1; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkreg l 0; checkmem 010 0121
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setreg ac 2; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 3; checkreg l 1; checkmem 010 0121
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setreg ac 2; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 3; checkreg l 0; checkmem 010 0121
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setreg ac 2; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 02; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1; checkmem 010 0121
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setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
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# SAM
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setreg ac 1; setmem 0100 [SAM 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101
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@@ -205,7 +199,7 @@ setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776;
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setmem 0100 [HLT]; RUN 0100; checkcycles 1; checkrun false; checkreg pc 0101
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# NOP
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setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkreg pc 0101
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setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkrun true; checkreg pc 0101
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# CLA
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setreg ac 0; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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@@ -225,12 +219,16 @@ setreg ac 0177777; setmem 0100 [STA]; RUN 0100; checkcycles 1; checkreg pc 0101;
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setreg ac 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
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setreg ac 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2
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# bug in microcode, MainCPU.py, line 333
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#setreg ac 0177777; setreg l 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
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#setreg ac 0177777; setreg l 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
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setreg ac 0177777; setreg l 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 0177777; setreg l 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
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# CIA
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setreg ac 0; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 0; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 0
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setreg ac 1; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
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setreg ac 0177777; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
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setreg ac 0177777; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 1
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# CLL
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setreg l 0; setmem 0100 [CLL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
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@@ -248,3 +246,94 @@ setreg ac 0; setreg l 0; setmem 0100 [CAL]; RUN 0100; checkcycles 1; checkreg pc
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setreg l 0; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
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setreg l 1; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
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# ODA
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setreg ds 0; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ds 0177777; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ds 0; setreg ac 0177777; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ds 0777; setreg ac 0177070; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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# LDA
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setreg ds 0; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ds 0; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ds 1; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
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setreg ds 0177000; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177000
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setreg ds 0177777; setreg ac 1; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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# SAL
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setreg ac 0; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0177777; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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setreg ac 0100001; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100002
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setreg ac 0; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
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setreg ac 0177777; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
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setreg ac 0100001; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100004
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setreg ac 0; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
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setreg ac 0177777; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
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setreg ac 0100001; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100010
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# SAR
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setreg ac 0; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0177777; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 1; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 3; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
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setreg ac 0100001; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0140000
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setreg ac 0; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0177777; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 03; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 07; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
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setreg ac 0100001; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0160000
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setreg ac 0; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0177777; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 0177777; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 07; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 017; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
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setreg ac 0100001; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0170000
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# RAL
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setreg ac 0; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
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setreg ac 0177777; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776; checkreg l 1
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setreg ac 0; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
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setreg ac 0177777; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177775; checkreg l 1
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setreg ac 0; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 010; checkreg l 0
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setreg ac 0177777; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177773; checkreg l 1
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# RAR
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setreg ac 0; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
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setreg ac 0177777; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0077777; checkreg l 1
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setreg ac 0; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 0; setreg l 1; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
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setreg ac 1; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0137777; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0020000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0157777; checkreg l 1
|
||||
|
||||
# DON
|
||||
|
||||
|
||||
@@ -284,18 +284,20 @@ def i_ADD(indirect, address, instruction):
|
||||
|
||||
AC += Memory.fetch(BLOCKADDR(address), indirect)
|
||||
if AC & OVERFLOWMASK:
|
||||
L = not L
|
||||
AC &= WORDMASK
|
||||
L = (~L) & 01
|
||||
AC &= WORDMASK
|
||||
Trace.itrace('ADD', indirect, address)
|
||||
return 3 if indirect else 2
|
||||
|
||||
def i_SUB(indirect, address, instruction):
|
||||
global AC, L
|
||||
|
||||
AC -= Memory.fetch(BLOCKADDR(address), indirect)
|
||||
addit = Memory.fetch(BLOCKADDR(address), indirect)
|
||||
addit = (~addit + 1) & WORDMASK
|
||||
AC += addit
|
||||
if AC & OVERFLOWMASK:
|
||||
L = not L
|
||||
AC &= WORDMASK
|
||||
AC &= WORDMASK
|
||||
Trace.itrace('SUB', indirect, address)
|
||||
return 3 if indirect else 2
|
||||
|
||||
@@ -304,38 +306,34 @@ def i_SAM(indirect, address, instruction):
|
||||
|
||||
samaddr = BLOCKADDR(address)
|
||||
|
||||
# if indirect:
|
||||
# samaddr = Memory.fetch(samaddr, False)
|
||||
|
||||
if AC == Memory.fetch(samaddr, indirect):
|
||||
PC = (PC + 1) & PCMASK
|
||||
Trace.itrace('SAM', indirect, address)
|
||||
return 3 if indirect else 2
|
||||
|
||||
def microcode(instruction):
|
||||
global AC, L, PC, running
|
||||
global AC, L, PC, DS, running
|
||||
|
||||
# T1
|
||||
if (instruction & 001):
|
||||
if instruction & 001:
|
||||
AC = 0
|
||||
if (instruction & 010):
|
||||
if instruction & 010:
|
||||
L = 0
|
||||
|
||||
# T2
|
||||
if (instruction & 002):
|
||||
if instruction & 002:
|
||||
AC = (~AC) & WORDMASK
|
||||
if (instruction & 020):
|
||||
if instruction & 020:
|
||||
L = (~L) & 01
|
||||
|
||||
# T3
|
||||
if (instruction & 004):
|
||||
newac = AC + 1
|
||||
# if newac & OVERFLOWMASK:
|
||||
# L = (~L) & 01
|
||||
AC = newac & WORDMASK
|
||||
if (instruction & 040):
|
||||
if instruction & 004:
|
||||
AC += 1
|
||||
if AC & OVERFLOWMASK:
|
||||
L = (~L) & 1
|
||||
AC &= WORDMASK
|
||||
if instruction & 040:
|
||||
AC |= DS
|
||||
L = (~L) & 1
|
||||
|
||||
# do some sort of trace
|
||||
combine = []
|
||||
|
||||
@@ -25,7 +25,7 @@ where <filename> is a file of test instructions and
|
||||
#
|
||||
# The test instructions are:
|
||||
# setreg <name> <value>
|
||||
# where <name> is one of AC, L or PC, value is any value
|
||||
# where <name> is one of AC, L, PC or DS, value is any value
|
||||
# (all registers are set to 0 initially)
|
||||
#
|
||||
# setmem <addr> <value>
|
||||
@@ -39,7 +39,7 @@ where <filename> is a file of test instructions and
|
||||
# check number of executed cycles is <number>
|
||||
#
|
||||
# checkreg <name> <value>
|
||||
# check register (AC, L or PC) has value <value>
|
||||
# check register (AC, L, PC or DS) has value <value>
|
||||
#
|
||||
# checkmem <addr> <value>
|
||||
# check that memory at <addr> has <value>
|
||||
@@ -102,7 +102,7 @@ def assemble(addr, opcode):
|
||||
# now assemble file
|
||||
os.system('../iasm/iasm -l %s.lst %s.asm' % (AsmFilename, AsmFilename))
|
||||
|
||||
# read the listing file to get assembled opcode
|
||||
# read the listing file to get assembled opcode (second line)
|
||||
with open(AsmFilename+'.lst', 'rb') as fd:
|
||||
lines = fd.readlines()
|
||||
line = lines[1]
|
||||
@@ -117,22 +117,20 @@ def setreg(name, value):
|
||||
Remember value to check later.
|
||||
"""
|
||||
|
||||
log.debug('setreg: name=%s, value=%s' % (name, oct(value)))
|
||||
|
||||
global RegValues
|
||||
|
||||
RegValues[name] = value
|
||||
log.debug('setreg: After, RegValues=%s' % str(RegValues))
|
||||
|
||||
if name == 'ac':
|
||||
MainCPU.AC = value
|
||||
log.debug('setreg: After, AC=%s' % oct(MainCPU.AC))
|
||||
elif name == 'l':
|
||||
MainCPU.L = value & 1
|
||||
log.debug('setreg: After, L=%s' % oct(MainCPU.L))
|
||||
elif name == 'pc':
|
||||
MainCPU.PC = value
|
||||
log.debug('setreg: After, PC=%s' % oct(MainCPU.PC))
|
||||
elif name == 'ds':
|
||||
MainCPU.DS = value
|
||||
else:
|
||||
raise Exception('setreg: bad register name: %s' % name)
|
||||
|
||||
def setmem(addr, value):
|
||||
"""Set memory location to a value."""
|
||||
@@ -182,59 +180,88 @@ def allreg(value):
|
||||
MainCPU.AC = value
|
||||
MainCPU.L = value & 1
|
||||
MainCPU.PC = value
|
||||
MainCPU.DS = value
|
||||
|
||||
def check_all_mem():
|
||||
"""Check memory for unwanted changes."""
|
||||
|
||||
result = []
|
||||
|
||||
for mem in range(MEMORY_SIZE):
|
||||
if mem in MemValues:
|
||||
continue
|
||||
value = Memory.fetch(mem, False)
|
||||
if value != MemAllValue:
|
||||
return ('Changed memory at address %07o, is %07o, should be %07o'
|
||||
% (mem, value, MemAllValue))
|
||||
if mem in MemValues:
|
||||
if value != MemValues[mem]:
|
||||
result.append('Memory at %07o changed, is %07o, should be %07o'
|
||||
% (mem, value, MemValues[mem]))
|
||||
else:
|
||||
if value != MemAllValue:
|
||||
result.append('Memory at %07o changed, is %07o, should be %07o'
|
||||
% (mem, value, MemAllValue))
|
||||
|
||||
def check_all_regs():
|
||||
"""Check registers for unwanted changes."""
|
||||
|
||||
result = []
|
||||
|
||||
if 'ac' not in RegValues:
|
||||
if 'ac' in RegValues:
|
||||
if MainCPU.AC != RegValues['ac']:
|
||||
result.append('AC changed, is %07o, should be %07o'
|
||||
% (MainCPU.AC, RegValues['ac']))
|
||||
else:
|
||||
if MainCPU.AC != RegAllValue:
|
||||
result.append('AC changed, is %07o, should be %07o'
|
||||
% (MainCPU.AC, RegAllValue))
|
||||
|
||||
if 'l' not in RegValues:
|
||||
if 'l' in RegValues:
|
||||
if MainCPU.L != RegValues['l']:
|
||||
result.append('L changed, is %02o, should be %02o'
|
||||
% (MainCPU.L, RegValues['l']))
|
||||
else:
|
||||
if MainCPU.L != RegAllValue & 1:
|
||||
result.append('L changed, is %02o, should be %02o'
|
||||
% (MainCPU.L, RegAllValue & 1))
|
||||
|
||||
if 'pc' not in RegValues:
|
||||
if 'pc' in RegValues:
|
||||
if MainCPU.PC != RegValues['pc']:
|
||||
result.append('PC changed, is %07o, should be %07o'
|
||||
% (MainCPU.PC, RegValues['pc']))
|
||||
else:
|
||||
if MainCPU.PC != RegAllValue:
|
||||
result.append('PC changed, is %07o, should be %07o'
|
||||
% (MainCPU.PC, RegAllValue))
|
||||
|
||||
if 'ds' in RegValues:
|
||||
if MainCPU.DS != RegValues['ds']:
|
||||
result.append('DS changed, is %07o, should be %07o'
|
||||
% (MainCPU.DS, RegValues['ds']))
|
||||
else:
|
||||
if MainCPU.DS != RegAllValue:
|
||||
result.append('DS changed, is %07o, should be %07o'
|
||||
% (MainCPU.DS, RegAllValue))
|
||||
|
||||
return result
|
||||
# if result:
|
||||
# return result.join('\n')
|
||||
|
||||
def checkreg(reg, value):
|
||||
"""Check register is as it should be."""
|
||||
|
||||
global RegValues
|
||||
|
||||
RegValues[reg] = value
|
||||
log.debug('checkreg: After, RegValues=%s' % str(RegValues))
|
||||
|
||||
if reg == 'ac':
|
||||
RegValues[reg] = MainCPU.AC
|
||||
if MainCPU.AC != value:
|
||||
return 'AC wrong, is %07o, should be %07o' % (MainCPU.AC, value)
|
||||
elif reg == 'l':
|
||||
RegValues[reg] = MainCPU.L
|
||||
if MainCPU.L != value:
|
||||
return 'L wrong, is %07o, should be %07o' % (MainCPU.L, value)
|
||||
return 'L wrong, is %02o, should be %02o' % (MainCPU.L, value)
|
||||
elif reg == 'pc':
|
||||
RegValues[reg] = MainCPU.PC
|
||||
if MainCPU.PC != value:
|
||||
return 'PC wrong, is %07o, should be %07o' % (MainCPU.PC, value)
|
||||
elif reg == 'ds':
|
||||
RegValues[reg] = MainCPU.DS
|
||||
if MainCPU.DS != value:
|
||||
return 'DS wrong, is %07o, should be %07o' % (MainCPU.DS, value)
|
||||
else:
|
||||
raise Exception('checkreg: bad register name: %s' % name)
|
||||
|
||||
@@ -328,12 +355,14 @@ def execute(test):
|
||||
var1 = int(var1, base=8)
|
||||
else:
|
||||
var1 = int(var1)
|
||||
var1 &= 0177777
|
||||
|
||||
if var2 and var2[0] in '0123456789':
|
||||
if var2[0] == '0':
|
||||
var2 = int(var2, base=8)
|
||||
else:
|
||||
var2 = int(var2)
|
||||
var2 &= 0177777
|
||||
|
||||
if op == 'setreg':
|
||||
r = setreg(var1, var2)
|
||||
|
||||
Reference in New Issue
Block a user