mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Changing DSL language
This commit is contained in:
Ross Wilson
parent
4d90fb7ab6
commit
add0b13a4d
@ -197,10 +197,10 @@ setreg ac 0177777; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776;
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setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102; checkmem 010 0121
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# HLT
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setmem 0100 [HLT]; setreg pc 0100; RUN; checkcycles 1; checkrun off; checkreg pc 0101
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setmem 0100 [HLT]; setreg pc 0100; RUN; checkcycles 1; checkcpu off; checkreg pc 0101
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# NOP
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setmem 0100 [NOP]; setreg pc 0100; RUN; checkcycles 1; checkrun on; checkreg pc 0101
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setmem 0100 [NOP]; setreg pc 0100; RUN; checkcycles 1; checkcpu on; checkreg pc 0101
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# CLA
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setreg ac 0; setmem 0100 [CLA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
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@ -400,3 +400,6 @@ setreg l 1; setmem 0100 [LSN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0
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# PSF
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# PPC
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# and lots of IOT instructions
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# check multiple instructions
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setmem 0100 [LAW 1|HLT]; setreg pc 0100; RUNUNTIL 0102; checkcycles 2; checkreg pc 0102; checkreg ac 1
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@ -159,13 +159,10 @@ class Memory(object):
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def set_PTR_ROM(self):
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"""Set addresses 040 to 077 as PTR ROM."""
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save_flag = self.rom_protected
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self.rom_protected = False
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i = self.ROM_START
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for ptr_value in self.PTR_ROM_IMAGE:
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self.memory[i] = ptr_value
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i += 1
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self.rom_protected = save_flag
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def set_TTY_ROM(self):
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"""Set addresses 040 to 077 as TTY ROM."""
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@ -39,6 +39,23 @@ class TestCPU(object):
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pass
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def list2int(self, values):
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"""Convert a string of multiple values to a list of ints.
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values a string like: '123;4;-2'
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(could be just '5')
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Returns a list of integers, for example: [123, 4, -2]
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"""
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values = values.split(';')
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result = []
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for value in values:
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result.append(self.str2int(value))
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return result
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def str2int(self, string):
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"""Convert string to numeric value.
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@ -47,10 +64,13 @@ class TestCPU(object):
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Returns the numeric value.
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"""
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if string[0] == '0':
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value = int(string, base=8)
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else:
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value = int(string)
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try:
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if string[0] == '0':
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value = int(string, base=8)
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else:
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value = int(string)
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except:
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return None
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return value
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@ -64,7 +84,7 @@ class TestCPU(object):
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"""
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# split possible multiple instructions
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opcodes = opcodes.split(';')
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opcodes = opcodes.split('|')
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# create ASM file with instruction
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with open(self.AsmFilename+'.asm', 'wb') as fd:
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@ -99,11 +119,8 @@ class TestCPU(object):
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# allmem <value>
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# bootrom <type>
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# romwrite <bool>
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# mount <device> <filename>
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# dismount <device>
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# run [<number>]
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# rununtil <address>
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# checklast <device> <value>
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# checkcycles <number>
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# checkreg <name> <value>
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# checkmem <addr> <value>
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@ -131,24 +148,21 @@ class TestCPU(object):
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else:
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raise Exception('setreg: bad register name: %s' % name)
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def setmem(self, addr, fld2):
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def setmem(self, addr, values):
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"""Set memory location to a value.
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addr address of memory location to set
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fld2 value to store at 'addr'
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addr address of memory location to set
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values value to store at 'addr'
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"""
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log.debug('setmem: addr=%s, fld2=%s' % (addr, fld2))
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addr = self.str2int(addr)
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# check if we must assemble var2
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if fld2[0] == '[':
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# check if we must assemble values
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if values[0] == '[':
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# assemble one or more instructions
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values = self.assemble(addr, fld2[1:-1])
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log.debug('setmem: assembled opcodes=%s' % str(fld2))
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values = self.assemble(addr, values[1:-1])
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else:
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values = [self.str2int(fld2)]
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values = self.list2int(values)
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for v in values:
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self.mem_values[addr] = v
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@ -158,12 +172,16 @@ class TestCPU(object):
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def allreg(self, value, ignore):
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"""Set all registers to a value."""
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self.reg_all_value = value
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new_value = self.str2int(value)
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if new_value is None:
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return 'allreg: bad value: %s' % str(value)
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self.cpu.AC = value
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self.cpu.L = value & 1
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self.cpu.PC = value
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self.cpu.DS = value
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self.reg_all_value = new_value
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self.cpu.AC = new_value
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self.cpu.L = new_value & 1
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self.cpu.PC = new_value
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self.cpu.DS = new_value
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def allmem(self, value, ignore):
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"""Set all of memory to a value.
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@ -171,24 +189,29 @@ class TestCPU(object):
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Remember value to check later.
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"""
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log.debug('allmem: setting memory to %07o' % value)
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new_value = self.str2int(value)
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if new_value is None:
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return 'allmem: bad value: %s' % str(value)
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self.mem_all_value = value
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self.mem_all_value = new_value
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for mem in range(MEMORY_SIZE):
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self.memory.put(value, mem, False)
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self.memory.put(new_value, mem, False)
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def bootrom(loader_type, ignore):
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pass
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"""Set bootloader memory range to appropriate bootloader code.
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loader_type either 'ptr' or 'tty'
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"""
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if loader_type not in ['ptr', 'tty']:
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return 'bootrom: invalid bootloader type: %s' % loader_type
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self.memory.set_ROM(loader_type)
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def romwrite(writable, ignore):
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pass
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"""Set ROM to be writable or not."""
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def mount(device, filename):
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pass
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def dismount(device, ignore):
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pass
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self.memory.rom_protected = writable
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def run(self, num_instructions, ignore):
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"""Execute one or more instructions.
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@ -204,17 +227,23 @@ class TestCPU(object):
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if number is None:
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return 'Invalid number of instructions: %s' % num_instructions
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cycles= 0
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self.used_cycles= 0
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for _ in range(number):
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cycles += self.cpu.execute_one_instruction()
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self.used_cycles += self.cpu.execute_one_instruction()
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self.used_cycles = cycles
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def rununtil(self, address, ignore):
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"""Execute instructions until PC == address.
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def rununtil(address, ignore):
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pass
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address address at which to stop
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"""
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def checklast(device, value):
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pass
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new_address = self.str2int(address)
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if new_address is None:
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return 'rununtil: invalid stop address: %s' % address
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self.used_cycles= 0
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while self.cpu.PC != new_address:
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self.used_cycles += self.cpu.execute_one_instruction()
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def checkcycles(self, cycles, ignore):
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"""Check that opcode cycles used is correct.
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@ -222,58 +251,67 @@ class TestCPU(object):
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cycles expected number of cycles used
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"""
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cycles = self.str2int(cycles)
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num_cycles = self.str2int(cycles)
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if num_cycles is None:
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return 'checkcycles: invalid number of cycles: %s' % cycles
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if cycles != self.used_cycles:
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if num_cycles != self.used_cycles:
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return ('Run used %d cycles, expected %d'
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% (self.used_cycles, cycles))
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% (self.used_cycles, num_cycles))
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def checkreg(self, reg, value):
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"""Check register is as it should be."""
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if not reg:
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return 'checkreg: requires a register name'
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if value:
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value = self.str2int(value)
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else:
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return 'checkreg: requires a value'
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new_value = self.str2int(value)
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if new_value is None:
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return 'checkreg: bad value: %s' % str(value)
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if reg == 'ac':
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self.reg_values[reg] = self.cpu.AC
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if self.cpu.AC != value:
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if self.cpu.AC != new_value:
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return ('AC wrong, is %07o, should be %07o'
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% (self.cpu.AC, value))
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% (self.cpu.AC, new_value))
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elif reg == 'l':
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self.reg_values[reg] = self.cpu.L
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if self.cpu.L != value:
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return 'L wrong, is %02o, should be %02o' % (self.cpu.L, value)
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if self.cpu.L != new_value:
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return ('L wrong, is %02o, should be %02o'
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% (self.cpu.L, new_value))
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elif reg == 'pc':
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self.reg_values[reg] = self.cpu.PC
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if self.cpu.PC != value:
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if self.cpu.PC != new_value:
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return ('PC wrong, is %07o, should be %07o'
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% (self.cpu.PC, value))
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% (self.cpu.PC, new_value))
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elif reg == 'ds':
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self.reg_values[reg] = self.cpu.DS
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if self.cpu.DS != value:
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if self.cpu.DS != new_value:
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return ('DS wrong, is %07o, should be %07o'
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% (self.cpu.DS, value))
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% (self.cpu.DS, new_value))
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else:
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raise Exception('checkreg: bad register name: %s' % name)
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return 'checkreg: bad register name: %s' % str(name)
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def checkmem(self, addr, value):
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"""Check a memory location is as it should be."""
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self.mem_values[addr] = value
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new_addr = self.str2int(addr)
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if new_addr is None:
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return 'checkmem: bad address: %s' % str(addr)
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new_value = self.str2int(value)
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if new_value is None:
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return 'checkmem: bad value: %s' % str(value)
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memvalue = self.memory.fetch(addr, False)
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if memvalue != value:
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self.mem_values[new_addr] = new_value
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memvalue = self.memory.fetch(new_addr, False)
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if memvalue != new_value:
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return ('Memory wrong at address %07o, is %07o, should be %07o'
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% (addr, memvalue, value))
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% (new_addr, memvalue, new_value))
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def checkcpu(self, state, ignore):
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"""Check main CPU run state is as desired."""
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if state not in ('on', 'off'):
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return 'checkcpu: bad state: %s' % str(state)
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cpu_state = str(self.cpu.running).lower()
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if ((state == "on" and cpu_state != "true") or
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@ -284,6 +322,9 @@ class TestCPU(object):
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def checkdcpu(self, state, ignore):
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"""Check display CPU run state is as desired."""
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if state not in ('on', 'off'):
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return 'checkdcpu: bad state: %s' % str(state)
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dcpu_state = str(self.display.running).lower()
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if ((state == "on" and dcpu_state != "true") or
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@ -364,14 +405,6 @@ class TestCPU(object):
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else:
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raise Exception('setd: bad state: %s' % str(state))
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def checkd(self, state, var2):
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"""Check display state is as expected."""
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if state == 'on' and self.display_state is not True:
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return 'DCPU run state is %s, should be True' % str(self.display_state)
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if state == 'off' and self.display_state is True:
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return 'DCPU run state is %s, should be False' % str(self.display_state)
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def debug_operation(self, op, var1, var2):
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"""Write operation to log file."""
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@ -433,6 +466,8 @@ class TestCPU(object):
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r = self.setmem(fld1, fld2)
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elif opcode == 'run':
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r = self.run(fld1, fld2)
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elif opcode == 'rununtil':
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r = self.rununtil(fld1, fld2)
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elif opcode == 'checkcycles':
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r = self.checkcycles(fld1, fld2)
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elif opcode == 'checkreg':
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@ -445,10 +480,18 @@ class TestCPU(object):
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r = self.allmem(fld1, fld2)
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elif opcode == 'checkcpu':
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r = self.checkcpu(fld1, fld2)
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elif opcode == 'checkdcpu':
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r = self.checkdcpu(fld1, fld2)
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elif opcode == 'setd':
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r = self.setd(fld1, fld2)
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elif opcode == 'checkd':
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r = self.checkd(fld1, fld2)
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elif opcode == 'bootrom':
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r = self.bootrom(fld1, fld2)
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elif opcode == 'romwrite':
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r = self.romwrite(fld1, fld2)
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elif opcode == 'mount':
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r = self.mount(fld1, fld2)
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elif opcode == 'dismount':
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r = self.dismount(fld1, fld2)
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else:
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raise Exception("Unrecognized opcode '%s' in: %s" % (opcode, test))
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