From cd0b1f00513de7eb973fb48da189d6e0418b0dbc Mon Sep 17 00:00:00 2001
From: Ross Wilson <rzzzwilson@gmail.com>
Date: Mon, 26 Oct 2015 16:30:09 +0700
Subject: [PATCH] New test file, fixed bugs

---
 pymlac/CPU.test    | 31 ++++++++++++++++---------------
 pymlac/test_CPU.py | 18 ++++++++++++------
 2 files changed, 28 insertions(+), 21 deletions(-)

diff --git a/pymlac/CPU.test b/pymlac/CPU.test
index 6c132e8..e257c66 100644
--- a/pymlac/CPU.test
+++ b/pymlac/CPU.test
@@ -1,5 +1,6 @@
 # LAW
-setreg ac 0177777; setreg l 1; setmem 0100 [LAW 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
+setreg ac 0177777; setreg l 1; setmem 0100 [LAW 0]; RUN 0100;
+    checkcycles 1; checkreg pc 0101; checkreg ac 0
 setreg ac 0177777; setreg l 0; setmem 0100 [LAW 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
 setreg ac 0; setreg l 1; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
 setreg ac 0; setreg l 0; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
@@ -73,11 +74,11 @@ setreg ac 0177777; setreg l 1; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem
 setreg ac 0125252; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
 setreg ac 0000777; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
 
-setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
-setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
-setreg ac 0177777; setreg l 1; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
-setreg ac 0125252; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
-setreg ac 0000777; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
+setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
+setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
+setreg ac 0177777; setreg l 1; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
+setreg ac 0125252; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
+setreg ac 0000777; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
 
 # XOR
 setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
@@ -96,13 +97,13 @@ setreg ac 0177777; setreg l 1; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem
 setreg ac 0125252; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
 setreg ac 0000777; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
 
-setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
-setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
-setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
-setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
-setreg ac 0177777; setreg l 1; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776
-setreg ac 0125252; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
-setreg ac 0000777; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
+setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
+setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
+setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
+setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
+setreg ac 0177777; setreg l 1; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776; checkmem 010 0121
+setreg ac 0125252; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
+setreg ac 0000777; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
 
 # LAC
 setreg ac 1; setmem 0100 [LAC 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
@@ -196,10 +197,10 @@ setreg ac 0177777; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776;
 setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121
 
 # HLT
-setmem 0100 [HLT]; RUN 0100; checkcycles 1; checkrun false; checkreg pc 0101
+setmem 0100 [HLT]; RUN 0100; checkcycles 1; checkrun off; checkreg pc 0101
 
 # NOP
-setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkrun true; checkreg pc 0101
+setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkrun on; checkreg pc 0101
 
 # CLA
 setreg ac 0; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
diff --git a/pymlac/test_CPU.py b/pymlac/test_CPU.py
index f31d042..a0faa65 100644
--- a/pymlac/test_CPU.py
+++ b/pymlac/test_CPU.py
@@ -281,7 +281,10 @@ class TestCPU(object):
     def checkrun(self, state, var2):
         """Check CPU run state is as desired."""
 
-        if str(self.cpu.running).lower() != state:
+        cpu_state = str(self.cpu.running).lower()
+
+        if ((state == "on" and cpu_state != "true") or
+            (state == "off" and cpu_state != "false")):
             return 'CPU run state is %s, should be %s' % (str(self.cpu.running), str(state))
 
     def setd(self, state, var2):
@@ -341,6 +344,9 @@ class TestCPU(object):
         instructions = test.split(';')
         for op in instructions:
             fields = op.split(None, 2)
+            if not fields:
+                continue;
+
             op = fields[0].lower()
             try:
                 var1 = fields[1].lower()
@@ -437,18 +443,18 @@ class TestCPU(object):
         tests = []
         test = ''
         for line in lines:
-            line = line[:-1]        # strip newline
+            line = line[:-1]                # strip newline
             if not line:
-                continue            # skip blank lines
+                continue                    # skip blank lines
 
-            if line[0] == '#':      # a comment
+            if line[0] == '#':              # a comment
                 continue
 
-            if line[0] == '\t':     # continuation
+            if line[0] in ('\t', ' '):      # continuation
                 if test:
                     test += '; '
                 test += line[1:]
-            else:                   # beginning of new test
+            else:                           # beginning of new test
                 if test:
                     tests.append(test)
                 test = line