mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Rethink trace, shows 'DAC *10' problem
This commit is contained in:
Ross Wilson
parent
a5c48fb43e
commit
d3db063bd2
@ -169,13 +169,14 @@ class MainCPU(object):
|
||||
return self.BlockBase | address
|
||||
|
||||
def execute_one_instruction(self):
|
||||
"""Execute one MAIN instruction, return # cycles used and if traced."""
|
||||
"""Execute one MAIN instruction, return # cycles and a trace string."""
|
||||
|
||||
if not self.running:
|
||||
return 0
|
||||
return (0, None)
|
||||
|
||||
# get instruction word to execute, advance PC
|
||||
instruction = self.memory.fetch(self.PC, False)
|
||||
self.dot = self.PC
|
||||
instruction = self.memory.fetch(self.dot, False)
|
||||
self.BlockBase = self.PC & ADDRHIGHMASK
|
||||
self.PC = MASK_MEM(self.PC + 1)
|
||||
|
||||
@ -209,34 +210,34 @@ class MainCPU(object):
|
||||
instruction)
|
||||
|
||||
def i_LAW_LWC(self, indirect, address, instruction):
|
||||
traced = False
|
||||
tracestr = None
|
||||
if indirect:
|
||||
self.AC = ~address & WORDMASK
|
||||
traced = trace.itrace('LWC', False, address)
|
||||
tracestr = trace.itrace(self.dot, 'LWC', False, address)
|
||||
else:
|
||||
self.AC = address
|
||||
traced = trace.itrace('LAW', False, address)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'LAW', False, address)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_JMP(self, indirect, address, instruction):
|
||||
address = self.memory.eff_address(address, indirect)
|
||||
self.PC = address & PCMASK
|
||||
traced = trace.itrace('JMP', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'JMP', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_DAC(self, indirect, address, instruction):
|
||||
address = self.memory.eff_address(address, indirect)
|
||||
self.memory.put(self.AC, address, False)
|
||||
traced = trace.itrace('DAC', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DAC', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_XAM(self, indirect, address, instruction):
|
||||
address = self.memory.eff_address(address, indirect)
|
||||
tmp = self.memory.fetch(address, False)
|
||||
self.memory.put(self.AC, address, False)
|
||||
self.AC = tmp
|
||||
traced = trace.itrace('XAM', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'XAM', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_ISZ(self, indirect, address, instruction):
|
||||
address = self.memory.eff_address(address, indirect)
|
||||
@ -244,43 +245,43 @@ class MainCPU(object):
|
||||
self.memory.put(value, address, False)
|
||||
if value == 0:
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('ISZ', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ISZ', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_JMS(self, indirect, address, instruction):
|
||||
address = self.memory.eff_address(address, indirect)
|
||||
self.memory.put(self.PC, address, False)
|
||||
self.PC = (address + 1) & PCMASK
|
||||
traced = trace.itrace('JMS', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'JMS', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_AND(self, indirect, address, instruction):
|
||||
self.AC &= self.memory.fetch(address, indirect)
|
||||
traced = trace.itrace('AND', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'AND', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_IOR(self, indirect, address, instruction):
|
||||
self.AC |= self.memory.fetch(address, indirect)
|
||||
traced = trace.itrace('IOR', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOR', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_XOR(self, indirect, address, instruction):
|
||||
self.AC ^= self.memory.fetch(address, indirect)
|
||||
traced = trace.itrace('XOR', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'XOR', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_LAC(self, indirect, address, instruction):
|
||||
self.AC = self.memory.fetch(address, indirect)
|
||||
traced = trace.itrace('LAC', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'LAC', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_ADD(self, indirect, address, instruction):
|
||||
self.AC += self.memory.fetch(self.BLOCKADDR(address), indirect)
|
||||
if self.AC & OVERFLOWMASK:
|
||||
self.L = (~self.L) & 01
|
||||
self.AC &= WORDMASK
|
||||
traced = trace.itrace('ADD', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ADD', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_SUB(self, indirect, address, instruction):
|
||||
addit = self.memory.fetch(self.BLOCKADDR(address), indirect)
|
||||
@ -289,15 +290,15 @@ class MainCPU(object):
|
||||
if self.AC & OVERFLOWMASK:
|
||||
self.L = ~self.L
|
||||
self.AC &= WORDMASK
|
||||
traced = trace.itrace('SUB', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SUB', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def i_SAM(self, indirect, address, instruction):
|
||||
samaddr = self.BLOCKADDR(address)
|
||||
if self.AC == self.memory.fetch(samaddr, indirect):
|
||||
self.PC = (self.PC + 1) & PCMASK
|
||||
traced = trace.itrace('SAM', indirect, address)
|
||||
return (3, traced) if indirect else (2, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAM', indirect, address)
|
||||
return (3, tracestr) if indirect else (2, tracestr)
|
||||
|
||||
def microcode(self, instruction):
|
||||
# T1
|
||||
@ -338,149 +339,149 @@ class MainCPU(object):
|
||||
if instruction & k:
|
||||
combine.append(op)
|
||||
|
||||
traced = trace.itrace('+'.join(combine), False)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, '+'.join(combine), False)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_DLA(self, indirect, address, instruction):
|
||||
self.displaycpu.DPC = self.AC
|
||||
traced = trace.itrace('DLA')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DLA')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_CTB(self, indirect, address, instruction):
|
||||
traced = trace.itrace('CTB')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'CTB')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_DOF(self, indirect, address, instruction):
|
||||
self.displaycpu.stop()
|
||||
traced = trace.itrace('DOF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DOF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_KRB(self, indirect, address, instruction):
|
||||
self.AC |= self.kbd.read()
|
||||
traced = trace.itrace('KRB')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'KRB')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_KCF(self, indirect, address, instruction):
|
||||
self.kbd.clear()
|
||||
traced = trace.itrace('KCF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'KCF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_KRC(self, indirect, address, instruction):
|
||||
self.AC |= self.kbd.read()
|
||||
self.kbd.clear()
|
||||
traced = trace.itrace('KRC')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'KRC')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RRB(self, indirect, address, instruction):
|
||||
self.AC |= self.ttyin.read()
|
||||
traced = trace.itrace('RRB')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RRB')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RCF(self, indirect, address, instruction):
|
||||
self.ttyin.clear()
|
||||
traced = trace.itrace('RCF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RCF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RRC(self, indirect, address, instruction):
|
||||
self.AC |= self.ttyin.read()
|
||||
self.ttyin.clear()
|
||||
traced = trace.itrace('RRC')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RRC')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_TPR(self, indirect, address, instruction):
|
||||
self.ttyout.write(self.AC & 0xff)
|
||||
traced = trace.itrace('TPR')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'TPR')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_TCF(self, indirect, address, instruction):
|
||||
self.ttyout.clear()
|
||||
traced = trace.itrace('TCF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'TCF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_TPC(self, indirect, address, instruction):
|
||||
self.ttyout.write(self.AC & 0xff)
|
||||
self.ttyout.clear()
|
||||
traced = trace.itrace('TPC')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'TPC')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_HRB(self, indirect, address, instruction):
|
||||
self.AC |= self.ptrptp.read()
|
||||
traced = trace.itrace('HRB')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'HRB')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_HOF(self, indirect, address, instruction):
|
||||
self.ptrptp.stop()
|
||||
traced = trace.itrace('HOF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'HOF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_HON(self, indirect, address, instruction):
|
||||
self.ptrptp.start()
|
||||
traced = trace.itrace('HON')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'HON')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_STB(self, indirect, address, instruction):
|
||||
traced = trace.itrace('STB')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'STB')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SCF(self, indirect, address, instruction):
|
||||
self.Sync40Hz = 0
|
||||
traced = trace.itrace('SCF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SCF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOS(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOS')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOS')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT101(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT101')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT101')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT111(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT111')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT111')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT131(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT131')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT131')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT132(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT132')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT132')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT134(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT134')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT134')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOT141(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOT141')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOT141')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_IOF(self, indirect, address, instruction):
|
||||
traced = trace.itrace('IOF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'IOF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_ION(self, indirect, address, instruction):
|
||||
traced = trace.itrace('ION')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ION')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_PPC(self, indirect, address, instruction):
|
||||
self.ptrptp.punch(self.AC & 0xff)
|
||||
traced = trace.itrace('PPC')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'PPC')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_PSF(self, indirect, address, instruction):
|
||||
if self.ptrptp.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('PSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'PSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAL1(self, indirect, address, instruction):
|
||||
newl = self.AC >> 15
|
||||
newac = (self.AC << 1) | self.L
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAL', False, 1)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAL', False, 1)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAL2(self, indirect, address, instruction):
|
||||
newl = self.AC >> 15
|
||||
@ -491,8 +492,8 @@ class MainCPU(object):
|
||||
newac = (self.AC << 1) | self.L
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAL', False, 2)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAL', False, 2)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAL3(self, indirect, address, instruction):
|
||||
newl = self.AC >> 15
|
||||
@ -507,16 +508,16 @@ class MainCPU(object):
|
||||
newac = (self.AC << 1) | self.L
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAL', False, 3)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAL', False, 3)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAR1(self, indirect, address, instruction):
|
||||
newl = self.AC & 1
|
||||
newac = (self.AC >> 1) | (self.L << 15)
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAR', False, 1)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAR', False, 1)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAR2(self, indirect, address, instruction):
|
||||
newl = self.AC & 1
|
||||
@ -527,8 +528,8 @@ class MainCPU(object):
|
||||
newac = (self.AC >> 1) | (self.L << 15)
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAR', False, 2)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAR', False, 2)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RAR3(self, indirect, address, instruction):
|
||||
newl = self.AC & 1
|
||||
@ -543,162 +544,162 @@ class MainCPU(object):
|
||||
newac = (self.AC >> 1) | (self.L << 15)
|
||||
self.L = newl
|
||||
self.AC = newac & WORDMASK
|
||||
traced = trace.itrace('RAR', False, 3)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RAR', False, 3)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAL1(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
value = self.AC & 037777
|
||||
self.AC = (value << 1) | high_bit
|
||||
traced = trace.itrace('SAL', False, 1)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAL', False, 1)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAL2(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
value = self.AC & 017777
|
||||
self.AC = (value << 2) | high_bit
|
||||
traced = trace.itrace('SAL', False, 2)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAL', False, 2)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAL3(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
value = self.AC & 007777
|
||||
self.AC = (value << 3) | high_bit
|
||||
traced = trace.itrace('SAL', False, 3)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAL', False, 3)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAR1(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
traced = trace.itrace('SAR', False, 1)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAR', False, 1)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAR2(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
traced = trace.itrace('SAR', False, 2)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAR', False, 2)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SAR3(self, indirect, address, instruction):
|
||||
high_bit = self.AC & HIGHBITMASK
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
self.AC = (self.AC >> 1) | high_bit
|
||||
traced = trace.itrace('SAR', False, 3)
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SAR', False, 3)
|
||||
return (1, tracestr)
|
||||
|
||||
def i_DON(self, indirect, address, instruction):
|
||||
self.displaycpu.DRSindex = 0
|
||||
self.displaycpu.start()
|
||||
traced = trace.itrace('DON')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DON')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_ASZ(self):
|
||||
if self.AC == 0:
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('ASZ')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ASZ')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_ASN(self):
|
||||
if self.AC != 0:
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('ASN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ASN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_ASP(self):
|
||||
if not (self.AC & HIGHBITMASK):
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('ASP')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ASP')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_ASM(self):
|
||||
if (self.AC & HIGHBITMASK):
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('ASM')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'ASM')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_LSZ(self):
|
||||
if self.L == 0:
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('LSZ')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'LSZ')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_LSN(self):
|
||||
if self.L != 0:
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('LSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'LSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_DSF(self):
|
||||
if self.displaycpu.ison():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('DSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_DSN(self):
|
||||
if not self.displaycpu.ison():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('DSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'DSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_KSF(self):
|
||||
if self.kbd.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('KSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'KSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_KSN(self):
|
||||
if not self.kbd.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('KSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'KSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RSF(self):
|
||||
if self.ttyin.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('RSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_RSN(self):
|
||||
if not self.ttyin.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('RSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'RSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_TSF(self):
|
||||
if self.ttyout.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('TSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'TSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_TSN(self):
|
||||
if not self.ttyout.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('TSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'TSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SSF(self):
|
||||
if self.display.ready(): # skip if 40Hz sync on
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('SSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_SSN(self):
|
||||
if not self.display.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('SSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'SSN')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_HSF(self):
|
||||
if self.ptrptp.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('HSF')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'HSF')
|
||||
return (1, tracestr)
|
||||
|
||||
def i_HSN(self):
|
||||
if not self.ptrptp.ready():
|
||||
self.PC = (self.PC + 1) & WORDMASK
|
||||
traced = trace.itrace('HSN')
|
||||
return (1, traced)
|
||||
tracestr = trace.itrace(self.dot, 'HSN')
|
||||
return (1, tracestr)
|
||||
|
||||
|
||||
@ -80,62 +80,65 @@ class Trace(object):
|
||||
self.tracefile.write('%s\t%s\t' % (opcode, code))
|
||||
self.tracefile.flush()
|
||||
|
||||
def dtrace(self, opcode, address=None):
|
||||
def dtrace(self, ddot, opcode, address=None):
|
||||
"""Trace the display CPU.
|
||||
|
||||
ddot address of instruction being traced
|
||||
opcode display opcode
|
||||
address address for the opcode
|
||||
|
||||
Returns the trace string or None if not tracing.
|
||||
"""
|
||||
|
||||
result = None
|
||||
|
||||
if self.tracing:
|
||||
if address is None:
|
||||
self.tracefile.write('%s\t\t' % opcode)
|
||||
result = '%04o: %s\t' % (ddot, opcode)
|
||||
else:
|
||||
self.tracefile.write('%s\t%5.5o\t' % (opcode, address))
|
||||
self.tracefile.flush()
|
||||
result = '%04o: %s\t%5.5o' % (ddot, opcode, address)
|
||||
|
||||
def itrace(self, opcode, indirect=False, address=None):
|
||||
return result
|
||||
|
||||
def itrace(self, dot, opcode, indirect=False, address=None):
|
||||
"""Main CPU trace.
|
||||
|
||||
opcode the main CPU opcode
|
||||
dot address of instruction being traced
|
||||
opcode the main CPU opcode
|
||||
indirect True if instruction was indirect
|
||||
address address for the instruction (if any)
|
||||
|
||||
Returns True if tracing, else False.
|
||||
Returns the trace string or None if not tracing.
|
||||
"""
|
||||
|
||||
# print('itrace: self.cpu.PC=%06o, self.trace_map[self.cpu.PC]=%s'
|
||||
# % (self.cpu.PC-1, str(self.trace_map[self.cpu.PC-1])))
|
||||
|
||||
if self.tracing and self.trace_map[self.cpu.PC-1]:
|
||||
result = None
|
||||
if self.tracing and self.trace_map[dot]:
|
||||
char = '*' if indirect else ''
|
||||
if address is None:
|
||||
self.tracefile.write('%s\t%s\t' % (opcode, char))
|
||||
result = '%04o\t%s\t%s' % (dot, opcode, char)
|
||||
else:
|
||||
self.tracefile.write('%s\t%s%5.5o\t' % (opcode, char, address))
|
||||
self.tracefile.flush()
|
||||
return True
|
||||
result = '%04o\t%s\t%s%5.5o' % (dot, opcode, char, address)
|
||||
|
||||
return False
|
||||
return result
|
||||
|
||||
def itraceend(self, dispon):
|
||||
"""Trace at the end of one execution cycle.
|
||||
|
||||
dispon True if the display was on
|
||||
|
||||
Returns the trace string.
|
||||
"""
|
||||
|
||||
self.tracefile.write('L=%1.1o AC=%6.6o PC=%6.6o'
|
||||
% (self.cpu.L, self.cpu.AC, self.cpu.PC))
|
||||
result = ('L=%1.1o AC=%6.6o PC=%6.6o'
|
||||
% (self.cpu.L, self.cpu.AC, self.cpu.PC))
|
||||
|
||||
if dispon:
|
||||
self.tracefile.write(' DX=%5.5o DY=%6.6o'
|
||||
% (self.dcpu.DX, self.dcpu.DY))
|
||||
self.tracefile.write('\n')
|
||||
result += ' DX=%5.5o DY=%5.5o' % (self.dcpu.DX, self.dcpu.DY)
|
||||
|
||||
self.tracefile.flush()
|
||||
return result
|
||||
|
||||
def comment(self, msg):
|
||||
"""Add a comment to the trace."""
|
||||
"""Write a line to the trace file."""
|
||||
|
||||
self.tracefile.write(msg+'\n')
|
||||
self.tracefile.flush()
|
||||
|
||||
@ -82,9 +82,10 @@ def start_running(cpu, memory, ptrptp):
|
||||
|
||||
cpu.running = True
|
||||
while cpu.running:
|
||||
(cycles, traced) = cpu.execute_one_instruction()
|
||||
if traced:
|
||||
trace.itraceend(False)
|
||||
(cycles, tracestr) = cpu.execute_one_instruction()
|
||||
if tracestr:
|
||||
endstr = trace.itraceend(False)
|
||||
trace.comment('%s\t%s' % (tracestr, endstr))
|
||||
ptrptp.ptr_tick(cycles)
|
||||
ptrptp.ptp_tick(cycles)
|
||||
|
||||
@ -126,19 +127,15 @@ def main():
|
||||
dev = sys.argv[ndx].lower()
|
||||
ndx += 1
|
||||
if dev == 'ptr':
|
||||
# set_bootrom('PTR')
|
||||
imlac_memory.set_ROM('ptr')
|
||||
elif dev == 'tty':
|
||||
# set_bootrom('TTYIN')
|
||||
imlac_memory.set_ROM('tty')
|
||||
elif dev == 'none':
|
||||
# set_bootrom(None)
|
||||
imlac_memory.set_ROM(None)
|
||||
else:
|
||||
usage("-b option must be followed by 'ptr', 'tty' or 'none'")
|
||||
sys.exit(10)
|
||||
elif opt == '-c':
|
||||
# clear_core()
|
||||
imlac_memory.clear_core()
|
||||
elif opt == '-cf':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -146,7 +143,6 @@ def main():
|
||||
sys.exit(10)
|
||||
filename = sys.argv[ndx]
|
||||
ndx += 1
|
||||
# set_core_file(filename)
|
||||
imlac_memory.set_corefile(filename)
|
||||
elif opt == '-d':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -157,7 +153,6 @@ def main():
|
||||
if value is None:
|
||||
usage("The '-d' option must be followed by a decimal or octal value")
|
||||
sys.exit(10)
|
||||
# set_data_switch(value)
|
||||
imlac_cpu.DS = value
|
||||
elif opt == '-h':
|
||||
usage()
|
||||
@ -168,7 +163,6 @@ def main():
|
||||
sys.exit(10)
|
||||
filename = sys.argv[ndx]
|
||||
ndx += 1
|
||||
# set_ptp_filename(filename)
|
||||
imlac_ptrptp.ptp_mount(filename)
|
||||
elif opt == '-ptr':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -176,7 +170,6 @@ def main():
|
||||
sys.exit(10)
|
||||
filename = sys.argv[ndx]
|
||||
ndx += 1
|
||||
# set_ptr_filename(filename)
|
||||
imlac_ptrptp.ptr_mount(filename)
|
||||
elif opt == '-r':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -189,7 +182,6 @@ def main():
|
||||
if addr_value is None:
|
||||
usage("'-r' option needs a following address or 'pc'")
|
||||
sys.exit(10)
|
||||
# set_pc(addr_value)
|
||||
imlac_cpu.PC = addr_value
|
||||
trace.set_trace_map(trace_map)
|
||||
start_running(imlac_cpu, imlac_memory, imlac_ptrptp)
|
||||
@ -206,10 +198,8 @@ def main():
|
||||
sys.exit(10)
|
||||
r = sys.argv[ndx]
|
||||
ndx += 1
|
||||
if r == 'off':
|
||||
trace_map = collections.defaultdict(bool)
|
||||
else:
|
||||
trace_map = collections.defaultdict(bool)
|
||||
trace_map = collections.defaultdict(bool)
|
||||
if r != 'off':
|
||||
print('r=%s' % r)
|
||||
for rng in r.split(':'):
|
||||
print('rng=%s' % rng)
|
||||
@ -230,7 +220,6 @@ def main():
|
||||
sys.exit(10)
|
||||
filename = sys.argv[ndx]
|
||||
ndx += 1
|
||||
# set_tty_in(filename)
|
||||
imlac_ttyin.mount(filename)
|
||||
elif opt == '-ttyout':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -238,7 +227,6 @@ def main():
|
||||
sys.exit(10)
|
||||
filename = sys.argv[ndx]
|
||||
ndx += 1
|
||||
# set_tty_out(filename)
|
||||
imlac_ttyout.mount(filename)
|
||||
elif opt == '-v':
|
||||
if ndx >= len_sys_argv:
|
||||
@ -260,7 +248,6 @@ def main():
|
||||
else:
|
||||
usage("'-v' option needs a following 'on' or 'off'")
|
||||
sys.exit(10)
|
||||
# set_rom_write(state)
|
||||
imlac_memory.set_ROM_writable(state)
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user