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https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Getting close, found unwanted writes to address 0
This commit is contained in:
Ross Wilson
parent
01e22d09c8
commit
f53ceca121
@ -1,26 +1,2 @@
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# LAW
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0]; RUN
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checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LAW 0]; RUN
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checkcycles 1; checkreg pc 0101; checkreg ac 0
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0377]; RUN
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checkcycles 1; checkreg pc 0101; checkreg ac 0377
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setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LAW 0377]; RUN
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checkcycles 1; checkreg pc 0101; checkreg ac 0377
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# LWC
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LWC 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LWC 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LWC 1]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [LWC 1]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
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# JMP
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [JMP 0200]; RUN; checkcycles 2; checkreg pc 0200
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setreg ac 012345; setreg l 0; setreg pc 0100; setmem 0100 [JMP 0110]; RUN; checkcycles 2; checkreg pc 0110
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [JMP *0110]; setmem 0110 0120; RUN; checkcycles 3; checkreg pc 0120
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setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [JMP *010]; setmem 010 0120; RUN checkcycles 3; checkreg pc 0120; checkmem 010 0121
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# DAC
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setreg ac 1; setreg l 1; setreg pc 0100; setmem 0100 [DAC 0110]; RUN
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checkcycles 2; checkreg pc 0101; checkmem 0110 1
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setreg ac 0177777; setreg l 0; setreg pc 0100; setmem 0100 [DAC *0110]; setmem 0110 0120; RUN
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checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
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setreg ac 0177777; setreg l 1; setreg pc 0100; setmem 0100 [DAC *010]; setmem 010 0120; RUN
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checkcycles 3; checkreg pc 0101; checkmem 0120 0177777; checkmem 010 0121
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checkcycles 3; checkreg pc 0101; checkmem 0121 0177777; checkmem 010 0121
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@ -221,7 +221,6 @@ def fetch(address, indirect):
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return memory[address]
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def eff_address(address, indirect):
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#def get(address, indirect):
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"""Get an effective memory address.
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The address can be indirect, and may be through an
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@ -61,10 +61,56 @@ where <filename> is a file of test instructions and
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# If any errors are found, print line followed by all errors.
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import os
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from Globals import *
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import MainCPU
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import Memory
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import log
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log = log.Log('test_CPU.log', log.Log.DEBUG)
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# number of cycles used in previous instruction
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UsedCycles = 0
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# register+value explicitly set by test
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RegValues = {}
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# memory address+value explicitly set by test
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MemValues = {}
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# memory value all explicitly set to (shouldn't change)
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MemAllValue = None
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# registers value all explicitly set to (shouldn't change)
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RegAllValue = None
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# temporary assembler file and listfile prefix
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AsmFilename = '_#ASM#_'
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def assemble(addr, opcode):
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"""Assemble a single instruction, return opcode."""
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# create ASM file with instruction
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with open(AsmFilename+'.asm', 'wb') as fd:
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fd.write('\torg\t%07o\n' % addr)
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fd.write('\t%s\n' % opcode[1:-1])
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fd.write('\tend\n')
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# now assemble file
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os.system('../iasm/iasm -l %s.lst %s.asm' % (AsmFilename, AsmFilename))
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# read the listing file to get assembled opcode
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with open(AsmFilename+'.lst', 'rb') as fd:
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lines = fd.readlines()
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line = lines[1]
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(opcode, _) = line.split(None, 1)
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print('opcode=%07o' % int(opcode, base=8))
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return int(opcode, base=8)
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def setreg(name, value):
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"""Set register to a value.
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@ -72,20 +118,44 @@ def setreg(name, value):
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Remember value to check later.
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"""
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log.debug('setreg: name=%s, value=%s' % (name, oct(value)))
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global RegValues
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RegValues[name] = value
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log.debug('setreg: After, RegValues=%s' % str(RegValues))
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exec "MainCPU.%s = %07o" % (name, value)
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if name == 'ac':
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MainCPU.AC = value
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log.debug('setreg: After, AC=%s' % oct(MainCPU.AC))
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elif name == 'l':
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MainCPU.L = value & 1
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log.debug('setreg: After, L=%s' % oct(MainCPU.L))
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elif name == 'pc':
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MainCPU.PC = value
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log.debug('setreg: After, PC=%s' % oct(MainCPU.PC))
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def setmem(addr, value):
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"""Set memory location to a value."""
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if isinstance(value, basestring):
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), value))
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else:
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), oct(value)))
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global MemValues
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MemValues[addr] = value
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# check if we must assemble var2
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if isinstance(value, basestring) and value[0] == '[':
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# assemble an instruction
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value = assemble(addr, value)
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log.debug('setmem: assembled opcode=%07o' % value)
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Memory.memory[addr] = value
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MemValues[addr] = value
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log.debug('setmem: After, MemValues=%s' % str(MemValues))
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Memory.put(value, addr, False)
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log.debug('setmem: After, Memory at %07o is %07o' % (addr, Memory.fetch(addr, False)))
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def allmem(value):
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@ -98,9 +168,8 @@ def allmem(value):
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MemAllValue = value
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for mem in range(PCMASK):
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print str(mem)
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Memory.memory[mem] = value
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for mem in range(MEMORY_SIZE):
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Memory.put(mem, value, False)
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def allreg(value):
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"""Set all registers to a value."""
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@ -113,12 +182,105 @@ def allreg(value):
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MainCPU.L = value & 1
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MainCPU.PC = value
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def check_all_mem():
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"""Check memory for unwanted changes."""
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for mem in range(MEMORY_SIZE):
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if mem in MemValues:
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continue
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value = Memory.fetch(mem, False)
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if value != MemAllValue:
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return ('Changed memory at address %07o, is %07o, should be %07o'
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% (mem, value, MemAllValue))
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def check_all_regs():
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"""Check registers for unwanted changes."""
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result = []
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if 'ac' not in RegValues:
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if MainCPU.AC != RegAllValue:
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result.append('AC changed, is %07o, should be %07o'
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% (MainCPU.AC, RegAllValue))
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if 'l' not in RegValues:
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if MainCPU.L != RegAllValue & 1:
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result.append('L changed, is %02o, should be %02o'
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% (MainCPU.L, RegAllValue & 1))
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if 'pc' not in RegValues:
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if MainCPU.PC != RegAllValue:
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result.append('PC changed, is %07o, should be %07o'
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% (MainCPU.PC, RegAllValue))
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if result:
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return result.join('\n')
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def checkreg(reg, value):
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"""Check register is as it should be."""
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global RegValues
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RegValues[reg] = value
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log.debug('checkreg: After, RegValues=%s' % str(RegValues))
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if reg == 'ac':
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if MainCPU.AC != value:
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return 'AC wrong, is %07o, should be %07o' % (MainCPU.AC, value)
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elif reg == 'l':
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if MainCPU.L != value:
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return 'L wrong, is %07o, should be %07o' % (MainCPU.L, value)
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elif reg == 'pc':
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if MainCPU.PC != value:
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return 'AC wrong, is %07o, should be %07o' % (MainCPU.PC, value)
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else:
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raise Exception('checkreg: bad register name: %s' % name)
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def checkmem(addr, value):
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"""Check a memory location is as it should be."""
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global MemValues
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MemValues[addr] = value
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log.debug('checkmem: After, MemValues=%s' % str(MemValues))
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memvalue = Memory.fetch(addr, False)
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if memvalue != value:
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return 'Memory wrong at address %07o, is %07o, should be %07o' % (addr, memvalue, value)
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def checkcycles(cycles, var2=None):
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"""Check that opcode cycles used is correct."""
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if cycles != UsedCycles:
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return 'Opcode used %d cycles, expected %d' % (UsedCycles, cycles)
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def run(addr, var2):
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"""Execute instruction."""
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global UsedCycles
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if addr is not None:
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# force PC to given address
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setreg('pc', addr)
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UsedCycles = MainCPU.execute_one_instruction()
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def debug_operation(op, var1, var2):
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"""Write operation to log file."""
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if var1:
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if var2:
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log.debug('Operation: %s %s %s' % (op, var1, var2))
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else:
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log.debug('Operation: %s %s' % (op, var1))
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else:
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log.debug('Operation: %s' % op)
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def execute(test):
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"""Execute test string in 'test'."""
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global RegValues, MemValues
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global RegAllValue, MemAllValue
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global Test
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# set globals
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RegValues = {}
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@ -126,11 +288,15 @@ def execute(test):
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RegAllValue = {}
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MemAllValue = {}
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Test = test
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result = []
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MainCPU.init()
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MainCPU.running = True
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Memory.init()
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# clear memory and registers to 0 first
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# allmem(0)
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# allreg(0)
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allmem(0)
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allreg(0)
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# interpret the test instructions
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instructions = test.split(';')
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@ -146,35 +312,77 @@ def execute(test):
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except IndexError:
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var2 = None
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try:
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if op == 'setreg':
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setreg(var1, var2)
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elif op == 'setmem':
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setmem(var1, var2)
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elif op == 'run':
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run(var1, var2)
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elif op == 'checkcycles':
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checkcycles(var1, var2)
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elif op == 'checkreg':
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checkreg(var1, var2)
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elif op == 'checkmem':
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checkmem(var1, var2)
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elif op == 'allreg':
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allreg(var1, var2)
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elif op == 'allmem':
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allmem(var1, var2)
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debug_operation(op, var1, var2)
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# change var strings into numeric values
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if var1 and var1[0] in '0123456789':
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if var1[0] == '0':
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var1 = int(var1, base=8)
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else:
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error('Unrecognized operation: %s' % test)
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except CPUError:
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pass
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var1 = int(var1)
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if var2 and var2[0] in '0123456789':
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if var2[0] == '0':
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var2 = int(var2, base=8)
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else:
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var2 = int(var2)
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if op == 'setreg':
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r = setreg(var1, var2)
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elif op == 'setmem':
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r = setmem(var1, var2)
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elif op == 'run':
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r = run(var1, var2)
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elif op == 'checkcycles':
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r = checkcycles(var1, var2)
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elif op == 'checkreg':
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r = checkreg(var1, var2)
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elif op == 'checkmem':
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r = checkmem(var1, var2)
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elif op == 'allreg':
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r = allreg(var1, var2)
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elif op == 'allmem':
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r = allmem(var1, var2)
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else:
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error('Unrecognized operation: %s' % test)
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if r is not None:
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result.append(r)
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# now check all memory and regs for changes
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check_all_mem()
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check_all_regs()
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r = check_all_mem()
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if r:
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result.append(r)
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r = check_all_regs()
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if r:
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result.append(r)
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print(test)
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if result:
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print('\t' + '\n\t'.join(result))
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memdump('core.txt', 0, 0200)
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def memdump(filename, start, number):
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"""Dump memory from 'start' into 'filename', 'number' words dumped."""
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with open(filename, 'wb') as fd:
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for addr in range(start, start+number, 8):
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a = addr
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llen = min(8, start+number - addr)
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line = '%04o ' % addr
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for _ in range(llen):
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line += '%06o ' % Memory.fetch(a, False)
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a += 1
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fd.write('%s\n' % line)
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def main(filename):
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"""Execute CPU tests from 'filename'."""
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log.debug("Running test file '%s'" % filename)
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# get all tests from file
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with open(filename, 'rb') as fd:
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lines = fd.readlines()
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@ -203,6 +411,7 @@ def main(filename):
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# now do each test
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for test in tests:
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log.debug('Executing test: %s' % test)
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execute(test)
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