From fe5a61b52fe04309df5a3dbe8a8eb437da9c8e5c Mon Sep 17 00:00:00 2001
From: Ross Wilson <rzzzwilson@gmail.com>
Date: Wed, 10 Jun 2015 17:42:09 +0700
Subject: [PATCH] More test cases

---
 pymlac/test_pymlac.py | 243 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 243 insertions(+)

diff --git a/pymlac/test_pymlac.py b/pymlac/test_pymlac.py
index 7affcc8..11176e6 100644
--- a/pymlac/test_pymlac.py
+++ b/pymlac/test_pymlac.py
@@ -171,6 +171,24 @@ class TestPymlac(unittest.TestCase):
         Trace.settrace(True)
         Memory.init()
 
+        # test "JMP 0100"
+        Memory.memory[0100] = 0010100    # JMP 0100
+        MainCPU.init()
+        MainCPU.AC = 012345
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"JMP 0100" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"JMP 0100" left AC containing %06o, should be 012345' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 012345, msg)
+        msg = '"JMP 0100" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"JMP 0100" modified PC to %06o, should be 0100' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0100, msg)
+
         # test "JMP 0110"
         Memory.memory[0100] = 0010110    # JMP 0110
         MainCPU.init()
@@ -189,6 +207,231 @@ class TestPymlac(unittest.TestCase):
         msg = '"JMP 0110" modified PC to %06o, should be 0110' % MainCPU.PC
         self.assertTrue(MainCPU.PC== 0110, msg)
 
+        # test "JMP *0110"
+        Memory.memory[0100] = 0110110    # JMP *0110
+        Memory.memory[0110] = 0120       # where next PC should be
+        MainCPU.init()
+        MainCPU.AC = 012345
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"JMP *0110" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"JMP *0110" left AC containing %06o, should be 012345' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 012345, msg)
+        msg = '"JMP *0110" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"JMP *0110" modified PC to %06o, should be 0120' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0120, msg)
+
+    def test_DAC(self):
+        Trace.init('test_DAC.trace')
+        Trace.settrace(True)
+        Memory.init()
+
+        # test "DAC 0101"
+        Memory.memory[0100] = 0020101    # DAC 0101
+        Memory.memory[0101] = 0          # value we are storing over
+        MainCPU.init()
+        MainCPU.AC = 1
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"DAC 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"DAC 0101" left AC containing %06o, should be 1' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 1, msg)
+        msg = '"DAC 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"DAC 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"DAC 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
+        self.assertTrue(Memory.memory[0101] == 1, msg)
+
+        # test "DAC *0101"
+        Memory.memory[0100] = 0120101    # DAC *0101
+        Memory.memory[0101] = 0102       # address of cell we are storing into
+        Memory.memory[0102] = 0
+        MainCPU.init()
+        MainCPU.AC = 0177777
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"DAC *0101" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"DAC *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0177777, msg)
+        msg = '"DAC *0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"DAC *0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"DAC *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
+        self.assertTrue(Memory.memory[0102] == 0177777, msg)
+
+    def test_XAM(self):
+        Trace.init('test_XAM.trace')
+        Trace.settrace(True)
+        Memory.init()
+
+        # test "XAM 0101"
+        Memory.memory[0100] = 0024101    # XAM 0101
+        Memory.memory[0101] = 0          # value we are exchanging
+        MainCPU.init()
+        MainCPU.AC = 2
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"XAM 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"XAM 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0, msg)
+        msg = '"XAM 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"XAM 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"XAM 0101" modified memory[0101] to %06o, should be 2' % Memory.memory[0101]
+        self.assertTrue(Memory.memory[0101] == 2, msg)
+
+        # test "XAM *0101"
+        Memory.memory[0100] = 0124101    # XAM *0101
+        Memory.memory[0101] = 0102       # address of cell we are storing into
+        Memory.memory[0102] = 0
+        MainCPU.init()
+        MainCPU.AC = 0177777
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"XAM *0101" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"XAM *0101" left AC containing %06o, should be 0' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0, msg)
+        msg = '"XAM *0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"XAM *0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"XAM *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
+        self.assertTrue(Memory.memory[0102] == 0177777, msg)
+
+    def test_ISZ(self):
+        Trace.init('test_ISZ.trace')
+        Trace.settrace(True)
+        Memory.init()
+
+        # test "ISZ 0101"
+        Memory.memory[0100] = 0024101    # ISZ 0101
+        Memory.memory[0101] = 0          # value we are incrementing/testing
+        MainCPU.init()
+        MainCPU.AC = 2
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"ISZ 0101" left AC containing %06o, should be 2' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 2, msg)
+        msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"ISZ 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"ISZ 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
+        self.assertTrue(Memory.memory[0101] == 1, msg)
+
+        # test "ISZ *0101"
+        Memory.memory[0100] = 0124101    # ISZ *0101
+        Memory.memory[0101] = 0102       # address of cell we are storing into
+        Memory.memory[0102] = 0
+        MainCPU.init()
+        MainCPU.AC = 0177777
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"ISZ *0101" used %d cycles, should be 3' % cycles
+        self.assertTrue(cycles == 3, msg)
+        msg = '"ISZ *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0177777, msg)
+        msg = '"ISZ *0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"ISZ *0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+        msg = '"ISZ *0101" modified memory[0102] to %06o, should be 1' % Memory.memory[0102]
+        self.assertTrue(Memory.memory[0102] == 1, msg)
+
+    def test_ADD(self):
+        Trace.init('test_ADD.trace')
+        Trace.settrace(True)
+        Memory.init()
+
+        # test "ADD 0101"
+        Memory.memory[0100] = 0064101    # ADD 0101
+        Memory.memory[0101] = 0          # value we are adding to PC
+        MainCPU.init()
+        MainCPU.AC = 0
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"ADD 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0, msg)
+        msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+
+        # test "ADD 0101"       add 1 to 0
+        Memory.memory[0100] = 0064101    # ADD 0101
+        Memory.memory[0101] = 1          # value we are adding to PC
+        MainCPU.init()
+        MainCPU.AC = 0
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"ADD 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"ADD 0101" left AC containing %06o, should be 1' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 1, msg)
+        msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
+        self.assertTrue(MainCPU.L == 1, msg)
+        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+
+        # test "ADD 0101"       add 1 to 0177777, L=1 before
+        Memory.memory[0100] = 0064101    # ADD 0101
+        Memory.memory[0101] = 1          # value we are adding to PC
+        MainCPU.init()
+        MainCPU.AC = 0177777
+        MainCPU.L = 1
+        MainCPU.PC = 0100
+        MainCPU.running = True
+        cycles = MainCPU.execute_one_instruction()
+        Trace.itraceend(False)
+        msg = '"ADD 0101" used %d cycles, should be 2' % cycles
+        self.assertTrue(cycles == 2, msg)
+        msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
+        self.assertTrue(MainCPU.AC == 0, msg)
+        msg = '"ADD 0101" modified L to %01o, should be 0' % MainCPU.L
+        self.assertTrue(MainCPU.L == 0, msg)
+        msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
+        self.assertTrue(MainCPU.PC== 0101, msg)
+
 
 
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