mirror of
https://github.com/rzzzwilson/pymlac.git
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309 lines
12 KiB
Python
309 lines
12 KiB
Python
#!/usr/bin/python
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"""
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Emulate the Imlac Memory.
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"""
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import struct
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from Globals import *
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import Trace
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import log
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log = log.Log('test.log', log.Log.DEBUG)
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class Memory(object):
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ROM_START = 040
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ROM_SIZE = 040
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ROM_END = ROM_START + ROM_SIZE - 1
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# this PTR bootstrap from "Loading The PDS-1" (loading.pdf)
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PTR_ROM_IMAGE = [ # org 040
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0060077, # start lac base ;40 get load address
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0020010, # dac 010 ;41 put into auto-inc reg
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0104076, # lwc 076 ;42 -0100+1 into AC
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0020020, # dac 020 ;43 put into memory
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0001061, # hon ;44 start PTR
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0100011, # wait cal ;45 clear AC+LINK
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0002400, # hsf ;46 skip if PTR has data
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0010046, # jmp .-1 ;47 wait until is data
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0001051, # hrb ;50 read PTR -> AC
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0074075, # sam what ;51 skip if AC == 2
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0010045, # jmp wait ;52 wait until PTR return 0
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0002400, # loop hsf ;53 skip if PTR has data
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0010053, # jmp .-1 ;54 wait until is data
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0001051, # hrb ;55 read PTR -> AC
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0003003, # ral 3 ;56 move byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0102400, # hsn ;61 wait until PTR moves
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0010061, # jmp .-1 ;62
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0002400, # hsf ;63 skip if PTR has data
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0010063, # jmp .-1 ;64 wait until is data
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0001051, # hrb ;65 read PTR -> AC
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0120010, # dac *010 ;66 store word, inc pointer
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0102400, # hsn ;67 wait until PTR moves
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0010067, # jmp .-1 ;70
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0100011, # cal ;71 clear AC & LINK
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0030020, # isz 020 ;72 inc mem and skip zero
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0010053, # jmp loop ;73 if not finished, jump
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0110076, # jmp *go ;74 execute loader
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0000002, # what data 2 ;75
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0003700, # go data 03700 ;76
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0003677, # base data 03677 ;77
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]
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TTY_ROM_IMAGE_TEST = [
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#00040 0001: org 040
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0100001, #00040 0002: loop cla ; clear AC
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0001031, #00041 0003: rrb ; IOR tty input -> AC
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0010040, #00042 0004: jmp loop ; keep going
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# 0005: end
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]
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# TTY ROM image from "Loading The PDS-1" (loading.pdf)
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TTY_ROM_IMAGE = [ # org 040
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0060077, # start lac base ;40 get load address
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0020010, # dac 10 ;41 put into auto-inc reg
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0104076, # lwc 076 ;42 -076 into AC (loader size)
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0020020, # dac 20 ;43 put into memory
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0001032, # rcf ;44 clear TTY flag
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0100011, # wait cal ;45 clear AC+LINK
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0002040, # rsf ;46 skip if TTY has data
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0010046, # jmp .-1 ;47 wait until there is data
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0001031, # rrb ;50 read TTY -> AC
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#0001033, # rrc ;50 read TTY -> AC, clear TTY flag
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0074075, # sam 75 ;51 first non-zero must be 02
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0010044, # jmp 044 ;52 wait until TTY return == 02
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0002040, # loop rsf ;53 skip if TTY has data
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0010053, # jmp .-1 ;54 wait until there is data
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0001033, # rrc ;55 read TTY -> AC, clear TTY flag
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0003003, # ral 3 ;56 move TTY byte into high AC
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0003003, # ral 3 ;57
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0003002, # ral 2 ;60
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0002040, # rsf ;61 wait until there is data
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0010061, # jmp .-1 ;62
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0001033, # rrc ;63 read TTY -> AC, clear flag
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0120010, # dac *10 ;64 store word, inc pointer
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0100011, # cal ;65 clear AC & LINK
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0030020, # isz 20 ;66 inc mem and skip if zero
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0010053, # jmp loop ;67 if not finished, next word
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0110076, # jmp *go ;70 else execute block loader
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0000000, # data 0 ;71
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0000000, # data 0 ;72
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0000000, # data 0 ;73
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0000000, # data 0 ;74
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0000002, # data 2 ;75
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#0037700, # go word 037700 ;76 block loader base address
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0003700, # go word 003700 ;76 block loader base address
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#0037677 # base word 037677 ;77 init value for 010 auto inc
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0003677 # base word 003677 ;77 init value for 010 auto inc
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]
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# class instance variables
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corefile = None
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memory = []
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using_rom = True
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boot_rom = None
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rom_protected = False
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def __init__(self, boot_rom=None, core=None):
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""" """
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self.corefile = core
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self.boot_rom = boot_rom
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self.memory = [0]*MEMORY_SIZE
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self.using_rom = boot_rom in [ROM_PTR, ROM_TTY]
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self.rom_protected = self.using_rom
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if self.corefile:
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try:
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self.loadcore(self.corefile)
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except IOError:
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self.clear_core()
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else:
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self.clear_core()
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self.set_ROM(self.boot_rom)
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def set_corefile(self, corefile):
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"""Set name of the core save/restore file."""
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self.corefile = corefile
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def clear_core(self):
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"""Clears memory to all zeros.
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If using ROM, that is unchanged.
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"""
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for address in range(MEMORY_SIZE):
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if not self.rom_protected or not (self.ROM_START <= address <= self.ROM_END):
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self.memory[address] = 0
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def loadcore(self, filename=None):
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"""Load core from a file. Read 16 bit values as big-endian."""
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if not filename:
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filename = self.corefile
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self.memory = []
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try:
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with open(filename, 'rb') as fd:
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while True:
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high = fd.read(1)
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if high == '':
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break
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low = fd.read(1)
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val = (ord(high) << 8) + ord(low)
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self.memory.append(val)
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except struct.error:
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raise RuntimeError('Core file %s is corrupt!' % filename)
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def savecore(self, filename=None):
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"""Save core in a file. Write 16 bit values big-endian."""
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if not filename:
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filename = self.corefile
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with open(filename, 'wb') as fd:
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for val in self.memory:
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high = val >> 8
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low = val & 0xff
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fd.write(chr(high))
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fd.write(chr(low))
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def set_PTR_ROM(self):
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"""Set addresses 040 to 077 as PTR ROM."""
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log('seting PTR bootstrap into ROM')
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i = self.ROM_START
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for ptr_value in self.PTR_ROM_IMAGE:
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self.memory[i] = ptr_value
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i += 1
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def set_TTY_ROM(self):
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"""Set addresses 040 to 077 as TTY ROM."""
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log('seting TTY bootstrap into ROM')
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i = self.ROM_START
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for tty_value in self.TTY_ROM_IMAGE:
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#for tty_value in self.TTY_ROM_IMAGE_TEST:
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self.memory[i] = tty_value
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i += 1
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def set_ROM(self, romtype=None):
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"""Set ROM to either PTR or TTY, or disable ROM."""
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save_flag = self.rom_protected
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self.rom_protected = False
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if romtype == 'ptr':
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self.set_PTR_ROM()
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self.rom_protected = True
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elif romtype == 'tty':
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self.set_TTY_ROM()
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self.rom_protected = True
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else:
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self.rom_protected = save_flag
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def set_ROM_writable(self, writable):
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"""Set ROM write protection state."""
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self.rom_protected = writable
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def fetch(self, address, indirect):
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"""Get a value from a memory address.
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The read can be indirect, and may be through an
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auto-increment address.
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"""
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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address = MASK_MEM(address)
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# if indirect on auto-inc register, add one to it before use
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if ISAUTOINC(address):
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self.memory[address] += 1
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address = self.memory[MASK_MEM(address)]
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indirect = bool(address & 0100000)
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return self.memory[MASK_MEM(address)]
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def eff_address(self, address, indirect):
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"""Get an effective memory address.
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The address can be indirect, and may be through an
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auto-increment address.
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"""
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# the Imlac can get into infinite defer loops, and so can we!
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while indirect:
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if ISAUTOINC(address):
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# indirect on auto-inc register, add one to it before use
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self.memory[address] = MASK_MEM(self.memory[address] + 1)
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try:
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address = self.memory[address]
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except IndexError:
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# assume we are addressing out of memory limits
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msg = 'Bad memory address: %06o' % address
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raise IndexError(msg)
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indirect = bool(address & 0100000)
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return address
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def str_trace(self, msg=None):
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"""Get a traceback string."""
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import traceback
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result = []
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if msg:
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result.append(msg+'\n')
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result.extend(traceback.format_stack())
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return ''.join(result)
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def put(self, value, address, indirect):
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"""Put a value into a memory address.
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The store can be indirect, and may be through an
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auto-increment address.
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"""
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if indirect:
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address = self.memory[address] & ADDRMASK
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if self.rom_protected and self.ROM_START <= address <= self.ROM_END:
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print('Attempt to write to ROM address %07o' % address)
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Trace.comment('Attempt to write to ROM address %07o' % address)
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return
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try:
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self.memory[address] = MASK_16(value)
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except IndexError:
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raise RuntimeError('Bad address: %06o (max mem=%06o, ADDRMASK=%06o)'
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% (address, len(self.memory), ADDRMASK))
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def dump(self, low, high):
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"""Dump memory in range [low, high] inclusive to a file."""
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with open('x.dump', 'wb') as fd:
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for i in range(high - low + 1):
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val = self.fetch(low + i, False)
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high = val >> 8
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low = val & 0xff
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data = struct.pack('B', high)
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fd.write(data)
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data = struct.pack('B', low)
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fd.write(data)
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