mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
710 lines
25 KiB
Python
710 lines
25 KiB
Python
#!/usr/bin/python
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"""
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The Imlac main CPU.
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"""
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import sys
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from Globals import *
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import Trace
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import log
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log = log.Log('test.log', log.Log.DEBUG)
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trace = Trace.Trace(TRACE_FILENAME)
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class MainCPU(object):
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######
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# The main CPU registers
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######
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PC = None # main CPU program counter
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L = 0 # main CPU link register
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AC = 0 # main CPU accumulator
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Sync40Hz = 1 # main CPU 40Hz flag register
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DS = 0 # dataswitches value
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# address of base of local code block
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BlockBase = 0
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# decode dictionaries (initialized in __init__())
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main_decode = None
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page_00_decode = None
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page02_decode = None
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micro_opcodes = None
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micro_singles = None
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# module-level state variables
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running = False # True if CPU running
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def __init__(self, memory, display, displaycpu, kbd, ttyin, ttyout, ptrptp):
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"""Initialize the main CPU."""
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self.memory = memory
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self.display = display
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self.displaycpu = displaycpu
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self.kbd = kbd
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self.ttyin = ttyin
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self.ttyout = ttyout
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self.ptrptp = ptrptp
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# main dispatch dictionary for decoding opcodes in bits 1-4
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self.main_decode = {000: self.page_00, # secondary decode
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001: self.i_LAW_LWC,
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002: self.i_JMP,
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# 003: self.illegal,
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004: self.i_DAC,
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005: self.i_XAM,
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006: self.i_ISZ,
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007: self.i_JMS,
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# 010: self.illegal
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011: self.i_AND,
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012: self.i_IOR,
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013: self.i_XOR,
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014: self.i_LAC,
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015: self.i_ADD,
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016: self.i_SUB,
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017: self.i_SAM}
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# page_00 dispatch dictionary for decoding opcodes
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# HLT may be handled specially
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self.page_00_decode = {001003: self.i_DLA,
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001011: self.i_CTB,
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001012: self.i_DOF,
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001021: self.i_KRB,
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001022: self.i_KCF,
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001023: self.i_KRC,
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001031: self.i_RRB,
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001032: self.i_RCF,
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001033: self.i_RRC,
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001041: self.i_TPR,
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001042: self.i_TCF,
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001043: self.i_TPC,
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001051: self.i_HRB,
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001052: self.i_HOF,
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001061: self.i_HON,
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001062: self.i_STB,
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001071: self.i_SCF,
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001072: self.i_IOS,
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001101: self.i_IOT101,
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001111: self.i_IOT111,
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001131: self.i_IOT131,
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001132: self.i_IOT132,
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001134: self.i_IOT134,
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001141: self.i_IOT141,
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001161: self.i_IOF,
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001162: self.i_ION,
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001271: self.i_PPC,
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001274: self.i_PSF,
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# 003000: self.illegal RAL0
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003001: self.i_RAL1,
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003002: self.i_RAL2,
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003003: self.i_RAL3,
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# 003020: self.illegal RAR0,
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003021: self.i_RAR1,
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003022: self.i_RAR2,
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003023: self.i_RAR3,
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# 003040: self.illegal SAL0,
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003041: self.i_SAL1,
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003042: self.i_SAL2,
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003043: self.i_SAL3,
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# 003060: self.illegal SAR0,
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003061: self.i_SAR1,
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003062: self.i_SAR2,
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003063: self.i_SAR3,
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003100: self.i_DON}
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self.page02_decode = {0002001: self.i_ASZ,
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0102001: self.i_ASN,
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0002002: self.i_ASP,
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0102002: self.i_ASM,
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0002004: self.i_LSZ,
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0102004: self.i_LSN,
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0002010: self.i_DSF,
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0102010: self.i_DSN,
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0002020: self.i_KSF,
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0102020: self.i_KSN,
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0002040: self.i_RSF,
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0102040: self.i_RSN,
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0002100: self.i_TSF,
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0102100: self.i_TSN,
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0002200: self.i_SSF,
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0102200: self.i_SSN,
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0002400: self.i_HSF,
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0102400: self.i_HSN}
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self.micro_opcodes = {0100000: 'NOP',
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0100001: 'CLA',
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0100002: 'CMA',
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0100003: 'STA',
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0100004: 'IAC',
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0100005: 'COA',
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0100006: 'CIA',
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0100010: 'CLL',
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0100011: 'CAL',
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0100020: 'CML',
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0100030: 'STL',
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0100040: 'ODA',
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0100041: 'LDA'}
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self.micro_singles = {0100001: 'CLA',
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0100002: 'CMA',
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0100004: 'IAC',
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0100010: 'CLL',
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0100020: 'CML',
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0100040: 'ODA'}
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self.running = False
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def set_dataswitches(self, value):
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"""Set given value into the data switches."""
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self.DS = value
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def BLOCKADDR(self, address):
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"""Get address WITHIN THE BLOCK."""
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return self.BlockBase | address
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def execute_one_instruction(self):
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"""Execute one MAIN instruction, return # cycles and a trace string."""
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if not self.running:
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return (0, None)
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# get instruction word to execute, advance PC
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self.dot = self.PC
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instruction = self.memory.fetch(self.dot, False)
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self.BlockBase = self.PC & ADDRHIGHMASK
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self.PC = MASK_MEM(self.PC + 1)
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# get instruction opcode, indirect bit and address
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opcode = (instruction >> 11) & 017
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indirect = bool(instruction & 0100000)
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address = (instruction & 03777)
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return self.main_decode.get(opcode, self.illegal)(indirect,
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address,
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instruction)
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def illegal(self, indirect, address, instruction):
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"""Handle an illegal instruction."""
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if instruction:
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msg = ('Illegal instruction (%6.6o) at address %6.6o'
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% (instruction, self.PC-1))
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else:
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msg = 'Illegal instruction at address %6.6o' % (PC-1)
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raise RuntimeError(msg)
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def page_00(self, indirect, address, instruction):
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if (instruction & 0077700) == 000000:
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return self.microcode(instruction)
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elif (instruction & 0077000) == 002000:
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return self.page02_decode.get(instruction, self.illegal)()
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return self.page_00_decode.get(instruction, self.illegal)(indirect,
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address,
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instruction)
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def i_LAW_LWC(self, indirect, address, instruction):
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tracestr = None
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if indirect:
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self.AC = (~address+1) & WORDMASK
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tracestr = trace.itrace(self.dot, 'LWC', False, address)
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else:
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self.AC = address
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tracestr = trace.itrace(self.dot, 'LAW', False, address)
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return (1, tracestr)
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def i_JMP(self, indirect, address, instruction):
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eff_address = self.memory.eff_address(address, indirect)
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self.PC = eff_address & PCMASK
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tracestr = trace.itrace(self.dot, 'JMP', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_DAC(self, indirect, address, instruction):
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eff_address = self.memory.eff_address(address, indirect)
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self.memory.put(self.AC, eff_address, False)
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tracestr = trace.itrace(self.dot, 'DAC', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_XAM(self, indirect, address, instruction):
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eff_address = self.memory.eff_address(address, indirect)
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tmp = self.memory.fetch(eff_address, False)
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self.memory.put(self.AC, eff_address, False)
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self.AC = tmp
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tracestr = trace.itrace(self.dot, 'XAM', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_ISZ(self, indirect, address, instruction):
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eff_address = self.memory.eff_address(address, indirect)
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value = (self.memory.fetch(eff_address, False) + 1) & WORDMASK
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self.memory.put(value, eff_address, False)
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if value == 0:
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self.PC = (self.PC + 1) & WORDMASK
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tracestr = trace.itrace(self.dot, 'ISZ', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_JMS(self, indirect, address, instruction):
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eff_address = self.memory.eff_address(address, indirect)
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self.memory.put(self.PC, eff_address, False)
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self.PC = (eff_address + 1) & PCMASK
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tracestr = trace.itrace(self.dot, 'JMS', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_AND(self, indirect, address, instruction):
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self.AC &= self.memory.fetch(address, indirect)
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tracestr = trace.itrace(self.dot, 'AND', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_IOR(self, indirect, address, instruction):
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self.AC |= self.memory.fetch(address, indirect)
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tracestr = trace.itrace(self.dot, 'IOR', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_XOR(self, indirect, address, instruction):
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self.AC ^= self.memory.fetch(address, indirect)
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tracestr = trace.itrace(self.dot, 'XOR', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_LAC(self, indirect, address, instruction):
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self.AC = self.memory.fetch(address, indirect)
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tracestr = trace.itrace(self.dot, 'LAC', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_ADD(self, indirect, address, instruction):
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self.AC += self.memory.fetch(self.BLOCKADDR(address), indirect)
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if self.AC & OVERFLOWMASK:
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self.L = 0 if self.L else 1
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self.AC &= WORDMASK
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tracestr = trace.itrace(self.dot, 'ADD', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_SUB(self, indirect, address, instruction):
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addit = self.memory.fetch(self.BLOCKADDR(address), indirect)
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addit = (~addit + 1) & WORDMASK
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self.AC += addit
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if self.AC & OVERFLOWMASK:
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self.L = 0 if self.L else 1
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self.AC &= WORDMASK
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tracestr = trace.itrace(self.dot, 'SUB', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def i_SAM(self, indirect, address, instruction):
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samaddr = self.BLOCKADDR(address)
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if self.AC == self.memory.fetch(samaddr, indirect):
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self.PC = (self.PC + 1) & PCMASK
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tracestr = trace.itrace(self.dot, 'SAM', indirect, address)
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return (3, tracestr) if indirect else (2, tracestr)
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def microcode(self, instruction):
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# T1
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if instruction & 001:
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self.AC = 0
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if instruction & 010:
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self.L = 0
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# T2
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if instruction & 002:
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self.AC = (~self.AC) & WORDMASK
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if instruction & 020:
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self.L = 0 if self.L else 1
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# T3
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if instruction & 004:
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self.AC += 1
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if self.AC & OVERFLOWMASK:
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self.L = 0 if self.L else 1
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self.AC &= WORDMASK
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if instruction & 040:
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self.AC |= self.DS
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# do some sort of trace
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combine = []
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opcode = self.micro_opcodes.get(instruction, None)
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if opcode:
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combine.append(opcode)
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if not combine:
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# nothing so far, we have HLT or unknown microcode
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if not instruction & 0100000:
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# bit 0 is clear, it's HLT
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self.running = False
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combine.append('HLT')
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else:
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for (k, op) in self.micro_singles.items():
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if instruction & k:
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combine.append(op)
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tracestr = trace.itrace(self.dot, '+'.join(combine), False)
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return (1, tracestr)
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def i_DLA(self, indirect, address, instruction):
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#self.displaycpu.DPC = self.AC
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tracestr = trace.itrace(self.dot, 'DLA_X')
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return (1, tracestr)
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def i_CTB(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'CTB')
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return (1, tracestr)
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def i_DOF(self, indirect, address, instruction):
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#self.displaycpu.stop()
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tracestr = trace.itrace(self.dot, 'DOF_X')
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return (1, tracestr)
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def i_KRB(self, indirect, address, instruction):
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self.AC |= self.kbd.read()
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tracestr = trace.itrace(self.dot, 'KRB')
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return (1, tracestr)
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def i_KCF(self, indirect, address, instruction):
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self.kbd.clear()
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tracestr = trace.itrace(self.dot, 'KCF')
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return (1, tracestr)
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def i_KRC(self, indirect, address, instruction):
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self.AC |= self.kbd.read()
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self.kbd.clear()
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tracestr = trace.itrace(self.dot, 'KRC')
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return (1, tracestr)
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def i_RRB(self, indirect, address, instruction):
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self.AC |= self.ttyin.read()
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tracestr = trace.itrace(self.dot, 'RRB')
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return (1, tracestr)
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def i_RCF(self, indirect, address, instruction):
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self.ttyin.clear()
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tracestr = trace.itrace(self.dot, 'RCF')
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return (1, tracestr)
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def i_RRC(self, indirect, address, instruction):
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self.AC |= self.ttyin.read()
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self.ttyin.clear()
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tracestr = trace.itrace(self.dot, 'RRC')
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return (1, tracestr)
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def i_TPR(self, indirect, address, instruction):
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self.ttyout.write(self.AC & 0xff)
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tracestr = trace.itrace(self.dot, 'TPR')
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return (1, tracestr)
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def i_TCF(self, indirect, address, instruction):
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self.ttyout.clear()
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tracestr = trace.itrace(self.dot, 'TCF')
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return (1, tracestr)
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def i_TPC(self, indirect, address, instruction):
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self.ttyout.write(self.AC & 0xff)
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self.ttyout.clear()
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tracestr = trace.itrace(self.dot, 'TPC')
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return (1, tracestr)
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def i_HRB(self, indirect, address, instruction):
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self.AC |= self.ptrptp.read()
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tracestr = trace.itrace(self.dot, 'HRB')
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return (1, tracestr)
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def i_HOF(self, indirect, address, instruction):
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self.ptrptp.stop()
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tracestr = trace.itrace(self.dot, 'HOF')
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return (1, tracestr)
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def i_HON(self, indirect, address, instruction):
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self.ptrptp.start()
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tracestr = trace.itrace(self.dot, 'HON')
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return (1, tracestr)
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def i_STB(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'STB')
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return (1, tracestr)
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def i_SCF(self, indirect, address, instruction):
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self.Sync40Hz = 0
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tracestr = trace.itrace(self.dot, 'SCF')
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return (1, tracestr)
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def i_IOS(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOS')
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return (1, tracestr)
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def i_IOT101(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT101')
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return (1, tracestr)
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def i_IOT111(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT111')
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return (1, tracestr)
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def i_IOT131(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT131')
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return (1, tracestr)
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def i_IOT132(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT132')
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return (1, tracestr)
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def i_IOT134(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT134')
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return (1, tracestr)
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def i_IOT141(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOT141')
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return (1, tracestr)
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def i_IOF(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'IOF')
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return (1, tracestr)
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def i_ION(self, indirect, address, instruction):
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tracestr = trace.itrace(self.dot, 'ION')
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return (1, tracestr)
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def i_PPC(self, indirect, address, instruction):
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self.ptrptp.punch(self.AC & 0xff)
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tracestr = trace.itrace(self.dot, 'PPC')
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return (1, tracestr)
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def i_PSF(self, indirect, address, instruction):
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if self.ptrptp.ready():
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self.PC = (self.PC + 1) & WORDMASK
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tracestr = trace.itrace(self.dot, 'PSF')
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return (1, tracestr)
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def i_RAL1(self, indirect, address, instruction):
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAL', False, 1)
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return (1, tracestr)
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def i_RAL2(self, indirect, address, instruction):
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAL', False, 2)
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return (1, tracestr)
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def i_RAL3(self, indirect, address, instruction):
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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newl = self.AC >> 15
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newac = (self.AC << 1) | self.L
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAL', False, 3)
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return (1, tracestr)
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def i_RAR1(self, indirect, address, instruction):
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAR', False, 1)
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return (1, tracestr)
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def i_RAR2(self, indirect, address, instruction):
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAR', False, 2)
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return (1, tracestr)
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def i_RAR3(self, indirect, address, instruction):
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
|
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self.AC = newac & WORDMASK
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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newl = self.AC & 1
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newac = (self.AC >> 1) | (self.L << 15)
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self.L = newl
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self.AC = newac & WORDMASK
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tracestr = trace.itrace(self.dot, 'RAR', False, 3)
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return (1, tracestr)
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def i_SAL1(self, indirect, address, instruction):
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high_bit = self.AC & HIGHBITMASK
|
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value = self.AC & 037777
|
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self.AC = (value << 1) | high_bit
|
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tracestr = trace.itrace(self.dot, 'SAL', False, 1)
|
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return (1, tracestr)
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def i_SAL2(self, indirect, address, instruction):
|
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high_bit = self.AC & HIGHBITMASK
|
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value = self.AC & 017777
|
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self.AC = (value << 2) | high_bit
|
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tracestr = trace.itrace(self.dot, 'SAL', False, 2)
|
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return (1, tracestr)
|
|
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def i_SAL3(self, indirect, address, instruction):
|
|
high_bit = self.AC & HIGHBITMASK
|
|
value = self.AC & 007777
|
|
self.AC = (value << 3) | high_bit
|
|
tracestr = trace.itrace(self.dot, 'SAL', False, 3)
|
|
return (1, tracestr)
|
|
|
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def i_SAR1(self, indirect, address, instruction):
|
|
high_bit = self.AC & HIGHBITMASK
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
tracestr = trace.itrace(self.dot, 'SAR', False, 1)
|
|
return (1, tracestr)
|
|
|
|
def i_SAR2(self, indirect, address, instruction):
|
|
high_bit = self.AC & HIGHBITMASK
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
tracestr = trace.itrace(self.dot, 'SAR', False, 2)
|
|
return (1, tracestr)
|
|
|
|
def i_SAR3(self, indirect, address, instruction):
|
|
high_bit = self.AC & HIGHBITMASK
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
self.AC = (self.AC >> 1) | high_bit
|
|
tracestr = trace.itrace(self.dot, 'SAR', False, 3)
|
|
return (1, tracestr)
|
|
|
|
def i_DON(self, indirect, address, instruction):
|
|
#self.displaycpu.DRSindex = 0
|
|
#self.displaycpu.start()
|
|
tracestr = trace.itrace(self.dot, 'DON_X')
|
|
return (1, tracestr)
|
|
|
|
def i_ASZ(self):
|
|
if self.AC == 0:
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'ASZ')
|
|
return (1, tracestr)
|
|
|
|
def i_ASN(self):
|
|
if self.AC != 0:
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'ASN')
|
|
return (1, tracestr)
|
|
|
|
def i_ASP(self):
|
|
if not (self.AC & HIGHBITMASK):
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'ASP')
|
|
return (1, tracestr)
|
|
|
|
def i_ASM(self):
|
|
if (self.AC & HIGHBITMASK):
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'ASM')
|
|
return (1, tracestr)
|
|
|
|
def i_LSZ(self):
|
|
if self.L == 0:
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'LSZ')
|
|
return (1, tracestr)
|
|
|
|
def i_LSN(self):
|
|
if self.L != 0:
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'LSN')
|
|
return (1, tracestr)
|
|
|
|
def i_DSF(self):
|
|
# if self.displaycpu.ison():
|
|
# self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'DSF_X')
|
|
return (1, tracestr)
|
|
|
|
def i_DSN(self):
|
|
# if not self.displaycpu.ison():
|
|
# self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'DSN_X')
|
|
return (1, tracestr)
|
|
|
|
def i_KSF(self):
|
|
if self.kbd.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'KSF')
|
|
return (1, tracestr)
|
|
|
|
def i_KSN(self):
|
|
if not self.kbd.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'KSN')
|
|
return (1, tracestr)
|
|
|
|
def i_RSF(self):
|
|
if self.ttyin.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'RSF')
|
|
return (1, tracestr)
|
|
|
|
def i_RSN(self):
|
|
if not self.ttyin.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'RSN')
|
|
return (1, tracestr)
|
|
|
|
def i_TSF(self):
|
|
if self.ttyout.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'TSF')
|
|
return (1, tracestr)
|
|
|
|
def i_TSN(self):
|
|
if not self.ttyout.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'TSN')
|
|
return (1, tracestr)
|
|
|
|
def i_SSF(self):
|
|
if self.display.ready(): # skip if 40Hz sync on
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'SSF')
|
|
return (1, tracestr)
|
|
|
|
def i_SSN(self):
|
|
if not self.display.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'SSN')
|
|
return (1, tracestr)
|
|
|
|
def i_HSF(self):
|
|
if self.ptrptp.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'HSF')
|
|
return (1, tracestr)
|
|
|
|
def i_HSN(self):
|
|
if not self.ptrptp.ready():
|
|
self.PC = (self.PC + 1) & WORDMASK
|
|
tracestr = trace.itrace(self.dot, 'HSN')
|
|
return (1, tracestr)
|
|
|