mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
444 lines
18 KiB
Python
444 lines
18 KiB
Python
#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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"""
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Test pymlac opcode DIRECTLY.
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Put opcodes into memory along with required memory values.
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Put L and AC values into registers.
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Execute opcode, test result.
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We DON'T try to load from papertape, use core files, etc.
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"""
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import unittest
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import MainCPU
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import Memory
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import Trace
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class TestPymlac(unittest.TestCase):
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def test_LAW(self):
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Trace.init('test_LAW.trace')
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Trace.settrace(True)
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Memory.init()
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# test "LAW 0"
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Memory.memory[0100] = 004000 # LAW 0
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"LAW 0" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LAW 0" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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Memory.memory[0100] = 004000 # LAW 0
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"LAW 0" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LAW 0" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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# test "LAW 0377"
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Memory.memory[0100] = 004377 # LAW 0377
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0377" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0377" left AC containing %06o, should be 0377' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0377, msg)
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msg = '"LAW 0377" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LAW 0377" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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Memory.memory[0100] = 004377 # LAW 0377
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LAW 0377" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LAW 0377" left AC containing %06o, should be 0377' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0377, msg)
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msg = '"LAW 0377" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LAW 0377" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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def test_LWC(self):
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Trace.init('test_LWC.trace')
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Trace.settrace(True)
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Memory.init()
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# test "LWC 0"
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Memory.memory[0100] = 0104000 # LWC 0
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 0" left AC containing %06o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"LWC 0" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LWC 0" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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Memory.memory[0100] = 0104000 # LWC 0
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 0" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 0" left AC containing %06o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"LWC 0" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LWC 0" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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# test "LWC 1"
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Memory.memory[0100] = 0104001 # LWC 1
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 1" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 1" left AC containing %06o, should be 0177776' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177776, msg)
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msg = '"LWC 1" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"LWC 1" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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Memory.memory[0100] = 0104001 # LWC 1
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MainCPU.AC = 012345
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MainCPU.L = 0
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"LWC 1" used %d cycles, should be 1' % cycles
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self.assertTrue(cycles == 1, msg)
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msg = '"LWC 1" left AC containing %06o, should be 0177776' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177776, msg)
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msg = '"LWC 1" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"LWC 1" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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def test_JMP(self):
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Trace.init('test_JMP.trace')
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Trace.settrace(True)
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Memory.init()
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# test "JMP 0100"
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Memory.memory[0100] = 0010100 # JMP 0100
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP 0100" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"JMP 0100" left AC containing %06o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP 0100" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"JMP 0100" modified PC to %06o, should be 0100' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0100, msg)
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# test "JMP 0110"
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Memory.memory[0100] = 0010110 # JMP 0110
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP 0110" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"JMP 0110" left AC containing %06o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP 0110" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"JMP 0110" modified PC to %06o, should be 0110' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0110, msg)
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# test "JMP *0110"
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Memory.memory[0100] = 0110110 # JMP *0110
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Memory.memory[0110] = 0120 # where next PC should be
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MainCPU.init()
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MainCPU.AC = 012345
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"JMP *0110" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"JMP *0110" left AC containing %06o, should be 012345' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 012345, msg)
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msg = '"JMP *0110" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"JMP *0110" modified PC to %06o, should be 0120' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0120, msg)
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def test_DAC(self):
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Trace.init('test_DAC.trace')
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Trace.settrace(True)
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Memory.init()
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# test "DAC 0101"
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Memory.memory[0100] = 0020101 # DAC 0101
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Memory.memory[0101] = 0 # value we are storing over
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MainCPU.init()
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MainCPU.AC = 1
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"DAC 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"DAC 0101" left AC containing %06o, should be 1' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 1, msg)
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msg = '"DAC 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"DAC 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"DAC 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
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self.assertTrue(Memory.memory[0101] == 1, msg)
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# test "DAC *0101"
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Memory.memory[0100] = 0120101 # DAC *0101
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Memory.memory[0101] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"DAC *0101" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"DAC *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"DAC *0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"DAC *0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"DAC *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 0177777, msg)
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def test_XAM(self):
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Trace.init('test_XAM.trace')
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Trace.settrace(True)
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Memory.init()
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# test "XAM 0101"
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Memory.memory[0100] = 0024101 # XAM 0101
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Memory.memory[0101] = 0 # value we are exchanging
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MainCPU.init()
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MainCPU.AC = 2
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"XAM 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"XAM 0101" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"XAM 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"XAM 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"XAM 0101" modified memory[0101] to %06o, should be 2' % Memory.memory[0101]
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self.assertTrue(Memory.memory[0101] == 2, msg)
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# test "XAM *0101"
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Memory.memory[0100] = 0124101 # XAM *0101
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Memory.memory[0101] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"XAM *0101" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"XAM *0101" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"XAM *0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"XAM *0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"XAM *0101" modified memory[0102] to %06o, should be 0177777' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 0177777, msg)
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def test_ISZ(self):
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Trace.init('test_ISZ.trace')
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Trace.settrace(True)
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Memory.init()
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# test "ISZ 0101"
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Memory.memory[0100] = 0024101 # ISZ 0101
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Memory.memory[0101] = 0 # value we are incrementing/testing
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MainCPU.init()
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MainCPU.AC = 2
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"ISZ 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"ISZ 0101" left AC containing %06o, should be 2' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 2, msg)
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msg = '"ISZ 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"ISZ 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"ISZ 0101" modified memory[0101] to %06o, should be 1' % Memory.memory[0101]
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self.assertTrue(Memory.memory[0101] == 1, msg)
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# test "ISZ *0101"
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Memory.memory[0100] = 0124101 # ISZ *0101
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Memory.memory[0101] = 0102 # address of cell we are storing into
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Memory.memory[0102] = 0
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"ISZ *0101" used %d cycles, should be 3' % cycles
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self.assertTrue(cycles == 3, msg)
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msg = '"ISZ *0101" left AC containing %06o, should be 0177777' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0177777, msg)
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msg = '"ISZ *0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"ISZ *0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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msg = '"ISZ *0101" modified memory[0102] to %06o, should be 1' % Memory.memory[0102]
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self.assertTrue(Memory.memory[0102] == 1, msg)
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def test_ADD(self):
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Trace.init('test_ADD.trace')
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Trace.settrace(True)
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Memory.init()
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# test "ADD 0101"
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Memory.memory[0100] = 0064101 # ADD 0101
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Memory.memory[0101] = 0 # value we are adding to PC
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MainCPU.init()
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MainCPU.AC = 0
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"ADD 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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# test "ADD 0101" add 1 to 0
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Memory.memory[0100] = 0064101 # ADD 0101
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Memory.memory[0101] = 1 # value we are adding to PC
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MainCPU.init()
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MainCPU.AC = 0
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"ADD 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"ADD 0101" left AC containing %06o, should be 1' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 1, msg)
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msg = '"ADD 0101" modified L to %01o, should be 1' % MainCPU.L
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self.assertTrue(MainCPU.L == 1, msg)
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msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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# test "ADD 0101" add 1 to 0177777, L=1 before
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Memory.memory[0100] = 0064101 # ADD 0101
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Memory.memory[0101] = 1 # value we are adding to PC
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MainCPU.init()
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MainCPU.AC = 0177777
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MainCPU.L = 1
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MainCPU.PC = 0100
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MainCPU.running = True
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cycles = MainCPU.execute_one_instruction()
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Trace.itraceend(False)
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msg = '"ADD 0101" used %d cycles, should be 2' % cycles
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self.assertTrue(cycles == 2, msg)
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msg = '"ADD 0101" left AC containing %06o, should be 0' % MainCPU.AC
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self.assertTrue(MainCPU.AC == 0, msg)
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msg = '"ADD 0101" modified L to %01o, should be 0' % MainCPU.L
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self.assertTrue(MainCPU.L == 0, msg)
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msg = '"ADD 0101" modified PC to %06o, should be 0101' % MainCPU.PC
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self.assertTrue(MainCPU.PC== 0101, msg)
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################################################################################
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if __name__ == '__main__':
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suite = unittest.makeSuite(TestPymlac, 'test')
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runner = unittest.TextTestRunner()
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runner.run(suite)
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