SDS Diagnostics, using the SDS 930/940 Master Diagnostic Tape image (D930X4A.TAP)

Summary

930 0-16K Memory Test			passed
930 16K-32K Memory Test			passed
930 Instruction Test			passed
930 P&S Register Test			passed

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930 0-16K Memory Test

sim> att mt diag.tap
sim> d a 1
sim> d bpt4 1				; stop every 1/2 cycle
sim> boot mt

HALT instruction, P: 00050 (STA 122,4)
sim> ex a
A:	00000000			; error count
sim> c

HALT instruction, P: 37650 (STA 37722,4)

sim> ex a
A:	00000000			; error count

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930 16K-32K Memory Test

sim> att mt diag.tap
sim> d a 2
sim> d bpt4 2				; stop every 1/2 cycle
sim> boot mt


HALT instruction, P: 00050 (STA 6)
sim> ex a
A:      00000000			; error count
sim> c

HALT instruction, P: 37650 (STA 37406)
sim> ex a
A:      00000000			; error count
sim> c

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930 Instruction Diagnostic

sim> att mt diag.tap
sim> d a 3
sim> br 17				; catch start of diagnostic
sim> boot mt

Breakpoint, P: 00017 (BRR 12,2)
sim> nobr 17
sim> br 112				; catch end of diagnostic
sim> c

Breakpoint, P: 00112 (BRU 3)

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930 P&S Register Test

sim> att mt diag.tap
sim> d a 4
sim> br 60				; catch end of pass
sim> boot mt

Breakpoint, P: 00060 (BRU 22)

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Bugs

1.  IO: Channel WAR not cleared after memory store
2.  IO: dev_map should contain _flags, not _v_flags
3.  SYS: Errors in system tables
4.  SYS: Character conversion table had 0 (space) as illegal, should be -1
5.  IO: Channel CPW calculation wrong for 12b mode
6.  RAD, DSK, MT: Instruction masks wrong for RAD, DSK, MT
7.  IO: Missing subscripts in dev_disp references
8.  RAD: typos referencing DSK
9.  IO: SKS 3 call incorrect
10. DRM: Drum track mask width incorrect
11. CPU: Memory management trap left reason in bogus state, stopped simulator
12. CPU: Interrupts require api_lvl as well as api_lvlhi, like PDP-10, PDP-15
13. CPU: Bug in find interrupt request
14. CPU: Interrupt priority scheme recoded for left to right priority
15. CPU: overflow test coded backwards
16. CPU: Rotates operate mod 48, not with upper limit of 48 (manual incorrect)
17. CPU: RSH not handling >= 48 correctly
18. CPU: CNA is 2's complement not 1's complement
19. CPU: MUL failed to mask cross product correctly
20. CPU: EM2, EM3 test using wrong 'channel'
21. CPU: EM3 test tested EM2 instead
22. CPU: POP must save EM2, EM3 like BRM (manual incorrect)
23. CPU: Shifts need special EA calculation, direct cycles using 9b indexing
24. CPU: Shifts ignore addr<13:14>
25. CPU: Diagnostic uses undefined shift 'normalize cyclic'
26. CPU: Divide 2'c complement of AB leaves B<23> unchanged
27. CPU: Divide overflow test requires special cases for divd.h == divr
28. CPU: Divide uses non-restoring algorithm
29. CPU: Channel terminate output must be deferred until channel buffer clears
30. CPU: Channel terminate output to magtape is convert to scan, must be
    handled in channel logic
31. SYS: duplicate entries for shifts
32. SYS: mask for shifts did not include indirect flag
33. MUX: Genie/SDS use inverted meanings for line enable flag
34. MT: missing fseek before write eof
35. MT: displayed characters only 7b wide instead of 8b
36. CPU: EOD 20000 used by diagnostic (EM change is NOP)
37. CPU: SKD sets all 24b of X, not just exponent
38. CPU: reset should not clear A, B, X
