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PDP11, VAX: MUX input rate limiting works correctly with input arriving on multiple lines concurrently.

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This commit is contained in:
Mark Pizzolato
2015-11-28 12:49:54 -08:00
parent d66b5a4671
commit 0938d31e59
10 changed files with 89 additions and 20 deletions
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9
PDP11/pdp11_dc.c
View File

@@ -290,7 +290,9 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
case 01: /* dci buf */
dci_clr_int (ln);
*data = dci_buf[ln];
sim_activate_after_abs (&dci_unit, dci_unit.wait);
/* Rechedule the next poll preceisely so that
the programmed input speed is observed. */
sim_clock_coschedule_abs (&dci_unit, tmxr_poll);
return SCPE_OK;
case 02: /* dco csr */
@@ -387,7 +389,6 @@ int32 ln, c, temp;
if ((uptr->flags & UNIT_ATT) == 0) /* attached? */
return SCPE_OK;
sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
ln = tmxr_poll_conn (&dcx_desc); /* look for connect */
if (ln >= 0) { /* got one? */
dcx_ldsc[ln].rcve = 1; /* set rcv enb */
@@ -432,7 +433,7 @@ for (ln = 0; ln < DCX_LINES; ln++) { /* loop thru lines */
dco_csr[ln] &= ~DCOCSR_CTS;
}
}
return SCPE_OK;
return sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
}
/* Terminal output service */
@@ -531,7 +532,7 @@ int32 ln;
dcx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
sim_cancel (&dci_unit); /* assume stop */
if (dci_unit.flags & UNIT_ATT) /* if attached, */
sim_activate (&dci_unit, tmxr_poll); /* activate */
sim_clock_coschedule (&dci_unit, tmxr_poll); /* activate */
for (ln = 0; ln < DCX_LINES; ln++) /* for all lines */
dcx_reset_ln (ln);
return auto_config (dci_dev.name, dcx_desc.lines); /* auto config */

10
PDP11/pdp11_dl.c
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@@ -272,7 +272,9 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
*data = dli_buf[ln] & DLIBUF_RD;
dli_csr[ln] &= ~CSR_DONE; /* clr rcv done */
dli_clr_int (ln, DLI_RCI); /* clr rcv int req */
sim_activate_after_abs (&dli_unit, dli_unit.wait);
/* Rechedule the next poll preceisely so that
the programmed input speed is observed. */
sim_clock_coschedule_abs (&dli_unit, tmxr_poll);
break;
case 02: /* tto csr */
@@ -377,7 +379,6 @@ sim_debug(DBG_TRC, &dli_dev, "dli_svc()\n");
if ((uptr->flags & UNIT_ATT) == 0) /* attached? */
return SCPE_OK;
sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
ln = tmxr_poll_conn (&dlx_desc); /* look for connect */
if (ln >= 0) { /* got one? rcv enb */
dlx_ldsc[ln].rcve = 1;
@@ -418,7 +419,8 @@ for (ln = 0; ln < DLX_LINES; ln++) { /* loop thru lines */
/* clr CDT,RNG,CTS */
}
}
return SCPE_OK;
return sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
}
/* Terminal output service */
@@ -532,7 +534,7 @@ sim_debug(DBG_TRC, dptr, "dlx_reset()\n");
dlx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
sim_cancel (&dli_unit); /* assume stop */
if (dli_unit.flags & UNIT_ATT) /* if attached, */
sim_activate (&dli_unit, tmxr_poll); /* activate */
sim_clock_coschedule (&dli_unit, tmxr_poll); /* activate */
for (ln = 0; ln < DLX_LINES; ln++) /* for all lines */
dlx_reset_ln (ln);
return auto_config (dli_dev.name, dlx_desc.lines); /* auto config */

4
PDP11/pdp11_dz.c
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@@ -392,9 +392,9 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
tmxr_poll_rx (&dz_desc); /* poll input */
dz_update_rcvi (); /* update rx intr */
if (dz_rbuf[dz]) {
/* Schedule the next poll somewhat preceisely so that
/* Rechedule the next poll preceisely so that
the programmed input speed is observed. */
sim_activate_after_abs (&dz_unit, dz_ldsc[(dz * DZ_LINES) + (dz_rbuf[dz]>>RBUF_V_RLINE) & 07].rxdelta + dz_wait);
sim_clock_coschedule_abs (&dz_unit, tmxr_poll);
}
}
else {

4
PDP11/pdp11_vh.c
View File

@@ -681,9 +681,9 @@ static int32 fifo_get ( int32 vh )
}
}
}
/* Schedule the next poll somewhat preceisely so that the
/* Reschedule the next poll preceisely so that the
programmed input speed is observed. */
sim_activate_after_abs (&vh_unit[0], vh_parm[(vh * VH_LINES) + RBUF_GETLINE(data)].tmln->rxdelta + vh_wait);
sim_clock_coschedule_abs (&vh_unit[0], tmxr_poll);
return (data & 0177777);
}
/* TX Q manipulation */