mirror of
https://github.com/simh/simh.git
synced 2026-01-26 04:01:38 +00:00
Notes For V3.3-2
1. New Features in 3.3-2 1.1 SCP and Libraries - Added ASSERT command (from Dave Bryan) 1.2 PDP-11, VAX - Added RA60, RA71, RA81 disks 2. Bugs Fixed in 3.3-2 2.1 H316 - Fixed IORETURN macro - PT: fixed bug in OCP '0001 (found by Philipp Hachtmann) - MT: fixed error reporting from OCP (found by Philipp Hachtmann) 2.2 Interdata 32b - Fixed branches to mask new PC (from Greg Johnson) 2.3 PDP-11 - Fixed bugs in RESET for 11/70 (reported by Tim Chapman) - Fixed bug in SHOW MODEL (from Sergey Okhapkin) - Made SYSID variable for 11/70 (from Tim Chapman) - Fixed MBRK write case for 11/70 (from Tim Chapman) - RY: fixed bug in boot code (reported by Graham Toal) 2.4 VAX - Fixed initial state of cpu_extmem 2.5 HP2100 (from Dave Bryan) - Fixed missing MPCK on JRS target - Removed EXECUTE instruction (is NOP in actual microcode) - Fixed missing negative overflow renorm in StoreFP 2.6 I1401 - Fixed bug in line printer write line (reported by Van Snyder)
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
9b5c8c9711
commit
098200a126
@@ -1,6 +1,6 @@
|
||||
/* pdp11_cpu.c: PDP-11 CPU simulator
|
||||
|
||||
Copyright (c) 1993-2004, Robert M Supnik
|
||||
Copyright (c) 1993-2005, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
cpu PDP-11 CPU
|
||||
|
||||
19-Jan-05 RMS Fixed bug(s) in RESET for 11/70 (reported by Tim Chapman)
|
||||
22-Dec-04 RMS Fixed WAIT to work in all modes (from John Dundas)
|
||||
02-Oct-04 RMS Added model emulation
|
||||
25-Jan-04 RMS Removed local debug logging support
|
||||
@@ -796,11 +797,12 @@ case 000:
|
||||
break;
|
||||
case 5: /* RESET */
|
||||
if (cm == MD_KER) {
|
||||
reset_all (1);
|
||||
PIRQ = 0;
|
||||
reset_all (2); /* skip CPU, sys reg */
|
||||
PIRQ = 0; /* clear PIRQ, STKLIM, */
|
||||
STKLIM = 0; /* MMR0<15:12,0>, */
|
||||
for (i = 0; i < IPL_HLVL; i++) int_req[i] = 0;
|
||||
MMR0 = MMR0 & ~(MMR0_MME | MMR0_FREEZE);
|
||||
MMR3 = 0;
|
||||
MMR3 = 0; /* MMR3 */
|
||||
trap_req = trap_req & ~TRAP_INT;
|
||||
dsenable = calc_ds (cm); }
|
||||
break;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp11_cpumod.c: PDP-11 CPU model-specific features
|
||||
|
||||
Copyright (c) 2004, Robert M Supnik
|
||||
Copyright (c) 2004-2005, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,9 @@
|
||||
|
||||
system PDP-11 model-specific registers
|
||||
|
||||
15-Feb-05 RMS Fixed bug in SHOW MODEL (from Sergey Okhapkin)
|
||||
19-Jan-05 RMS Added variable SYSID, MBRK write (from Tim Chapman)
|
||||
|
||||
This module includes CPU- and system-specific registers, such as the Unibus
|
||||
map and control registers on 22b Unibus systems, the board registers for the
|
||||
F11- and J11-based systems, and the system registers for the PDP-11/44,
|
||||
@@ -51,6 +54,7 @@
|
||||
int32 SR = 0; /* switch register */
|
||||
int32 DR = 0; /* display register */
|
||||
int32 MBRK = 0; /* 11/70 microbreak */
|
||||
int32 SYSID = 0x1234; /* 11/70 system ID */
|
||||
int32 CPUERR = 0; /* CPU error reg */
|
||||
int32 MEMERR = 0; /* memory error reg */
|
||||
int32 CCR = 0; /* cache control reg */
|
||||
@@ -249,6 +253,7 @@ REG sys_reg[] = {
|
||||
{ ORDATA (HITMISS, HITMISS, 16) },
|
||||
{ ORDATA (CPUERR, CPUERR, 16) },
|
||||
{ ORDATA (MBRK, MBRK, 16) },
|
||||
{ ORDATA (SYSID, SYSID, 16) },
|
||||
{ ORDATA (JCSR, JCSR, 16) },
|
||||
{ ORDATA (JPCR, JPCR, 16) },
|
||||
{ ORDATA (JASR, JASR, 16) },
|
||||
@@ -477,7 +482,7 @@ case 010: /* lower size */
|
||||
*data = (MEMSIZE >> 6) - 1;
|
||||
return SCPE_OK;
|
||||
case 012: /* system ID */
|
||||
*data = 0x1234;
|
||||
*data = SYSID;
|
||||
return SCPE_OK;
|
||||
case 013: /* CPUERR */
|
||||
*data = CPUERR & CPUE_IMP;
|
||||
@@ -513,6 +518,9 @@ case 5: /* Hit/miss */
|
||||
case 013: /* CPUERR */
|
||||
CPUERR = 0;
|
||||
return SCPE_OK;
|
||||
case 014: /* MBRK */
|
||||
MBRK = data;
|
||||
return SCPE_OK;
|
||||
case 015: /* PIRQ */
|
||||
ODD_WO (data);
|
||||
put_PIRQ (data);
|
||||
@@ -876,12 +884,12 @@ return SCPE_OK;
|
||||
|
||||
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
uint32 i, std;
|
||||
uint32 i, all_opt;
|
||||
|
||||
fprintf (st, "%s", cpu_tab[cpu_model].name);
|
||||
std = cpu_tab[cpu_model].opt;
|
||||
for (i = 0; std && opt_name[i]; i = i++) {
|
||||
if ((std >> i) & 1) fprintf (st, ", %s",
|
||||
all_opt = cpu_tab[cpu_model].opt;
|
||||
for (i = 0; opt_name[2 * i] != NULL; i++) {
|
||||
if ((all_opt >> i) & 1) fprintf (st, ", %s",
|
||||
((cpu_opt >> i) & 1)? opt_name[2 * i]: opt_name[(2 * i) + 1]);
|
||||
}
|
||||
return SCPE_OK;
|
||||
|
||||
@@ -1,14 +1,14 @@
|
||||
To: Users
|
||||
From: Bob Supnik
|
||||
Subj: PDP-11 Simulator Usage
|
||||
Date: 15-Nov-2004
|
||||
Date: 20-Jan-2005
|
||||
|
||||
COPYRIGHT NOTICE
|
||||
|
||||
The following copyright notice applies to both the SIMH source and binary:
|
||||
|
||||
Original code published in 1993-2004, written by Robert M Supnik
|
||||
Copyright (c) 1993-2004, Robert M Supnik
|
||||
Original code published in 1993-2005, written by Robert M Supnik
|
||||
Copyright (c) 1993-2005, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -328,6 +328,7 @@ The SYSTEM device implements registers that vary from system to system:
|
||||
11/83, 11/84, 11/93,
|
||||
11/94
|
||||
MBRK 11/45, 11/70 16 microbreak register
|
||||
SYSID 11/70 16 system ID (default = 1234 hex)
|
||||
JCSR 11/53, 11/73B, 11/83, 16 board control/status
|
||||
11/84, 11/93, 11/94
|
||||
JPCR 11/23+, 11/53, 11/73B, 16 page control register
|
||||
@@ -983,13 +984,15 @@ of many disk types:
|
||||
SET RQn RD53 set type to RD53
|
||||
SET RQn RD54 set type to RD54
|
||||
SET RQn RD31 set type to RD31
|
||||
SET RQn RA81 set type to RA81
|
||||
SET RQn RA82 set type to RA82
|
||||
set RQn RA71 set type to RA71
|
||||
SET RQn RA72 set type to RA72
|
||||
SET RQn RA90 set type to RA90
|
||||
SET RQn RA92 set type to RA92
|
||||
SET RQn RRD40 set type to RRD40 (CD ROM)
|
||||
SET RQn RAUSER{=n} set type to RA81 with n MB's
|
||||
SET -L RQn RAUSER{=n} set type to RA81 with n LBN's
|
||||
SET RQn RAUSER{=n} set type to RA82 with n MB's
|
||||
SET -L RQn RAUSER{=n} set type to RA82 with n LBN's
|
||||
|
||||
The type options can be used only when a unit is not attached to a file.
|
||||
RAUSER is a "user specified" disk; the user can specify the size of the
|
||||
|
||||
113
PDP11/pdp11_rq.c
113
PDP11/pdp11_rq.c
@@ -1,6 +1,6 @@
|
||||
/* pdp11_rq.c: MSCP disk controller simulator
|
||||
|
||||
Copyright (c) 2002-2004, Robert M Supnik
|
||||
Copyright (c) 2002-2005, Robert M Supnik
|
||||
Derived from work by Stephen F. Shirron
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -26,6 +26,7 @@
|
||||
|
||||
rq RQDX3 disk controller
|
||||
|
||||
17-Jan-05 RMS Added more RA and RD disks
|
||||
31-Oct-04 RMS Added -L switch (LBNs) to RAUSER size specification
|
||||
01-Oct-04 RMS Revised Unibus interface
|
||||
Changed to identify as UDA50 in Unibus configurations
|
||||
@@ -203,7 +204,7 @@ struct rqpkt {
|
||||
#define RCT_ENTB 128 /* entries/blk */
|
||||
#define RCT_END 0x80000000 /* marks RCT end */
|
||||
|
||||
/* The RQDX3 supports multiple disk drive types:
|
||||
/* The RQDX3 supports multiple disk drive types (x = not implemented):
|
||||
|
||||
type sec surf cyl tpg gpc RCT LBNs
|
||||
|
||||
@@ -212,17 +213,23 @@ struct rqpkt {
|
||||
RD51 18 4 306 4 1 36*4 21600
|
||||
RD31 17 4 615 4 1 3*8 41560
|
||||
RD52 17 8 512 8 1 4*8 60480
|
||||
x RD32 17 6 820 ? ? ? 83236
|
||||
x RD33 17 7 1170 ? ? ? 138565
|
||||
RD53 17 7 1024 7 1 5*8 138672
|
||||
RD54 17 15 1225 15 1 7*8 311200
|
||||
|
||||
The simulator also supports larger drives that only existed
|
||||
on SDI controllers. XBN, DBN, RCTS and RCTC are not known
|
||||
for the SDI drives and are not used by the simulator:
|
||||
on SDI controllers.
|
||||
|
||||
RA82 57 15 1435 15 1 ?*8 1216665
|
||||
RA72 51 20 1921? 20 1 ?*8 1953300
|
||||
RA90 69 13 2656 13 1 ?*8 2376153
|
||||
RA92 73 13 3101 13 1 ?*8 2940951
|
||||
RA60 42(+1) 6 1600 6 1 1008 400176
|
||||
x RA70 33(+1) 11 1507+ 11 1 ? 547041
|
||||
RA81 51(+1) 14 1258 14 1 2856 891072
|
||||
RA82 57(+1) 15 1435 15 1 3420 1216665
|
||||
RA71 51(+1) 14 1921 14 1 1428 1367310
|
||||
RA72 51(+1) 20 1921 20 1 2040 1953300
|
||||
RA90 69(+1) 13 2656 13 1 1794 2376153
|
||||
RA92 73(+1) 13 3101 13 1 949 2940951
|
||||
x RA73 70(+1) 21 2667+ 21 1 ? 3920490
|
||||
|
||||
Each drive can be a different type. The drive field in the
|
||||
unit flags specified the drive type and thus, indirectly,
|
||||
@@ -351,11 +358,11 @@ struct rqpkt {
|
||||
#define RA82_CYL 1435 /* 0-1422 user */
|
||||
#define RA82_TPG RA82_SURF
|
||||
#define RA82_GPC 1
|
||||
#define RA82_XBN 3420 /* cyl 1427-1430 */
|
||||
#define RA82_DBN 3420 /* cyl 1431-1434 */
|
||||
#define RA82_XBN 3480 /* cyl 1427-1430 */
|
||||
#define RA82_DBN 3480 /* cyl 1431-1434 */
|
||||
#define RA82_LBN 1216665 /* 57*15*1423 */
|
||||
#define RA82_RCTS 400 /* cyl 1423-1426 */
|
||||
#define RA82_RCTC 8
|
||||
#define RA82_RCTS 3420 /* cyl 1423-1426 */
|
||||
#define RA82_RCTC 1
|
||||
#define RA82_RBN 21345 /* 1 *15*1423 */
|
||||
#define RA82_MOD 11
|
||||
#define RA82_MED 0x25641052
|
||||
@@ -383,11 +390,11 @@ struct rqpkt {
|
||||
#define RA72_CYL 1921 /* 0-1914 user */
|
||||
#define RA72_TPG RA72_SURF
|
||||
#define RA72_GPC 1
|
||||
#define RA72_XBN 2040 /* cyl 1917-1918? */
|
||||
#define RA72_DBN 2040 /* cyl 1920-1921? */
|
||||
#define RA72_XBN 2080 /* cyl 1917-1918? */
|
||||
#define RA72_DBN 2080 /* cyl 1920-1921? */
|
||||
#define RA72_LBN 1953300 /* 51*20*1915 */
|
||||
#define RA72_RCTS 400 /* cyl 1915-1916? */
|
||||
#define RA72_RCTC 5 /* ? */
|
||||
#define RA72_RCTS 2040 /* cyl 1915-1916? */
|
||||
#define RA72_RCTC 1
|
||||
#define RA72_RBN 38300 /* 1 *20*1915 */
|
||||
#define RA72_MOD 37
|
||||
#define RA72_MED 0x25641048
|
||||
@@ -399,11 +406,11 @@ struct rqpkt {
|
||||
#define RA90_CYL 2656 /* 0-2648 user */
|
||||
#define RA90_TPG RA90_SURF
|
||||
#define RA90_GPC 1
|
||||
#define RA90_XBN 1794 /* cyl 2651-2652? */
|
||||
#define RA90_DBN 1794 /* cyl 2653-2654? */
|
||||
#define RA90_XBN 1820 /* cyl 2651-2652? */
|
||||
#define RA90_DBN 1820 /* cyl 2653-2654? */
|
||||
#define RA90_LBN 2376153 /* 69*13*2649 */
|
||||
#define RA90_RCTS 400 /* cyl 2649-2650? */
|
||||
#define RA90_RCTC 6 /* ? */
|
||||
#define RA90_RCTS 1794 /* cyl 2649-2650? */
|
||||
#define RA90_RCTC 1
|
||||
#define RA90_RBN 34437 /* 1 *13*2649 */
|
||||
#define RA90_MOD 19
|
||||
#define RA90_MED 0x2564105A
|
||||
@@ -416,10 +423,10 @@ struct rqpkt {
|
||||
#define RA92_TPG RA92_SURF
|
||||
#define RA92_GPC 1
|
||||
#define RA92_XBN 174 /* cyl 3100? */
|
||||
#define RA92_DBN 775
|
||||
#define RA92_DBN 788
|
||||
#define RA92_LBN 2940951 /* 73*13*3099 */
|
||||
#define RA92_RCTS 316 /* cyl 3099? */
|
||||
#define RA92_RCTC 3 /* ? */
|
||||
#define RA92_RCTS 949 /* cyl 3099? */
|
||||
#define RA92_RCTC 1
|
||||
#define RA92_RBN 40287 /* 1 *13*3099 */
|
||||
#define RA92_MOD 29
|
||||
#define RA92_MED 0x2564105C
|
||||
@@ -444,6 +451,54 @@ struct rqpkt {
|
||||
#define RA8U_MAXC 4000000 /* max cap LBNs */
|
||||
#define RA8U_EMAXC 2000000000 /* ext max cap */
|
||||
|
||||
#define RA60_DTYPE 13 /* SDI drive */
|
||||
#define RA60_SECT 42 /* +1 spare/track */
|
||||
#define RA60_SURF 6
|
||||
#define RA60_CYL 1600 /* 0-1587 user */
|
||||
#define RA60_TPG RA60_SURF
|
||||
#define RA60_GPC 1
|
||||
#define RA60_XBN 1032 /* cyl 1592-1595 */
|
||||
#define RA60_DBN 1032 /* cyl 1596-1599 */
|
||||
#define RA60_LBN 400176 /* 42*6*1588 */
|
||||
#define RA60_RCTS 1008 /* cyl 1588-1591 */
|
||||
#define RA60_RCTC 1
|
||||
#define RA60_RBN 9528 /* 1 *6*1588 */
|
||||
#define RA60_MOD 4
|
||||
#define RA60_MED 0x22A4103C
|
||||
#define RA60_FLGS (RQDF_RMV | RQDF_SDI)
|
||||
|
||||
#define RA81_DTYPE 14 /* SDI drive */
|
||||
#define RA81_SECT 51 /* +1 spare/track */
|
||||
#define RA81_SURF 14
|
||||
#define RA81_CYL 1258 /* 0-1247 user */
|
||||
#define RA81_TPG RA81_SURF
|
||||
#define RA81_GPC 1
|
||||
#define RA81_XBN 2436 /* cyl 1252-1254? */
|
||||
#define RA81_DBN 2436 /* cyl 1255-1256? */
|
||||
#define RA81_LBN 891072 /* 51*14*1248 */
|
||||
#define RA81_RCTS 2856 /* cyl 1248-1251? */
|
||||
#define RA81_RCTC 1
|
||||
#define RA81_RBN 17472 /* 1 *14*1248 */
|
||||
#define RA81_MOD 5
|
||||
#define RA81_MED 0x25641051
|
||||
#define RA81_FLGS RQDF_SDI
|
||||
|
||||
#define RA71_DTYPE 15 /* SDI drive */
|
||||
#define RA71_SECT 51 /* +1 spare/track */
|
||||
#define RA71_SURF 14
|
||||
#define RA71_CYL 1921 /* 0-1914 user */
|
||||
#define RA71_TPG RA71_SURF
|
||||
#define RA71_GPC 1
|
||||
#define RA71_XBN 1456 /* cyl 1917-1918? */
|
||||
#define RA71_DBN 1456 /* cyl 1919-1920? */
|
||||
#define RA71_LBN 1367310 /* 51*14*1915 */
|
||||
#define RA71_RCTS 1428 /* cyl 1915-1916? */
|
||||
#define RA71_RCTC 1
|
||||
#define RA71_RBN 26810 /* 1 *14*1915 */
|
||||
#define RA71_MOD 40
|
||||
#define RA71_MED 0x25641047
|
||||
#define RA71_FLGS RQDF_SDI
|
||||
|
||||
struct drvtyp {
|
||||
int32 sect; /* sectors */
|
||||
int32 surf; /* surfaces */
|
||||
@@ -476,7 +531,9 @@ static struct drvtyp drv_tab[] = {
|
||||
{ RQ_DRV (RD54), "RD54" }, { RQ_DRV (RA82), "RA82" },
|
||||
{ RQ_DRV (RRD40), "RRD40" }, { RQ_DRV (RA72), "RA72" },
|
||||
{ RQ_DRV (RA90), "RA90" }, { RQ_DRV (RA92), "RA92" },
|
||||
{ RQ_DRV (RA8U), "RAUSER" }, { 0 } };
|
||||
{ RQ_DRV (RA8U), "RAUSER" }, { RQ_DRV (RA60), "RA60" },
|
||||
{ RQ_DRV (RA81), "RA81" }, { RQ_DRV (RA71), "RA71" },
|
||||
{ 0 } };
|
||||
|
||||
extern int32 int_req[IPL_HLVL];
|
||||
extern int32 tmr_poll, clk_tps;
|
||||
@@ -666,12 +723,18 @@ MTAB rq_mod[] = {
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RD54_DTYPE, NULL, "RD54",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA60_DTYPE, NULL, "RA60",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA81_DTYPE, NULL, "RA81",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA82_DTYPE, NULL, "RA82",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RRD40_DTYPE, NULL, "RRD40",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RRD40_DTYPE, NULL, "CDROM",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA71_DTYPE, NULL, "RA71",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA72_DTYPE, NULL, "RA72",
|
||||
&rq_set_type, NULL, NULL },
|
||||
{ MTAB_XTD | MTAB_VUN, RA90_DTYPE, NULL, "RA90",
|
||||
@@ -2028,7 +2091,7 @@ uint32 cap;
|
||||
uint32 max = sim_taddr_64? RA8U_EMAXC: RA8U_MAXC;
|
||||
t_stat r;
|
||||
|
||||
if ((val < 0) || (val > RA8U_DTYPE) || ((val != RA8U_DTYPE) && cptr))
|
||||
if ((val < 0) || ((val != RA8U_DTYPE) && cptr))
|
||||
return SCPE_ARG;
|
||||
if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
|
||||
if (cptr) {
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp11_ry.c: RX211/RXV21/RX02 floppy disk simulator
|
||||
|
||||
Copyright (c) 1993-2004, Robert M Supnik
|
||||
Copyright (c) 1993-2005, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
ry RX211/RXV21/RX02 floppy disk
|
||||
|
||||
18-Feb-05 RMS Fixed bug in boot code (reported by Graham Toal)
|
||||
30-Sep-04 RMS Revised Unibus interface
|
||||
21-Mar-04 RMS Added VAX support
|
||||
29-Dec-03 RMS Added RXV21 support
|
||||
@@ -575,6 +576,7 @@ static const uint16 boot_rom[] = {
|
||||
0032711, 0000040, /* RD: BIT #40, (R1) ; ready? */
|
||||
0001775, /* BEQ .-4 */
|
||||
0012746, 0000007, /* MOV #READ+GO, -(SP) */
|
||||
0050316, /* BIS R3, (SP) ; or unit */
|
||||
0050416, /* BIS R4, (SP) ; or density */
|
||||
0012611, /* MOV (SP)+, (R1) ; read & go */
|
||||
0105711, /* TSTB (R1) ; xfr ready? */
|
||||
@@ -588,7 +590,7 @@ static const uint16 boot_rom[] = {
|
||||
0005711, /* TST (R1) ; error? */
|
||||
0100003, /* BEQ OK */
|
||||
0005704, /* TST R4 ; single? */
|
||||
0001346, /* BNE DN ; no, try again */
|
||||
0001345, /* BNE DN ; no, try again */
|
||||
0000000, /* HALT ; dead */
|
||||
0012746, 0000003, /* OK: MOV #EMPTY+GO, -(SP); empty & go */
|
||||
0050416, /* BIS R4, (SP) ; or density */
|
||||
@@ -609,7 +611,7 @@ static const uint16 boot_rom[] = {
|
||||
0062602, /* ADD (SP)+, R2 ; adv buf addr */
|
||||
0122525, /* CMPB (R5)+, (R5)+ ; sect += 2 */
|
||||
0020527, 0000007, /* CMP R5, #7 ; end? */
|
||||
0101716, /* BLOS RD ; read next */
|
||||
0101715, /* BLOS RD ; read next */
|
||||
0005002, /* CLR R2 */
|
||||
0005003, /* CLR R3 */
|
||||
0012704, BOOT_START+020, /* MOV #START+20, R4 */
|
||||
|
||||
Reference in New Issue
Block a user