From 13cb294274da5febbaf50bd597ea90a83ea3db47 Mon Sep 17 00:00:00 2001 From: Roberto Sancho Villa <32797258+rsanchovilla@users.noreply.github.com> Date: Fri, 18 May 2018 21:58:24 +0200 Subject: [PATCH] I650: Release 3 New Hardware support: - IBM 653 Storage Unit: provides machine opcodes for Floating Point, Immediate Access Storage (IAS), Three Index registers, Cards Punch-read synchronizers 2 and 3. New Software included: - FORTRANSIT: version II (S), plus run time PACKAGE with standard Fortran functions. - Reorganized sw directory, separating each language in its own folder. Each one Includes a 00_readme.txt file with restoration notes and comments. New features: - Support for SOAP opcode mnemonics in addition to regular IBM mnemonics - FAST / REALTIME CPU options - PROP pseudo register - CARDDECK ECHOLAST command --- I650/650_test.ini | 41 +- I650/i650_cdp.c | 321 ++- I650/i650_cdr.c | 310 ++- I650/i650_cpu.c | 1167 ++++++++--- I650/i650_defs.h | 247 ++- I650/i650_sys.c | 412 ++-- I650/sw/Build_is_from_decks.ini | 18 +- I650/sw/Build_soap_from_source.ini | 7 +- I650/sw/bell/00_readme.txt | 26 + I650/sw/{ => bell}/is.dck | 4 +- I650/sw/{ => bell}/is_example_1_src.txt | 0 I650/sw/{ => bell}/is_main_src.txt | 0 I650/sw/{ => bell}/is_set_loopbox.txt | 0 I650/sw/{ => bell}/is_sys_load_src.txt | 0 I650/sw/{ => bell}/is_trace_src.txt | 0 I650/sw/build_fortransit_pack.ini | 106 + I650/sw/fortransit/00_readme.txt | 186 ++ I650/sw/fortransit/fortransit_addfn.dck | 71 + .../fortransit/fortransit_addfn_listing.txt | 71 + I650/sw/fortransit/fortransit_addfn_src.txt | 71 + .../fortransit/fortransit_example_1_src.txt | 34 + .../fortransit/fortransit_example_2_data.txt | 7 + .../fortransit/fortransit_example_2_src.txt | 12 + .../fortransit/fortransit_example_3_src.txt | 7 + .../fortransit/fortransit_example_4_src.txt | 118 ++ .../fortransit/fortransit_example_5_src.txt | 42 + I650/sw/fortransit/fortransit_translator.dck | 1762 ++++++++++++++++ .../fortransit_translator_listing.txt | 1729 ++++++++++++++++ .../fortransit/fortransit_translator_src.txt | 1724 +++++++++++++++ I650/sw/fortransit/it_compiler.dck | 1691 +++++++++++++++ I650/sw/fortransit/it_compiler_listing.txt | 1841 +++++++++++++++++ I650/sw/fortransit/pack.dck | 749 +++++++ I650/sw/fortransit/pack_entry_src.txt | 44 + I650/sw/fortransit/pack_listing.txt | 774 +++++++ I650/sw/fortransit/pack_res1.txt | 21 + I650/sw/fortransit/pack_res2.txt | 21 + I650/sw/fortransit/pack_src.txt | 684 ++++++ I650/sw/{ => fortransit}/soapII.dck | 0 I650/sw/it/00_readme.txt | 58 + I650/sw/{ => it}/it_compiler.dck | 0 I650/sw/{ => it}/it_compiler_listing.txt | 30 +- I650/sw/{ => it}/it_example_1_data.txt | 0 I650/sw/{ => it}/it_example_1_out.txt | 0 I650/sw/{ => it}/it_example_1_src.txt | 0 I650/sw/{ => it}/it_example_2_src.txt | 6 +- I650/sw/{ => it}/it_package_p1.dck | 0 I650/sw/{ => it}/it_package_p1_listing.txt | 0 I650/sw/{ => it}/it_package_p2.dck | 0 I650/sw/{ => it}/it_package_p2_listing.txt | 2 +- I650/sw/{ => it}/it_package_p3.dck | 0 I650/sw/{ => it}/it_package_p3_listing.txt | 2 +- I650/sw/{ => it}/it_package_p4.dck | 0 I650/sw/{ => it}/it_package_p4_listing.txt | 0 I650/sw/{ => it}/it_reservation_p1.dck | 0 .../sw/{ => it}/it_reservation_p1_listing.txt | 0 I650/sw/{ => it}/it_reservation_p2.dck | 0 .../sw/{ => it}/it_reservation_p2_listing.txt | 0 I650/sw/{ => it}/it_reservation_p3.dck | 0 .../sw/{ => it}/it_reservation_p3_listing.txt | 0 I650/sw/{ => it}/it_reservation_p4.dck | 0 .../sw/{ => it}/it_reservation_p4_listing.txt | 0 I650/sw/{ => it}/it_subr_cos_listing.txt | 34 +- I650/sw/{ => it}/it_subr_sqrt_listing.txt | 0 I650/sw/it/soapII.dck | 1400 +++++++++++++ .../soapII_patch.dck} | 0 .../soapII_patch.txt} | 1 + .../soap_patch_listing.txt} | 0 I650/sw/it_subr_sin_listing.txt | 87 - I650/sw/run_fortransit.ini | 247 +++ I650/sw/{is_run.ini => run_is.ini} | 4 +- I650/sw/{it_run.ini => run_it.ini} | 23 +- I650/sw/{soap_and_run.ini => run_soap.ini} | 10 +- I650/sw/soap/00_readme.txt | 11 + I650/sw/soap/soapII.dck | 1400 +++++++++++++ I650/sw/{ => soap}/soapII_condensed_card.dck | 0 I650/sw/{ => soap}/soap_example_1_src.txt | 0 I650/sw/{ => soap}/soap_listing.txt | 0 I650/sw/{ => soap}/soap_src.txt | 0 doc/i650_doc.doc | Bin 372736 -> 428544 bytes 79 files changed, 16830 insertions(+), 803 deletions(-) create mode 100644 I650/sw/bell/00_readme.txt rename I650/sw/{ => bell}/is.dck (99%) rename I650/sw/{ => bell}/is_example_1_src.txt (100%) rename I650/sw/{ => bell}/is_main_src.txt (100%) rename I650/sw/{ => bell}/is_set_loopbox.txt (100%) rename I650/sw/{ => bell}/is_sys_load_src.txt (100%) rename I650/sw/{ => bell}/is_trace_src.txt (100%) create mode 100644 I650/sw/build_fortransit_pack.ini create mode 100644 I650/sw/fortransit/00_readme.txt create mode 100644 I650/sw/fortransit/fortransit_addfn.dck create mode 100644 I650/sw/fortransit/fortransit_addfn_listing.txt create mode 100644 I650/sw/fortransit/fortransit_addfn_src.txt create mode 100644 I650/sw/fortransit/fortransit_example_1_src.txt create mode 100644 I650/sw/fortransit/fortransit_example_2_data.txt create mode 100644 I650/sw/fortransit/fortransit_example_2_src.txt create mode 100644 I650/sw/fortransit/fortransit_example_3_src.txt create mode 100644 I650/sw/fortransit/fortransit_example_4_src.txt create mode 100644 I650/sw/fortransit/fortransit_example_5_src.txt create mode 100644 I650/sw/fortransit/fortransit_translator.dck create mode 100644 I650/sw/fortransit/fortransit_translator_listing.txt create mode 100644 I650/sw/fortransit/fortransit_translator_src.txt create mode 100644 I650/sw/fortransit/it_compiler.dck create mode 100644 I650/sw/fortransit/it_compiler_listing.txt create mode 100644 I650/sw/fortransit/pack.dck create mode 100644 I650/sw/fortransit/pack_entry_src.txt create mode 100644 I650/sw/fortransit/pack_listing.txt create mode 100644 I650/sw/fortransit/pack_res1.txt create mode 100644 I650/sw/fortransit/pack_res2.txt create mode 100644 I650/sw/fortransit/pack_src.txt rename I650/sw/{ => fortransit}/soapII.dck (100%) create mode 100644 I650/sw/it/00_readme.txt rename I650/sw/{ => it}/it_compiler.dck (100%) rename I650/sw/{ => it}/it_compiler_listing.txt (98%) rename I650/sw/{ => it}/it_example_1_data.txt (100%) rename I650/sw/{ => it}/it_example_1_out.txt (100%) rename I650/sw/{ => it}/it_example_1_src.txt (100%) rename I650/sw/{ => it}/it_example_2_src.txt (92%) rename I650/sw/{ => it}/it_package_p1.dck (100%) rename I650/sw/{ => it}/it_package_p1_listing.txt (100%) rename I650/sw/{ => it}/it_package_p2.dck (100%) rename I650/sw/{ => it}/it_package_p2_listing.txt (98%) rename I650/sw/{ => it}/it_package_p3.dck (100%) rename I650/sw/{ => it}/it_package_p3_listing.txt (98%) rename I650/sw/{ => it}/it_package_p4.dck (100%) rename I650/sw/{ => it}/it_package_p4_listing.txt (100%) rename I650/sw/{ => it}/it_reservation_p1.dck (100%) rename I650/sw/{ => it}/it_reservation_p1_listing.txt (100%) rename I650/sw/{ => it}/it_reservation_p2.dck (100%) rename I650/sw/{ => it}/it_reservation_p2_listing.txt (100%) rename I650/sw/{ => it}/it_reservation_p3.dck (100%) rename I650/sw/{ => it}/it_reservation_p3_listing.txt (100%) rename I650/sw/{ => it}/it_reservation_p4.dck (100%) rename I650/sw/{ => it}/it_reservation_p4_listing.txt (100%) rename I650/sw/{ => it}/it_subr_cos_listing.txt (79%) rename I650/sw/{ => it}/it_subr_sqrt_listing.txt (100%) create mode 100644 I650/sw/it/soapII.dck rename I650/sw/{it_soapII_patch.dck => it/soapII_patch.dck} (100%) rename I650/sw/{it_soapII_patch.txt => it/soapII_patch.txt} (92%) rename I650/sw/{it_soapIIA_patch_listing.txt => it/soap_patch_listing.txt} (100%) delete mode 100644 I650/sw/it_subr_sin_listing.txt create mode 100644 I650/sw/run_fortransit.ini rename I650/sw/{is_run.ini => run_is.ini} (89%) rename I650/sw/{it_run.ini => run_it.ini} (78%) rename I650/sw/{soap_and_run.ini => run_soap.ini} (87%) create mode 100644 I650/sw/soap/00_readme.txt create mode 100644 I650/sw/soap/soapII.dck rename I650/sw/{ => soap}/soapII_condensed_card.dck (100%) rename I650/sw/{ => soap}/soap_example_1_src.txt (100%) rename I650/sw/{ => soap}/soap_listing.txt (100%) rename I650/sw/{ => soap}/soap_src.txt (100%) diff --git a/I650/650_test.ini b/I650/650_test.ini index ce1a0c85..d245cd94 100644 --- a/I650/650_test.ini +++ b/I650/650_test.ini @@ -10,20 +10,39 @@ cd sw ; set throttle 11k ; set throttle 55/5 +do build_soap_from_source.ini +set env -P "Press Enter to continue . . . " -do Build_soap_from_source.ini -set env -P "Press enter to continue . . . " +do run_soap.ini soap/soap_example_1_src.txt 1000 +set env -P "Press Enter to continue . . . " -do soap_and_run.ini soap_example_1_src.txt 1000 -set env -P "Press enter to continue . . . " +do build_is_from_decks.ini ntr lbox +set env -P "Press Enter to continue . . . " -do Build_is_from_decks.ini ntr lbox -set env -P "Press enter to continue . . . " +do run_is.ini bell/is_example_1_src.txt +set env -P "Press Enter to continue . . . " -do is_run.ini is_example_1_src.txt -set env -P "Press enter to continue . . . " +do run_it.ini it/it_example_1_src.txt it/it_example_1_data.txt +set env -P "Press Enter to continue . . . " -do it_run.ini it_example_1_src.txt it_example_1_data.txt deck_out.dck -set env -P "Press enter to continue . . . " +do run_it.ini it/it_example_2_src.txt nul +set env -P "Press Enter to continue . . . " -do it_run.ini it_example_2_src.txt nul deck_out.dck +do build_fortransit_pack.ini +set env -P "Press Enter to continue . . . " + +do run_fortransit.ini fortransit/fortransit_example_2_src.txt fortransit/fortransit_example_2_data.txt +set env -P "Press Enter to continue . . . " + +do run_fortransit.ini fortransit/fortransit_example_1_src.txt nul +set env -P "Press Enter to continue . . . " + +do run_fortransit.ini fortransit/fortransit_example_4_src.txt +set env -P "Press Enter to continue . . . " + +do run_fortransit.ini fortransit/fortransit_example_5_src.txt +set env -P "Press Enter to continue . . . " + +goto end + +:end diff --git a/I650/i650_cdp.c b/I650/i650_cdp.c index 2517b724..df33e9d9 100644 --- a/I650/i650_cdp.c +++ b/I650/i650_cdp.c @@ -137,6 +137,8 @@ void encode_lpt_num(t_int64 d, int l) #define wf_sN_NNNNNNN_NN 3 #define wf_sN_NNN_NNN_NNN 4 #define wf_nnnnnnnnnNs 5 +#define wf_nnnnnnnnnH 6 +#define wf_NNNNNNNNNN 7 void encode_lpt_word(t_int64 d, int NegZero, int wFormat) { @@ -163,6 +165,16 @@ void encode_lpt_word(t_int64 d, int NegZero, int wFormat) } else if (wFormat == wf_nnnnnnnnnNs) { encode_lpt_num(d,-10); // replace leading zeroes by spaces encode_char(0, neg ? '-':' '); + } else if (wFormat == wf_nnnnnnnnnH) { + if (d < 10) { + encode_lpt_spc(9); + } else { + encode_lpt_num(d / 10, -9); // print 9 digits, replacing leading zeroes by spaces + } + n = d % 10; + encode_char(0, (n==0) ? '+':'A'+n-1); // hi punch on last digit + } else if (wFormat == wf_NNNNNNNNNN) { + encode_lpt_num(d,10); } else { // default: wFormat == wf_NNNNNNNNNNs encode_lpt_num(d,10); encode_char(0, neg ? '-':' '); @@ -209,17 +221,18 @@ void encode_pch_str(const char * buf) } -void encode_8word_wiring(int addr) +void encode_8word_wiring(void) { // encode 8 numerical words per card - // get the decoded data from drum at addr + // get the decoded data from IOSync int i, NegZero; t_int64 d; char pch_word[20]; // punch card for(i=0;i<8;i++) { - ReadDrum(addr + i, &d, &NegZero); + d = IOSync[i]; + NegZero = IOSync_NegativeZeroFlag[i]; sprintf_word(pch_word, d, NegZero, 0); encode_pch_str(pch_word); } @@ -227,13 +240,14 @@ void encode_8word_wiring(int addr) // print out card contents // 8 words in format NN NNNN NNNN+ for(i=0;i<8;i++) { - ReadDrum(addr + i, &d, &NegZero); + d = IOSync[i]; + NegZero = IOSync_NegativeZeroFlag[i]; encode_lpt_word(d, NegZero, wf_NN_NNNN_NNNNs); encode_lpt_spc(1); } } -void encode_soap_wiring(int addr) +void encode_soap_wiring(void) { // encode soap card simulating soap control panel wiring for 533 // from SOAP II manual at http://www.bitsavers.org/pdf/ibm/650/24-4000-0_SOAPII.pdf @@ -279,19 +293,19 @@ void encode_soap_wiring(int addr) int i, sv_card_nbuf, n; int pat1, pat2; - word_to_ascii(loc, 1, 5, DRUM[addr + 0]); - word_to_ascii(data_addr, 1, 5, DRUM[addr + 1]); - word_to_ascii(inst_addr, 1, 5, DRUM[addr + 2]); - word_to_ascii(OpCode, 1, 3, DRUM[addr + 3]); - word_to_ascii(Data_Tag, 4, 1, DRUM[addr + 3]); - word_to_ascii(Instr_Tag, 5, 1, DRUM[addr + 3]); - word_to_ascii(rem1, 1, 5, DRUM[addr + 4]); - word_to_ascii(rem2, 1, 5, DRUM[addr + 5]); - instr = DRUM[addr + 6]; - location = (int) ((DRUM[addr + 7] / D4) % D4); - ty = (int) ( DRUM[addr + 7] % 10); - CardNum = (int) ( DRUM[addr + 8] % D4); - d = DRUM[addr + 9]; + word_to_ascii(loc, 1, 5, IOSync[0]); + word_to_ascii(data_addr, 1, 5, IOSync[1]); + word_to_ascii(inst_addr, 1, 5, IOSync[2]); + word_to_ascii(OpCode, 1, 3, IOSync[3]); + word_to_ascii(Data_Tag, 4, 1, IOSync[3]); + word_to_ascii(Instr_Tag, 5, 1, IOSync[3]); + word_to_ascii(rem1, 1, 5, IOSync[4]); + word_to_ascii(rem2, 1, 5, IOSync[5]); + instr = IOSync[6]; + location = (int) ((IOSync[7] / D4) % D4); + ty = (int) ( IOSync[7] % 10); + CardNum = (int) ( IOSync[8] % D4); + d = IOSync[9]; b_blk_op = ((int) (d % 10) == 8) ? 1:0; d = d / 10; b_blk_i = ((int) (d % 10) == 8) ? 1:0; d = d / 10; b_blk_d = ((int) (d % 10) == 8) ? 1:0; d = d / 10; @@ -303,13 +317,13 @@ void encode_soap_wiring(int addr) neg = ((int) (d % 10) == 8) ? 1:0; d = d / 10; b_non_blank = ((int) (d % 10) == 8) ? 1:0; d = d / 10; - // printf("bits %06d%04d%c ", printfw(DRUM[addr + 9])); // to echo the status digits of punched card + // printf("bits %06d%04d%c ", printfw(IOSync[9])); // to echo the control word of punched card // generate card if (b_pch_b) { // punch availability table (pat pseudo-op output) for(i=0;i<8;i++) { - sprintf_word(pch_word, DRUM[addr + i], 0, 1); + sprintf_word(pch_word, IOSync[i], 0, 1); encode_pch_str(pch_word); } } else { @@ -353,10 +367,10 @@ void encode_soap_wiring(int addr) if (b_pch_b) { // print availability table (pat pseudo-op output) for(i=0; i<4; i++) { - d = DRUM[addr + i*2]; + d = IOSync[i*2]; pat1 = (int) ((d / D4) % D4); pat2 = (int) ( d % D4); - d = DRUM[addr + i*2 + 1]; + d = IOSync[i*2 + 1]; encode_lpt_num(pat1, 4); encode_lpt_spc(2); encode_lpt_num(d, 10); @@ -412,7 +426,7 @@ void encode_soap_wiring(int addr) } } -void encode_is_wiring(int addr) +void encode_is_wiring(void) { // encode Floationg Decimal Interpretive System (IS) card simulating control panel wiring for 533 as described // in manual at http://www.bitsavers.org/pdf/ibm/650/28-4024_FltDecIntrpSys @@ -454,23 +468,24 @@ void encode_is_wiring(int addr) char pch_word[20]; int bSetHiPunch; - bSetHiPunch = (DRUM[addr] < 0) ? 2 : 0; // first bSetHiPunch is 2 if word negative (signals a load card must be punched) + bSetHiPunch = (IOSync[0] < 0) ? 2 : 0; // first bSetHiPunch is 2 if word negative (signals a load card must be punched) - loc = (int) ((DRUM[addr] / D4) % D4); - CardNum = (int) ((DRUM[addr+9] / D4) % D4); - wc = (int) ((DRUM[addr+1] / D4) % D4); - PrNum = (int) ( DRUM[addr+8]); - bTraceCard = (DRUM[addr] / D8) > 0 ? 1 : 0; // if to higher digits are nonzero -> is a trace card + loc = (int) ((IOSync[0] / D4) % D4); + CardNum = (int) ((IOSync[9] / D4) % D4); + wc = (int) ((IOSync[1] / D4) % D4); + PrNum = (int) ( IOSync[8]); + bTraceCard = (IOSync[0] / D8) > 0 ? 1 : 0; // if to higher digits are nonzero -> is a trace card if (bSetHiPunch) { // punch a load card for(i=0;i<8;i++) { - ReadDrum(addr + i, &d, &NegZero); - if ((i==0) && (d < 0)) d = -d; // get absolute value for DRUM[addr + 0] + d = IOSync[i]; + NegZero = IOSync_NegativeZeroFlag[i]; + if ((i==0) && (d < 0)) d = -d; // get absolute value for IOSync[0] sprintf_word(pch_word, d, NegZero, bSetHiPunch); if (bSetHiPunch==2) bSetHiPunch = 1; // if bSetHiPunch is 2 change it to bSetHiPunch = 1 encode_pch_str(pch_word); - } + } } else { // punch a card using output format if (loc < 1000) { @@ -481,7 +496,8 @@ void encode_is_wiring(int addr) encode_pch_str(pch_word); for(i=0;i<6;i++) { if (i | Alphabetic + // 1978: | <- statement -> | Alphabetic + // 1979: | <- statement -> | Alphabetic + // 1980: | <- statement -> | Alphabetic + // 1981: | <- statement -> | Alphabetic + // 1982: | <- statement -> | Alphabetic + // +-------------------+ + // 1983: | | Not Used + // 1984: | | Not Used + // +-----------+-------+ + // 1985: | |N N N N| N N N N=Statement Number + // 1986: |a|b|c|d|e|f|g|h|i|j| Control Word + // a = 0/8 =8 -> punch a data card + // b = 0/8 + // c = 0/8 + // d = 0/8 =8 -> ??? + // e = 0/8 + // f = 0/8 + // g = 0/8 =8 -> punching a IT source card, =0 -> punching SOAP card + // h = 0/8 + // i = 0/8 =8 -> punching a FORTRANSIT card + // j = 0/8 =8 -> punching an IT header card (8 word load card format) + // + // IT card punch format + // Column: 1 2 3 4 | 5 | 6 - 42 | 43 - 70 | 71 72 | 73 - 80 | + // N N N N | + | | Statement | | Statement | + // Statement | Y(12) | | max 28 | | number as | + // Number | Punch | | chars | | comment | + // + // + // SOAP card storage in output block + // +-------------------+ + // Word 1977: | <- Loc. Label -> | Alphabetic + // 1978: | <- Data Addr -> | Alphabetic + // 1979: | <- Inst Addr -> | Alphabetic + // 1980: | <- Op Code -> | Alphabetic + // 1981: | <- Remarks -> | Alphabetic + // 1982: | <- Remarks -> | Alphabetic + // +-------------------+ + // 1983: | | Not Used + // 1984: | | Not Used + // +-------------------+ + // 1985: | |N N N N| N N N N=Card Number as defined above + // 1986: | <- Control Word-> | As defined above + + char pch_word[20]; + char lin[31]; + char loc[6], data_addr[6], inst_addr[6], OpCode[6], rem1[6], rem2[6]; + t_int64 d; + int CardNum; + int b, neg, b_it_hdr, b_it_src, b_fort, b_soap, b_data; // punch control word flags + int i; + + word_to_ascii(&lin[0], 1, 5, IOSync[0]); + word_to_ascii(&lin[5], 1, 5, IOSync[1]); + word_to_ascii(&lin[10], 1, 5, IOSync[2]); + word_to_ascii(&lin[15], 1, 5, IOSync[3]); + word_to_ascii(&lin[20], 1, 5, IOSync[4]); + word_to_ascii(&lin[25], 1, 5, IOSync[5]); + lin[30] = 0; + + CardNum = (int) (IOSync[8] % D4); + + word_to_ascii(loc, 1, 5, IOSync[0]); + word_to_ascii(data_addr, 1, 5, IOSync[1]); + word_to_ascii(inst_addr, 1, 5, IOSync[2]); + word_to_ascii(OpCode, 1, 3, IOSync[3]); + word_to_ascii(rem1, 1, 5, IOSync[4]); + word_to_ascii(rem2, 1, 5, IOSync[5]); + + neg = 0; + + d = IOSync[9]; + b_it_hdr = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_fort = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_it_src = ((int) (d % 10) == 8) ? 1:0; d = d / 10; b_soap = ((b_fort == 1) && (b_it_src == 0)); + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_data = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + + // printf("bits %06d%04d%c ", printfw(IOSync[9])); // to echo the control word of punched card + // generate card + if (b_data) { + // punch data card output for PUNCH fortransit command + for (i=0;i<8;i++) { + sprintf_word(pch_word, IOSync[i], 0, 0); + encode_pch_str(pch_word); + } + } else if (b_it_hdr) { + // punch IT header card as 8 word per card load card format + for (i=0;i<8;i++) { + sprintf_word(pch_word, IOSync[i], 0, 1); + encode_pch_str(pch_word); + } + } else if (b_soap) { + // punch SOAP source instruction + for(i=0;i<40;i++) encode_pch_str(" "); // leave 40 first columns blank + encode_pch_str(" "); + encode_char(neg == 0 ? ' ' : '-', 0); + encode_pch_str(loc); + encode_pch_str(OpCode); + encode_pch_str(data_addr); + encode_pch_str(" "); + encode_pch_str(inst_addr); + encode_pch_str(" "); + encode_pch_str(rem1); + encode_pch_str(rem2); + // convert to lowercase for punching + for (i=40;i= 'A') && (card_buf[i] <= 'Z')) + card_buf[i] = card_buf[i] - 'A' + 'a'; + } else if (b_it_src) { + // punch IT source card + sprintf_word(pch_word, CardNum, 0, 0); // punch statement number + for (i=0;i<4;i++) pch_word[i] = pch_word[i+6]; + pch_word[4] = '+'; + for (i=5;i<10;i++) pch_word[i] = ' '; // punch separation spaces + encode_pch_str(pch_word); + for (i=10;i<42;i++) encode_pch_str(" "); + encode_pch_str(lin); // punch statement + encode_pch_str(" "); + sprintf_word(pch_word, CardNum, 0, 0); // punch statement number again as comment + for (i=0;i<4;i++) pch_word[i] = pch_word[i+6]; + pch_word[4] = 0; + encode_pch_str(pch_word); + // convert to lowercase for punching + for (i=0;i= 'A') && (card_buf[i] <= 'Z')) + card_buf[i] = card_buf[i] - 'A' + 'a'; + } + + // generate printout + if (b_data) { + // print data card output for PUNCH fortransit command + for (i=0;i<8;i++) { + d = IOSync[i]; + if ((d == 0) && (i != 0)) { + encode_lpt_spc(11); + } else { + encode_lpt_word(d, 0, wf_nnnnnnnnnNs); + } + encode_lpt_spc(1); + } + } else if (b_it_hdr) { + // print IT header card as 8 word per card load card format + for (i=0;i<8;i++) { + if (i==4) { + encode_lpt_word(IOSync[i], 0, wf_NNNNNNNNNN); + } else { + encode_lpt_word(IOSync[i], 0, wf_nnnnnnnnnH); + } + } + } else if (b_soap) { + // print generated SOAP source listing + encode_lpt_spc(2); + encode_lpt_num(CardNum, -4); + encode_lpt_spc(6); + encode_lpt_str(loc); + encode_lpt_spc(2); encode_char(0, neg ? '-':' '); encode_lpt_spc(1); + encode_lpt_str(OpCode); encode_lpt_spc(3); + encode_lpt_str(data_addr); encode_lpt_spc(3); + encode_lpt_str(inst_addr); encode_lpt_spc(6); + encode_lpt_str(rem1); encode_lpt_str(rem2); + } else if (b_it_src) { + // print generated it source listing + if (CardNum == 0) { + encode_lpt_spc(5); + } else { + encode_lpt_num(CardNum, -4); + encode_lpt_str("+"); + } + encode_lpt_spc(37); + encode_lpt_str(lin); + encode_lpt_spc(4); + encode_lpt_num(CardNum, 4); + } +} + + /* Card punch routine */ uint32 cdp_cmd(UNIT * uptr, uint16 cmd, uint16 addr) { @@ -710,19 +918,22 @@ uint32 cdp_cmd(UNIT * uptr, uint16 cmd, uint16 addr) if (wiring == WIRING_SOAP) { // encode soap card simulating soap control panel wiring for 533 (gasp!) - encode_soap_wiring(addr); + encode_soap_wiring(); } else if (wiring == WIRING_IS) { // encode floating point interpretive system (bell interpreter) card - encode_is_wiring(addr); + encode_is_wiring(); } else if (wiring == WIRING_IT) { // encode Carnegie Internal Translator compiler card - encode_it_wiring(addr); + encode_it_wiring(); + } else if (wiring == WIRING_FORTRANSIT) { + // encode Fortransit translator card + encode_fortransit_wiring(); } else if (wiring == WIRING_8WORD) { // encode 8 words per card - encode_8word_wiring(addr); + encode_8word_wiring(); } else { // default wiring: decode up to 8 numerical words per card - encode_8word_wiring(addr); + encode_8word_wiring(); } if ((card_nlpt == 1) && (card_lpt[0] == 0)) { diff --git a/I650/i650_cdr.c b/I650/i650_cdr.c index 261eccd8..2f47b45e 100644 --- a/I650/i650_cdr.c +++ b/I650/i650_cdr.c @@ -74,16 +74,20 @@ DEVICE cdr_dev = { NULL, NULL, &cdr_help, NULL, NULL, &cdr_description }; +// buffer to hold read cards in take hopper of each unit +// to be printed by carddeck command +char ReadHopper[3 * MAX_CARDS_IN_READ_TAKE_HOPPER * 80]; +int ReadHopperLast[3]; // get 10 digits word with sign from card buf (the data struct). return 1 if HiPunch set on any digit -int decode_8word_wiring(struct _card_data * data, int addr) +int decode_8word_wiring(struct _card_data * data, int bCheckForHiPunch) { // decode up to 8 numerical words per card // input card // NNNNNNNNNN ... 8 times // If last digit of word has X(11) punch whole word is set as negative value // If N is non numeric, a 0 is assumed - // put the decoded data in drum at addr (if addr < 0 -> do not store in drum) + // put the decoded data in IO Sync buffer (if bCheckForHiPunch = 1 -> do not store in IO Sync Buffer) // return 1 if any colum has Y(12) hi-punch set uint16 c1,c2; int wn,iCol,iDigit; @@ -113,7 +117,7 @@ int decode_8word_wiring(struct _card_data * data, int addr) c1 = c1 & 0x3FF; // remove X and Y punches c2 = data->hol_to_ascii[c1]; // convert to ascii again c2 = c2 - '0'; // convert ascii to binary digit - if (c2 > 9) c2 = 0; // nondigits chars interpreted as zero + if (c2 > 9) c2 = 0; // nondigits chars interpreted as zero d = d * 10 + c2; } // end of word. set sign @@ -121,15 +125,18 @@ int decode_8word_wiring(struct _card_data * data, int addr) d = -d; // yes, change sign of word read if (d == 0) NegZero=1; // word read is minus zero } - if (addr >= 0) WriteDrum(addr++, d, NegZero); // store word read from card into drum - + + if (bCheckForHiPunch == 0) { + IOSync [wn]=d; + IOSync_NegativeZeroFlag[wn]=NegZero; + } } return HiPunch; } // load soap symbolic info, This is a facility to help debugging of soap programs into SimH // does not exist in real hw -void decode_soap_symb_info(struct _card_data * data, int addr) +void decode_soap_symb_info(struct _card_data * data) { t_int64 d; int op,da,ia,i,i2,p; @@ -137,16 +144,16 @@ void decode_soap_symb_info(struct _card_data * data, int addr) uint16 c1,c2; // check soap 1-word load card initial word - d = DRUM[addr + 0]; + d = IOSync[0]; if (d != 6919541953LL) return; // not a 1-word load card // get the address where the 1-word card will be loaded (into da) - d = DRUM[addr+2]; + d = IOSync[2]; op = Shift_Digits(&d, 2); // current inst opcode da = Shift_Digits(&d, 4); // addr of data ia = Shift_Digits(&d, 4); // addr of next instr if ((op != 24) && (ia != 8000)) return; // not a 1-word load card - if (da >= (int)MEMSIZE) return; // destination address out of range + if (da >= (int)DRUMSIZE) return; // symbolic info can only be associated to drum addrs // convert card image punches to ascii buf for processing, starting at col 40 // keep 026 fortran charset @@ -210,7 +217,7 @@ t_int64 decode_alpha_word(char * buf, int n) } -void decode_soap_wiring(struct _card_data * data, int addr) +void decode_soap_wiring(struct _card_data * data) { // decode soap card simulating soap control panel wiring for 533 // from SOAP II manual at http://www.bitsavers.org/pdf/ibm/650/24-4000-0_SOAPII.pdf @@ -254,26 +261,26 @@ void decode_soap_wiring(struct _card_data * data, int addr) } buf[80] = 0; // terminate string - DRUM[addr + 0] = decode_alpha_word(&buf[42], 5); // Location (5 chars) - DRUM[addr + 1] = decode_alpha_word(&buf[50], 5); // Data Addr (5 chars) - DRUM[addr + 2] = decode_alpha_word(&buf[56], 5); // Inst Addr (5 chars) - DRUM[addr + 3] = decode_alpha_word(&buf[47], 3) * D4 + // OpCode (3 chars only) - decode_alpha_word(&buf[55], 1) * 100 + // Data Addr Tag (1 char only) - decode_alpha_word(&buf[61], 1); // Instr Addr Tag (1 char only) - DRUM[addr + 4] = decode_alpha_word(&buf[62], 5); // Remarks - DRUM[addr + 5] = decode_alpha_word(&buf[67], 5); // Remarks + IOSync[0] = decode_alpha_word(&buf[42], 5); // Location (5 chars) + IOSync[1] = decode_alpha_word(&buf[50], 5); // Data Addr (5 chars) + IOSync[2] = decode_alpha_word(&buf[56], 5); // Inst Addr (5 chars) + IOSync[3] = decode_alpha_word(&buf[47], 3) * D4 + // OpCode (3 chars only) + decode_alpha_word(&buf[55], 1) * 100 + // Data Addr Tag (1 char only) + decode_alpha_word(&buf[61], 1); // Instr Addr Tag (1 char only) + IOSync[4] = decode_alpha_word(&buf[62], 5); // Remarks + IOSync[5] = decode_alpha_word(&buf[67], 5); // Remarks - DRUM[addr + 6] = decode_num_word(&buf[43], 4, 0); // Absolute Part of location - DRUM[addr + 7] = decode_num_word(&buf[51], 4, 0); // Absolute Part of Data Addr - DRUM[addr + 8] = decode_num_word(&buf[57], 4, 0); // Absolute Part of Instr Addr + IOSync[6] = decode_num_word(&buf[43], 4, 0); // Absolute Part of location + IOSync[7] = decode_num_word(&buf[51], 4, 0); // Absolute Part of Data Addr + IOSync[8] = decode_num_word(&buf[57], 4, 0); // Absolute Part of Instr Addr ty = buf[40] - '0'; if ((ty < 0) || (ty > 9)) ty = 0; neg = (buf[41] == '-') ? 8:0; - DRUM[addr + 9] = ty * 100 + - (ty ? 80:0) + - neg; // |T b n| T=Type (0 if Blank), b=0/8 (for non blank type), n=0/8 (for negative) + IOSync[9] = ty * 100 + + (ty ? 80:0) + + neg; // |T b n| T=Type (0 if Blank), b=0/8 (for non blank type), n=0/8 (for negative) } int sformat(char * buf, const char * match) @@ -293,7 +300,7 @@ int sformat(char * buf, const char * match) return 1; // end of match string -> return 1 -> buf matches } -void decode_is_wiring(struct _card_data * data, int addr) +void decode_is_wiring(struct _card_data * data) { // decode Floationg Decimal Interpretive System (IS) card simulating control panel wiring for 533 as described // in manual at http://www.bitsavers.org/pdf/ibm/650/28-4024_FltDecIntrpSys.pdf @@ -339,7 +346,6 @@ void decode_is_wiring(struct _card_data * data, int addr) // 1959: | Problem Number | // +-------------------+ // - // put the decoded data in drum at addr (if addr < 0 -> do not store in drum) // card number is ignored on reading int wc,neg,i; @@ -360,15 +366,15 @@ void decode_is_wiring(struct _card_data * data, int addr) if ( sformat(&buf[6], " ")) { // card with firsts 26 cols blank = blank card: read as all zero, one word count // this allows to have blank cards/comments card as long as the comment starts on column 27 of more - DRUM[addr + 1] = 1 * D4; // word count + IOSync[1] = 1 * D4; // word count } else if ( sformat(&buf[5], " NNN ")) { // alternate format for loading IT program (IT transfer card) - DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // start location (3 digits) - DRUM[addr + 1] = 0; // word count = 0 + IOSync[0] = decode_num_word(&buf[6], 3, 0) * D4; // start location (3 digits) + IOSync[1] = 0; // word count = 0 } else if ( sformat(&buf[5], " NNN +N NNN NNN NNN ")) { // alternate format for loading IT program (IT instruction) - DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) - DRUM[addr + 1] = 1 * D4; // word count + IOSync[0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + IOSync[1] = 1 * D4; // word count NegZero = 0; neg = (buf[10] == '-') ? 1:0; d = decode_num_word(&buf[11], 1, 0) * 10 * D8 + // O1 @@ -379,11 +385,12 @@ void decode_is_wiring(struct _card_data * data, int addr) d=-d; if (d==0) NegZero = 1; } - WriteDrum(addr + 2, d, NegZero); + IOSync [2]=d; + IOSync_NegativeZeroFlag[2]=NegZero; } else if ( sformat(&buf[5], " NNN +N NNNNNNN NN ")) { // alternate format for loading IT program (numeric constant in float format) - DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) - DRUM[addr + 1] = 1 * D4; // word count + IOSync[0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + IOSync[1] = 1 * D4; // word count NegZero = 0; neg = (buf[10] == '-') ? 1:0; d = decode_num_word(&buf[11], 1, 0) * 10 * D8 + // integer part of mantissa @@ -393,24 +400,25 @@ void decode_is_wiring(struct _card_data * data, int addr) d=-d; if (d==0) NegZero = 1; } - WriteDrum(addr + 2, d, NegZero); + IOSync [2]=d; + IOSync_NegativeZeroFlag[2]=NegZero; } else if ( (sformat(&buf[6], " NNNN NN NNNN NNNN ")) || (sformat(&buf[6], " NNNN NN NNNN ")) || (sformat(&buf[6], " NNNN NN NNNN ")) || (sformat(&buf[6], " NNNN NN ")) ) { // alternate format for loading main IT system deck - DRUM[addr + 0] = decode_num_word(&buf[7], 4, 0) * D4; // location (4 digits) - DRUM[addr + 1] = 1 * D4; // word count = 1 - DRUM[addr + 2] = decode_num_word(&buf[12], 2, 1) * D8 + // op - decode_num_word(&buf[15], 4, 1) * D4 + // data address - decode_num_word(&buf[20], 4, 1); // instr addr, no negative zero allowed + IOSync[0] = decode_num_word(&buf[7], 4, 0) * D4; // location (4 digits) + IOSync[1] = 1 * D4; // word count = 1 + IOSync[2] = decode_num_word(&buf[12], 2, 1) * D8 + // op + decode_num_word(&buf[15], 4, 1) * D4 + // data address + decode_num_word(&buf[20], 4, 1); // instr addr, no negative zero allowed } else { // regular IT read/punch format - DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + IOSync[0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) wc = (int) decode_num_word(&buf[9], 1, 1); if (wc > 6) wc = 6; - DRUM[addr + 1] = wc * D4; // word count + IOSync[1] = wc * D4; // word count for (i=0;i | Alphabetic + // 1952: | <- Statement -> | Alphabetic + // 1953: | <- Statement -> | Alphabetic + // 1954: | <- Statement -> | Alphabetic + // 1955: | <- Statement -> | Alphabetic + // 1956: | <- Statement -> | Alphabetic + // +-------------------+ + // 1957: | | Not used + // 1958: | | Not used + // 1959: | | Not used + // +-+-+-------+-------+ + // 1960: |m t| |N N N N| m = 8/0 (8 -> comment card) + // +---+-------+-------+ t = 8/0 (8 -> continuatin card) + // NNNN = statement sumber + // + // it source program input card + // Column: 1 2 3 4 | 5 | 6 - 42 | 43 - 70 | 71 72 | 73 - 80 | + // N N N N | + | | Statement | | Comments | + // Statement | Y(12) | | max 28 | | max 8 | + // Number | Punch | | chars | | chars | + // + // storage in input block + // +-------------------+ + // Word 0051: | <- Statement -> | Alphabetic + // 0052: | <- Statement -> | Alphabetic + // 0053: | <- Statement -> | Alphabetic + // 0054: | <- Statement -> | Alphabetic + // 0055: | <- Statement -> | Alphabetic + // 0056: | <- Statement -> | Alphabetic + // +-+-+-+-+-+-|-+-+-+-| + // 0057: | |N N N N| Statement Number + // +-+-+-+-+-+-|-+-+-+-| + // 0058: | | Not used + // 0059: | | Not used + // 0060: | | Not used + // +-------------------+ + // + // fortransit input data card + // Column: 1 - 10 | 11 - 20 | 21 - 30 | 31 - 40 | 41 - 50 | 51 - 60 | 61 - 70 | 71 72 | 73 | 74 - 80 | + // Word1 | Word2 | Word3 | Word4 | Word5 | Word6 | Word7 | | + | + // | Y(12) | + // Word = word to be loaded into FORTRANSITIT variable. Must match the variable type where it is read in + // float (MMMMMMMM EE -> M=mantisa, EE=exponent, 1000000051 is 1.0) + // fixed (NNNNNNNNNN -> 000000030J is -302) + // if word is negative, last digit get X(11) overpunch + // If last digit of word has X(11) punch whole word is set as negative value + // If N is non numeric, a 0 is assumed + // + // storage in input block + // +-------------------+ + // Word 1951: | <- Word1 -> | + // 1952: | <- Word2 -> | + // 1953: | <- Word3 -> | + // 1954: | <- Word4 -> | + // 1955: | <- Word5 -> | + // 1956: | <- Word6 -> | + // 1957: | <- Word7 -> | + // +-------------------+ + // 1958: | | Not used + // 1959: | | Not used + // 1960: | | Not used + // +-------------------+ + // + char buf[81]; + int i; + uint16 c1,c2; + // convert card image punches to ascii buf for processing + // keep 026 fortran charset + for (i=0;i<80;i++) { + c1 = data->image[i]; + c2 = data->hol_to_ascii[c1]; + c2 = toupper(c2); + c2 = (strchr(mem_to_ascii, c2)) ? c2:' '; + if (c2 == '~') c2 = ' '; + buf[i] = (char) c2; + } + buf[80] = 0; // terminate string + if (buf[72] == '+') { + // read data card input for READ fortransit command + // re-read as 8 word per card + decode_8word_wiring(data, 0); + return; + } else if (buf[4] == '+') { + // it source statement + IOSync[0] = decode_alpha_word(&buf[42], 5); // Statement (5 chars) + IOSync[1] = decode_alpha_word(&buf[47], 5); // Statement (5 chars) + IOSync[2] = decode_alpha_word(&buf[52], 5); // Statement (5 chars) + IOSync[3] = decode_alpha_word(&buf[57], 5); // Statement (5 chars) + IOSync[4] = decode_alpha_word(&buf[62], 5); // Statement (5 chars) + IOSync[5] = decode_alpha_word(&buf[67], 5); // Statement (5 chars) + + IOSync[6] = decode_num_word(&buf[0], 4, 1); // Statement Number (space is read as digit zero) + } else { + // fortran source statement + IOSync[0] = decode_alpha_word(&buf[6], 5); // Statement (5 chars) + IOSync[1] = decode_alpha_word(&buf[11], 5); // Statement (5 chars) + IOSync[2] = decode_alpha_word(&buf[16], 5); // Statement (5 chars) + IOSync[3] = decode_alpha_word(&buf[21], 5); // Statement (5 chars) + IOSync[4] = decode_alpha_word(&buf[26], 5); // Statement (5 chars) + IOSync[5] = decode_alpha_word(&buf[31], 5); // Statement (5 chars) + + IOSync[9] = ( (buf[0] == 'C') ? (t_int64) 80 * D8 : 0 ) + // is a comment card + ( ((buf[5] != ' ') && (buf[5] != 0)) ? (t_int64) 8 * D8 : 0 ) + // continuation line + ( decode_num_word(&buf[1], 4, 1) ); // statement number + } +} /* * Device entry points for card reader. */ @@ -510,13 +640,17 @@ uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 addr) uint32 wiring; int i; char cbuf[81]; + int ncdr, ic; /* Are we currently tranfering? */ if (uptr->u5 & URCSTA_BUSY) return SCPE_BUSY; - // clear read buffer in drum (where words read from cards will be stored) - for (i=0;i<10;i++) WriteDrum(addr + i, 0, 0); + // clear IO Sync buffer (where words read from cards will be stored) + for (i=0;i<10;i++) { + IOSync [i]=0; + IOSync_NegativeZeroFlag[i]=0; + } /* Test ready */ if ((uptr->flags & UNIT_ATT) == 0) { @@ -553,29 +687,40 @@ uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 addr) cbuf[80] = 0; // terminate string sim_debug(DEBUG_DETAIL, &cpu_dev, "Read Card: %s\n", sim_trim_endspc(cbuf)); + // save read card in last read card buffer to be eventually printed + // by carddec echolast scp command + ncdr = uptr - &cdr_unit[1]; // ncdr is the card reader: 0 for cdr1, 1 for cdr2, 2 for cdr3 + if ((ncdr >= 0) && (ncdr < 3)) { // safety check, not needed (should allways be true) but just to be sure + // advance read buffer last card + ReadHopperLast[ncdr] = (ReadHopperLast[ncdr] + 1) % MAX_CARDS_IN_READ_TAKE_HOPPER; + // save card in read card hopper buffer + ic = (ncdr * MAX_CARDS_IN_READ_TAKE_HOPPER + ReadHopperLast[ncdr]) * 80; + for (i=0; i<80; i++) ReadHopper[ic + i] = cbuf[i]; + } + // uint16 data->image[] array that holds the actual punched rows on card // using this codification: // // Row Name value in image[] comments // - // Y 0x800 Hi Punch Y(12) - // X 0x400 Minus Punch X(11) - // 0 0x200 also called T (Ten, 10) - // 1 0x100 - // 2 0x080 - // 3 0x040 - // 4 0x020 - // 5 0x010 - // 6 0x008 - // 7 0x004 - // 8 0x002 - // 9 0x001 + // Y 0x800 Hi Punch Y(12) + // X 0x400 Minus Punch X(11) + // 0 0x200 also called T (Ten, 10) + // 1 0x100 + // 2 0x080 + // 3 0x040 + // 4 0x020 + // 5 0x010 + // 6 0x008 + // 7 0x004 + // 8 0x002 + // 9 0x001 // // If several columns are punched, the values are ORed: eg char A is represented as a punch // on row Y and row 1, so it value in image array will be 0x800 | 0x100 -> 0x900 // check if it is a load card (Y(12) = HiPunch set on any column of card) signales it - if (decode_8word_wiring(data, -1)) { + if (decode_8word_wiring(data, 1)) { uptr->u5 |= URCSTA_LOAD; } else { uptr->u5 &= ~URCSTA_LOAD; @@ -583,27 +728,30 @@ uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 addr) wiring = (uptr->flags & UNIT_CARD_WIRING); - // translate chars read from card and copy to drum memory words + // translate chars read from card and copy to memory words // using the control panel wiring. if (uptr->u5 & URCSTA_LOAD) { // load card -> use 8 words per card encoding - decode_8word_wiring(data, addr); + decode_8word_wiring(data, 0); if (uptr->u5 & URCSTA_SOAPSYMB) { // requested to load soap symb info - decode_soap_symb_info(data, addr); + decode_soap_symb_info(data); } } else if (wiring == WIRING_SOAP) { // decode soap card simulating soap control panel wiring for 533 (gasp!) - decode_soap_wiring(data, addr); + decode_soap_wiring(data); } else if (wiring == WIRING_IS) { // decode floating point interpretive system (bell interpreter) card - decode_is_wiring(data, addr); + decode_is_wiring(data); } else if (wiring == WIRING_IT) { // decode Carnegie Internal Translator compiler card - decode_it_wiring(data, addr); + decode_it_wiring(data); + } else if (wiring == WIRING_FORTRANSIT) { + // decode Fortransit translator card + decode_fortransit_wiring(data); } else { // default wiring: decode up to 8 numerical words per card. Can be a load card - decode_8word_wiring(data, addr); + decode_8word_wiring(data, 0); } uptr->u5 &= ~URCSTA_BUSY; @@ -656,6 +804,7 @@ t_stat cdr_attach(UNIT * uptr, CONST char *file) { t_stat r; + int ncdr, ic1, ic2, i; if (uptr->flags & UNIT_ATT) // remove current deck in read hopper before attaching sim_card_detach(uptr); // the new one @@ -669,6 +818,17 @@ cdr_attach(UNIT * uptr, CONST char *file) if (sim_switches & SWMASK ('L')) { /* Load Symbolic SOAP info? */ uptr->u5 |= URCSTA_SOAPSYMB; } + // clear read card take hopper buffer + ncdr = uptr - &cdr_unit[1]; // ncdr is the card reader: 0 for cdr1, 1 for cdr2, 2 for cdr3 + if ((ncdr >= 0) && (ncdr < 3)) { // safety check, not needed (should allways be true) but just to be sure + // reset last read card number + ReadHopperLast[ncdr] = 0; + // clear buffer + ic1 = (ncdr * MAX_CARDS_IN_READ_TAKE_HOPPER) * 80; + ic2 = ic1 + MAX_CARDS_IN_READ_TAKE_HOPPER * 80; + for (i=ic1; i> UNIT_V_CPUMODEL) & 0x01) #define MODEL(x) (x << UNIT_V_CPUMODEL) #define MEMAMOUNT(x) (x << UNIT_V_MSIZE) -//XXX #define OPTION_FLOAT (1 << (UNIT_V_CPUMODEL + 1)) +#define OPTION_STOR (1 << (UNIT_V_CPUMODEL + 1)) +#define OPTION_CNTRL (1 << (UNIT_V_CPUMODEL + 2)) +#define OPTION_SOAPMNE (1 << (UNIT_V_CPUMODEL + 3)) +#define OPTION_FAST (1 << (UNIT_V_CPUMODEL + 4)) t_stat cpu_ex(t_value * vptr, t_addr addr, UNIT * uptr, int32 sw); t_stat cpu_dep(t_value val, t_addr addr, UNIT * uptr, int32 sw); @@ -98,12 +106,29 @@ t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, co t_stat cpu_svc (UNIT *uptr); const char *cpu_description (DEVICE *dptr); -t_int64 DRUM[MAXMEMSIZE] = {0}; -int DRUM_NegativeZeroFlag[MAXMEMSIZE] = {0}; -char DRUM_Symbolic_Buffer[MAXMEMSIZE * 80] = {0}; // does not exists on real hw. Used to keep symbolic info +// DRUM Memory +t_int64 DRUM[MAXDRUMSIZE] = {0}; +int DRUM_NegativeZeroFlag[MAXDRUMSIZE] = {0}; +char DRUM_Symbolic_Buffer[MAXDRUMSIZE * 80] = {0}; // does not exists on real hw. Used to keep symbolic info + +// IO Synchronizer for card read-punch buffer +t_int64 IOSync[10] = {0}; +int IOSync_NegativeZeroFlag[10] = {0}; + +// IAS Memory +t_int64 IAS[60] = {0}; +int IAS_NegativeZeroFlag[60] = {0}; +int IAS_TimingRing = 0; + +// interlock counters +int InterLockCount[IL_array] = {0}; + +// address where rotating drum is currently positioned (0-49) +int DrumAddr; // cpu registers uint16 IC; // Added register not part of cpu. Has addr of current intr in execution, just for displaying purposes. IBM 650 has no program counter +uint16 PROP; // Added register not part of cpu. Has operation code of current intr in execution, just for scp scripting purposes. Contains the two higher digits of PR register t_int64 ACC[2]; /* lower, upper accumulator. 10 digits (=one word) each*/ t_int64 DIST; /* ditributor. 10 digits */ t_int64 CSW = 0; /* Console Switches, 10 digits */ @@ -113,8 +138,10 @@ uint8 OV; /* Overflow flag */ uint8 CSWProgStop = 1; /* Console programmed stop switch */ uint8 CSWOverflowStop = 0; /* Console stop on overflow switch */ uint8 HalfCycle = 0; // set to 0 for normal run, =1 to execute I-Half-cycle, =2 to execute D-half-cycle +int ProgStopFlag = 0; // set to 1 if programmed stop was the previous inst executed int AccNegativeZeroFlag = 0; // set to 1 if acc has a negative zero int DistNegativeZeroFlag = 0; // set to 1 if distributor has a negative zero +int16 IR[3]; // Index registers. Are 4 digits as AR register, but signed /* CPU data structures @@ -130,7 +157,8 @@ UNIT cpu_unit = REG cpu_reg[] = { - {DRDATAD(IC, IC, 16, "Current Instruction"), REG_FIT}, + {DRDATAD(IC, IC, 16, "Current Instruction"), REG_FIT|REG_RO}, + {DRDATAD(PROP, PROP, 16, "Program Register Operation Code"), REG_FIT|REG_RO}, {HRDATAD(DIST, DIST, 64, "Distributor"), REG_VMIO|REG_FIT}, {HRDATAD(ACCLO, ACC[0], 64, "Lower Accumulator"), REG_VMIO|REG_FIT}, {HRDATAD(ACCUP, ACC[1], 64, "Upper Accumulator"), REG_VMIO|REG_FIT}, @@ -145,15 +173,23 @@ REG cpu_reg[] = { }; MTAB cpu_mod[] = { - {UNIT_MSIZE, MEMAMOUNT(0), "1K", "1K", &cpu_set_size}, - {UNIT_MSIZE, MEMAMOUNT(1), "2K", "2K", &cpu_set_size}, - {UNIT_MSIZE, MEMAMOUNT(2), "4K", "4K", &cpu_set_size}, + {UNIT_MSIZE, MEMAMOUNT(0), "1K", "1K", &cpu_set_size}, + {UNIT_MSIZE, MEMAMOUNT(1), "2K", "2K", &cpu_set_size}, + {UNIT_MSIZE, MEMAMOUNT(2), "4K", "4K", &cpu_set_size}, + {OPTION_STOR, 0, NULL, "NOSTORAGEUNIT", NULL}, + {OPTION_STOR, OPTION_STOR, "Storage Unit", "STORAGEUNIT", NULL}, + {OPTION_CNTRL, 0, NULL, "NOCNTRLUNIT", NULL}, + {OPTION_CNTRL, OPTION_CNTRL, "Control Unit", "CNTRLUNIT", NULL}, + {OPTION_SOAPMNE, 0, NULL, "DEFAULTMNE", NULL}, + {OPTION_SOAPMNE, OPTION_SOAPMNE, "Using SOAP Mnemonics", "SOAPMNE", NULL}, + {OPTION_FAST, 0, NULL, "REALTIME", NULL}, + {OPTION_FAST, OPTION_FAST, "Fast Execution", "FAST", NULL}, {0} }; DEVICE cpu_dev = { "CPU", &cpu_unit, cpu_reg, cpu_mod, - 1, 10, 12, 1, 10, 64, + 1, 10, 16, 1, 10, 64, &cpu_ex, &cpu_dep, &cpu_reset, NULL, NULL, NULL, NULL, DEV_DEBUG, 0, dev_debug, NULL, NULL, &cpu_help, NULL, NULL, &cpu_description @@ -168,57 +204,286 @@ t_stat cpu_svc (UNIT *uptr) } -// return 0 if drum addr invalid -int IsDrumAddrOk(int AR) +// return 0 if addr invalid, 1 if addr valid depending on allowed addrs given by ValidDA +// set the ias TimingRing to AR is IAS is accessed +int IsDrumAddrOk(int AR, int ValidDA) { - if ((AR < 0) || (AR >= (int)MEMSIZE) || (AR >= MAXMEMSIZE)) return 0; - return 1; + // check if AR should be 9000 + if ((STOR) && (ValidDA & vda_9000)) + return (AR == 9000) ? 1:0; + // Drum address + if ((AR >= 0) && (AR < DRUMSIZE)) + return (ValidDA & vda_D) ? 1:0; + // cpu registers: acc (lo&hi), distibutor, console swithc reg: ok to check for Addr validity, ok to read, cannot write to it + if ((AR >= 8000) && (AR <= 8003)) + return (ValidDA & vda_A) ? 1:0; + // index registers (ir) present if Storage Unit is enabled: ok to check for Addr validity, ok to read, cannot write to it + if ((STOR) && (AR >= 8005) && (AR <= 8007)) + return (ValidDA & vda_I) ? 1:0; + // tape address present is tapes are enabled: ok to check for Addr validity, cannot read/write to it + if ((CNTRL) && (AR >= 8010) && (AR <= 8015)) + return (ValidDA & vda_T) ? 1:0; + // inmediate access storage (ias) if Storage Unit is enabled: ok to check for Addr validity, ok to read/write + if ((STOR) && (AR >= 9000) && (AR <= 9059)) { + if (ValidDA & vda_S) { + IAS_TimingRing = AR - 9000; // set Timing ring on address accesed + return 1; + } + } + // none of the above -> invalid address or address/mode combination + return 0; } // return 0 if write addr invalid -int WriteDrum(int AR, t_int64 d, int NegZero) +int WriteAddr(int AR, t_int64 d, int NegZero) { - if (IsDrumAddrOk(AR) == 0) return 0; if (d) NegZero = 0; // sanity check on Minus Zero - DRUM[AR] = d; - DRUM_NegativeZeroFlag[AR] = NegZero; - return 1; -} - -// return 0 if drum addr invalid -int ReadDrum(int AR, t_int64 * d, int * NegZero) -{ - if (IsDrumAddrOk(AR) == 0) return 0; - *d = DRUM[AR]; - *NegZero = DRUM_NegativeZeroFlag[AR]; - if (*d) { - *NegZero = 0; // sanity check on Minus Zero - DRUM_NegativeZeroFlag[AR] = 0; + if ((STOR) && (AR >= 9000) && (AR <= 9059)) { // IAS is available at addr 9000-9059 + IAS_TimingRing = AR - 9000; // not necessary as before any call to WriteAddr IsAddrOk is invoked. But ... just in case + IAS[IAS_TimingRing] = d; + IAS_NegativeZeroFlag[IAS_TimingRing] = NegZero; + return 1; + } else if ((AR >= 0) && (AR < DRUMSIZE)) { + if (d) NegZero = 0; // sanity check on Minus Zero + DRUM[AR] = d; + DRUM_NegativeZeroFlag[AR] = NegZero; + return 1; } - return 1; + // none of the above -> invalid address or address/mode combination + return 0; } // return 0 if read addr invalid int ReadAddr(int AR, t_int64 * d, int * NegZero) { - int r; int neg; - if (AR == 8000) {*d = CSW; neg=0; r=1; } else - if (AR == 8001) {*d = DIST; neg=DistNegativeZeroFlag; r=1; } else - if (AR == 8002) {*d = ACC[0]; neg=AccNegativeZeroFlag; r=1; } else - if (AR == 8003) {*d = ACC[1]; neg=AccNegativeZeroFlag; r=1; } else - { r=ReadDrum(AR, d, &neg); } + // read from drum? + if ((AR >= 0) && (AR < DRUMSIZE)) { + *d = DRUM[AR]; + neg = DRUM_NegativeZeroFlag[AR]; + if (*d) DRUM_NegativeZeroFlag[AR] = 0; + } else + // read from cpu registers? + if (AR == 8000) {*d = CSW; neg=0; } else + if (AR == 8001) {*d = DIST; neg=DistNegativeZeroFlag; } else + if (AR == 8002) {*d = ACC[0]; neg=AccNegativeZeroFlag; } else + if (AR == 8003) {*d = ACC[1]; neg=AccNegativeZeroFlag; } else + // read index registers (ir) ? + if ((STOR) && (AR == 8005)) {*d = IR[0]; neg=0; } else + if ((STOR) && (AR == 8006)) {*d = IR[1]; neg=0; } else + if ((STOR) && (AR == 8007)) {*d = IR[2]; neg=0; } else + // tape address ? + if ((CNTRL) && (AR >= 8010) && (AR <= 8015)) { + // cannot read/write to tape addresses + return 0; + } else + // read inmediate access storage (ias)? + if ((STOR) && (AR >= 9000) && (AR <= 9059)) { + IAS_TimingRing = AR - 9000; + *d = IAS[IAS_TimingRing]; + neg = IAS_NegativeZeroFlag[IAS_TimingRing]; + if (*d) IAS_NegativeZeroFlag[IAS_TimingRing] = 0; + } else { + // none of the above -> invalid address for read + return 0; + } if (*d) neg = 0; // sanity check on Minus Zero if (NegZero != NULL) *NegZero = neg; - return r; + return 1; +} + +// shift acc 1 digit. If direction > 0 to the left, if direction < 0 to the right. +// Return digit going out of acc (with sign) +int ShiftAcc(int direction) +{ + t_int64 a0, a1; + int neg = 0; + int n, m; + + n = 0; + a1 = ACC[1]; if (a1 < 0) {a1 = -a1; neg = 1;} + a0 = ACC[0]; if (a0 < 0) {a0 = -a0; neg = 1;} + if ((AccNegativeZeroFlag) && (ACC[0] == 0) && (ACC[1] == 0)) neg = 1; + + if (direction > 0) { // shift left + n = Shift_Digits(&a1, 1); // n = Upper Acc high digit shifted out on the left + m = Shift_Digits(&a0, 1); // m = intermediate digit that goes from one acc to the other + a1 = a1 + (t_int64) m; + } else if (direction < 0) { // shift right + m = Shift_Digits(&a1, -1); // m = intermediate digit that goes from one acc to the other + n = Shift_Digits(&a0, -1); // n = Lower Acc units digit shifted out on the right + a0 = a0 + (t_int64) m * (1000000000L); + } + if (neg) {a1=-a1; a0=-a0; n=-n;} + + ACC[0] = a0; + ACC[1] = a1; + if ((neg == 1) && (a0 == 0) && (a1 == 0)) AccNegativeZeroFlag = 1; + return n; +} + + +// float value format = mmmmmmmcc = 0.m x 10^(c-50) +// mmmmmmm = mantissa +// cc = modified characteristic (== exponent) +// get modified characteristic of float d +int GetExp(t_int64 d) +{ + return (AbsWord(d) % 100); +} + +// set modified characteristic of float d +t_int64 SetExp(t_int64 d, int exp) +{ + int neg = 0; + + if (d < 0) {neg=1; d=-d;} + d = ((d / 100) * 100) + (exp % 100); + if (neg) d=-d; + return d; +} + +// set result into ACC[1] and ACC[0] for float mult and division +// get a 10 digits mantissa en ACC[1] +// round to the 8th digit +// add the modified characteristic (exp) +// add sign, check for zero +void MantissaRoundAndNormalizeToFloat(int * CpuStepsUsed, int neg, int exp) +{ + // if high order digit of mantissa is zero, shift left once + if (Get_HiDigit(ACC[1]) == 0) { + ShiftAcc(1); + *CpuStepsUsed = *CpuStepsUsed + 2; + if (exp == 0) { + OV = 1; + } else { + exp--; + } + } + // round mantissa in ACC[1] to the 8th digit + if (GetExp(ACC[1]) >= 50) { + ACC[1] = ACC[1] + 100; + if (ACC[1] >= D10) { + ACC[1] = ACC[1] / 10; + *CpuStepsUsed = *CpuStepsUsed + 2; + if (exp == 99) { + OV = 1; + } else { + exp++; + } + } + } + ACC[1] = SetExp(ACC[1], 0); + // normalize mantissas + while (( ACC[1] != 0) && (Get_HiDigit(ACC[1]) == 0)) { + if (exp == 0) { + OV = 1; + break; // if zero, underflow + } else { + exp--; + } + ACC[1] = ACC[1] * 10; + *CpuStepsUsed = *CpuStepsUsed + 2; + } + // set result + if (exp < 0) {exp += 100; OV = 1;} + if (exp > 99) {exp -= 100; OV = 1;} + ACC[1] = neg * SetExp(ACC[1], exp); + ACC[0] = 0; + if ((ACC[1] / 100) == 0) ACC[1] = 0; // if mantissa is zero, all is zero + AccNegativeZeroFlag = 0; +} + + +// add float to accumulator, set Overflow +// return number of steps used +int AddFloatToAcc(int bSubstractFlag, int bAbsFlag, int bNormalizeFlag) +{ + int nSteps; + int n, neg; + t_int64 d; + + OV = 0; AccNegativeZeroFlag = 0; + nSteps = 0; + + n = GetExp(ACC[1]) - GetExp(DIST); + if (n == 0) { + // no decimal aligning necessary. Mantissas ready to being added + } else if ( n > 8) { + DIST = ACC[1]; ACC[1] = 0; + } else if ( n < -8) { + ACC[1] = 0; + } else { + if (n < 0) { // if between -1 and -8 + n = -n; // just remove sign on number of shifts to be done + } else { // if between 1 and 8 + d = ACC[1]; + ACC[1] = DIST; DIST = d; // exchange distrib and upper acc + nSteps += 2; + } + ACC[1] = SetExp(ACC[1], 0); // modified characteristic of upper set to zero + while (n>0) { // shift right n digits + ShiftAcc(-1); + nSteps += 2; + n--; + } + if (GetExp(ACC[1]) >= 50) { // should round? + ACC[1] = ACC[1] + ((ACC[1] >= 0) ? 100:-100); + } + } + d = DIST; + if (bAbsFlag) if (d < 0) d = -d; + if (bSubstractFlag) d = -d; + + if (((ACC[1] > 0) && (d < 0)) || ((ACC[1] < 0) && (d > 0))) nSteps += 4; + + ACC[1] = (ACC[1] / 100) + (d / 100); // add/substract mantissas (positions 10-3) + n = GetExp(DIST); // get modified characteristic from dist + if (ACC[1] < 0) { + ACC[1] = -ACC[1]; neg=-1; + } else { + neg=1; + } + + if (ACC[1] >= D8) { // overflow? + if ((ACC[1] % 10) >= 5) { // should round? + ACC[1] = ACC[1] / 10 + 1; // yes, shift right, keep extra 1 in high pos, add rounding + nSteps += 4; + } else { + ACC[1] = ACC[1] / 10; // no, just shift + } + n++; // add 1 to dist modified characteristic + if (n > 99) {OV = 1; n=0;} // overflow. Set modified characteristic to zero + nSteps += 4; + } + + if (ACC[1] == 0) { + n = 0; // if mantissa is zero, mod. char is set to zero also + bNormalizeFlag = 0; // must not normalize + nSteps += 2; + } + ACC[1] = SetExp(neg * ACC[1] * 100, n); // insert modified characteristic of dist into upper acc + ACC[0] = 0; // lower acc set to zero + if (bNormalizeFlag) { + while(Get_HiDigit(ACC[1]) == 0) { // while hi digit (digit 10) is zero -> normalize + n = GetExp(ACC[1]); // get modified characteristic + if (n == 0) { + OV = 1; break; // if zero, underflow + } + n--; + ACC[1] = SetExp(ACC[1]/100 * 1000, n); // left shift mantissa, set modified characteristic + nSteps += 3; + } + } + return nSteps; } int bAccNegComplement; // flag to signals acc has complemented a negative ass (== sign adjust) // needed to compute execution cycles taken by the intruction // add to accumulator, set Overflow -void AddToAcc(t_int64 a1, t_int64 a0) +void AddToAcc(t_int64 a1, t_int64 a0, int bSetOverflow) { OV = 0; AccNegativeZeroFlag = 0; bAccNegComplement = 0; @@ -241,41 +506,14 @@ void AddToAcc(t_int64 a1, t_int64 a0) } // check overflow - if ((ACC[1] >= D10) || (ACC[1] <= -D10)) { - ACC[1] = ACC[1] % D10; - OV=1; + if (bSetOverflow) { + if ((ACC[1] >= D10) || (ACC[1] <= -D10)) { + ACC[1] = ACC[1] % D10; + OV=1; + } } } -// shift acc 1 digit. If direction > 0 to the left, if direction < 0 to the right. -// Return overflow digit (with sign) -int ShiftAcc(int direction) -{ - t_int64 a0, a1; - int neg = 0; - int n, m; - - n = 0; - a1 = ACC[1]; if (a1 < 0) {a1 = -a1; neg = 1;} - a0 = ACC[0]; if (a0 < 0) {a0 = -a0; neg = 1;} - - if (direction > 0) { // shift left - n = Shift_Digits(&a1, 1); // n = Upper Acc high digit shifted out on the left - m = Shift_Digits(&a0, 1); // m = intermediate digit that goes from one acc to the other - a1 = a1 + (t_int64) m; - } else if (direction < 0) { // shift right - m = Shift_Digits(&a1, -1); // m = intermediate digit that goes from one acc to the other - n = Shift_Digits(&a0, -1); // n = Lower Acc units digit shifted out on the right - a0 = a0 + (t_int64) m * (1000000000L); - } - if (neg) {a1=-a1; a0=-a0; n=-n;} - - ACC[0] = a0; - ACC[1] = a1; - if ((neg == 1) && (a0 == 0) && (a1 == 0)) AccNegativeZeroFlag = 1; - return n; -} - t_int64 SetDA(t_int64 d, int DA) { @@ -324,41 +562,111 @@ t_int64 SetIA2(t_int64 d, int n) return d; } +// normalize to 4 digits, 10 complements +void NormalizeAddr(int * addr) +{ + while (*addr >= 10000) *addr -= 10000; + while (*addr < 0) *addr += 10000; +} + +// apply index register to a tagged address +// removes tag, replace value with developed address +// return 1 if address was tagged, and has been replaced by developed addr +int ApplyIndexRegister(int * addr) +{ + int n = 0; + int norm = 0; + + // check for tag and untag + if ((*addr >= 2000) && (*addr < 4000)) {n = 1; norm = 2000; } else + if ((*addr >= 4000) && (*addr < 6000)) {n = 2; norm = 4000; } else + if ((*addr >= 6000) && (*addr < 8000)) {n = 3; norm = 6000; } else + if ((*addr >= 9200) && (*addr < 9260)) {n = 1; norm = 200; } else + if ((*addr >= 9400) && (*addr < 9460)) {n = 2; norm = 400; } else + if ((*addr >= 9600) && (*addr < 9660)) {n = 3; norm = 600; } else + return 0; // address not tagged + + *addr = *addr + IR[n-1] - norm; + NormalizeAddr(addr); + + return 1; +} + // opcode decode // input: prior to call DecodeOpcode PR cpu register must be loaded with the word to decode // output: decoded instruction as opcode, DA, IA parts -// bReadDrum: =1 if instruction needes to read data from drum before execution // returns opname: points to opcode name or NULL if undef opcode -CONST char * DecodeOpcode(int * opcode, int * DA, int * IA, int * bReadData) +CONST char * DecodeOpcode(t_int64 d, int * opcode, int * DA, int * IA) { - t_int64 d; CONST char * opname; - d = PR; *opcode = Shift_Digits(&d, 2); // current inste opcode *DA = Shift_Digits(&d, 4); // addr of data used by current instr *IA = Shift_Digits(&d, 4); // addr of next instr - opname = get_opcode_data(*opcode, bReadData); + + opname = (cpu_unit.flags & OPTION_SOAPMNE) ? base_ops[*opcode].name2 : base_ops[*opcode].name1; + if (base_ops[*opcode].option == opStorUnit) { + // opcode available if IBM 653 Storage Unit is present + if (STOR == 0) return NULL; + } else if (base_ops[*opcode].option == opCntrlUnit) { + // opcode available if IBM 652 Control Unit is present + if (CNTRL == 0) return NULL; + } return opname; } +// transfer (copy words) between IAS and DRUM +// dir = "D->I" or "I->D" +// bEOB = 1 -> End of IAS band terminated transfer +// return number of words transfered +int TransferIAS(CONST char * dir, int bEOB) +{ + int n, f0, t0, f1, t1, ec; + + n = f0 = t0 = f1 = t1 = ec = 0; + while (1) { + if (dir[0] == 'D') { + IAS[IAS_TimingRing] = DRUM[AR]; + IAS_NegativeZeroFlag[IAS_TimingRing] = DRUM_NegativeZeroFlag[AR]; + if (n==0) {f0=AR; t0=IAS_TimingRing;} + f1=AR; t1=IAS_TimingRing; + } else { + DRUM[AR] = IAS[IAS_TimingRing]; + DRUM_NegativeZeroFlag[AR] = IAS_NegativeZeroFlag[IAS_TimingRing]; + if (n==0) {t0=AR; f0=IAS_TimingRing;} + t1=AR; f1=IAS_TimingRing; + } + n++; + if ((AR % 50) == 49) { ec = 0; break; } + if (IAS_TimingRing == 9059) { ec = 1; break; } + if ((bEOB) && ((IAS_TimingRing % 10) == 9)) { ec = 2; break; } + AR++; IAS_TimingRing++; + } + sim_debug(DEBUG_DATA, &cpu_dev, " ... Copy %04d-%04d to %04d-%04d (%d words)\n", + f0, f1, t0, t1, n); + sim_debug(DEBUG_DATA, &cpu_dev, " ended by end of %s condition\n", + (ec == 0) ? "Drum band" : (ec == 1) ? "IAS" : "IAS Block"); + IAS_TimingRing = (IAS_TimingRing + 1) % 60; // incr timing ring at end of pch + return n; +} + + // opcode execution // input: opcode, DA (data address), DrumAddr (current word under the r/w heads. Needed to calculate time used on instr execution) // prior to call ExecOpcode DIST cpu register must be loaded with the needed data for inst execution -// output: bWriteDrum: =1 if DIST must be written back to drum -// bBranchToDA: =1 if next inst must be taken from DA register instead of DA +// output: bBranchToDA: =1 if next inst must be taken from DA register instead of DA // CpuStepsUsed: number of steps (=word time) used on program execution t_stat ExecOpcode(int opcode, int DA, - int * bWriteDrum, int * bBranchToDA, + int * bBranchToDA, int DrumAddr, int * CpuStepsUsed) { t_stat reason = 0; t_int64 d; int i, n, neg; + int bUsingIAS; *bBranchToDA = 0; - *bWriteDrum = 0; *CpuStepsUsed = 0; switch(opcode) { @@ -368,10 +676,10 @@ t_stat ExecOpcode(int opcode, int DA, case OP_STOP : // Stop if console switch is set to stop, otherwise continue as a NO-OP if (CSWProgStop) { reason = STOP_PROG; - // normal stops has the consequence to prevent AR to be set with IA contents (to point to next instruction). - // but STOP allows the user to resume execution with program start key on console (= scp go command) - // so to allow this here we must explicitelly update AR - AR = (PR % D4); + // stops has the consequence to prevent AR to be set with IA contents (to point to next instruction). + // so must set a flag so next setp/go scp command will take next inst to execute from + // IA field in PR reg instead of AR + ProgStopFlag = 1; } break; // arithmetic @@ -416,7 +724,7 @@ t_stat ExecOpcode(int opcode, int DA, d = DIST; if ((opcode == OP_AABL) || (opcode == OP_SABL)) d = AbsWord(d); if ((opcode == OP_SL) || (opcode == OP_SABL)) d = -d; - AddToAcc(0,d); + AddToAcc(0,d,1); sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\n", printfa, OV); @@ -441,7 +749,7 @@ t_stat ExecOpcode(int opcode, int DA, d = DIST; if ((opcode == OP_RAU) || (opcode == OP_RSU)) ACC[1] = ACC[0] = 0; if ((opcode == OP_SU) || (opcode == OP_RSU)) d = -d; - AddToAcc(d,0); + AddToAcc(d,0,1); sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\n", printfa, OV); @@ -461,12 +769,13 @@ t_stat ExecOpcode(int opcode, int DA, // Acc result on minus zero if a drum location that contains minus zero // is multiplied by +1 OV = 0; - sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: 0000000000 0000000000- (Minus Zero), OV: 0\n"); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Mult result ACC: 0000000000 0000000000- (Minus Zero), OV: 0\n"); // acc set to minus zero ACC[1] = ACC[0] = 0; AccNegativeZeroFlag = 1; break; } + *CpuStepsUsed = 0; OV = 0; neg = (DIST < 0) ? 1:0; if (AccNegative) neg = 1-neg; d = AbsWord(DIST); @@ -474,8 +783,10 @@ t_stat ExecOpcode(int opcode, int DA, ACC[1] = AbsWord(ACC[1]); for(i=0;i<10;i++) { n = ShiftAcc(1); + *CpuStepsUsed = *CpuStepsUsed + 2; while (n-- > 0) { - AddToAcc(0, d); + AddToAcc(0, d, 1); + *CpuStepsUsed = *CpuStepsUsed + 18; if (OV) break; } if (OV) break; @@ -496,7 +807,7 @@ t_stat ExecOpcode(int opcode, int DA, // Signal Inst *CpuStepsUsed = 1+1+1+1 +(DrumAddr % 2) // wait for even - +20*(i+1); // i holds the number of loops done + +*CpuStepsUsed; // i holds the number of loops done break; case OP_DIV: // Divide case OP_DIVRU: // Divide and reset upper accumulator @@ -508,20 +819,25 @@ t_stat ExecOpcode(int opcode, int DA, if (DIST == 0) { OV = 1; sim_debug(DEBUG_DETAIL, &cpu_dev, "Divide By Zero -> OV set\n"); + reason = STOP_OV; // divisor zero allways stops the machine } else if (AbsWord(DIST) <= AbsWord(ACC[1])) { OV = 1; sim_debug(DEBUG_DETAIL, &cpu_dev, "Quotient Overflow -> OV set and ERROR\n"); reason = STOP_OV; // quotient overfow allways stops the machine } else { + *CpuStepsUsed = 0; OV = 0; neg = (DIST < 0) ? 1:0; if (AccNegative) neg = 1-neg; d = AbsWord(DIST); ACC[0] = AbsWord(ACC[0]); ACC[1] = AbsWord(ACC[1]); for(i=0;i<10;i++) { - ShiftAcc(1); + n = ShiftAcc(1); + ACC[1] = ACC[1] + n * D10; + *CpuStepsUsed = *CpuStepsUsed + 2; while (d <= ACC[1]) { - AddToAcc(-d, 0); + AddToAcc(-d, 0, 0); + *CpuStepsUsed = *CpuStepsUsed + 18; ACC[0]++; } } @@ -534,7 +850,7 @@ t_stat ExecOpcode(int opcode, int DA, } *CpuStepsUsed = 1+1+1+1 +(DrumAddr % 2) // wait for even - +20*(i+1) + 40; // i holds the number of loops done + +*CpuStepsUsed + 40; // i holds the number of loops done } sim_debug(DEBUG_DETAIL, &cpu_dev, "... Div result ACC: %06d%04d %06d%04d%c, OV: %d\n", printfa, @@ -544,14 +860,15 @@ t_stat ExecOpcode(int opcode, int DA, case OP_SLT: // Shift Left case OP_SRT: // Shift Right case OP_SRD: // Shift Right and Round - n = DA % 10; // number of digits to shift + n = DA % 10; // number of digits to shift + if (opcode == OP_SRD) if (n == 0) n=10; // SRD 0000 means 10 sifts. SRT/SLT 0000 means no shifts d = 0; while (n-- > 0) { d = ShiftAcc((opcode == OP_SLT) ? 1:-1); } if (opcode == OP_SRD) { - if (d <= - 5) AddToAcc(0,-1); - if (d >= 5) AddToAcc(0,+1); + if (d <= - 5) AddToAcc(0,-1,1); + if (d >= 5) AddToAcc(0,+1,1); OV = 0; } sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\n", @@ -570,7 +887,10 @@ t_stat ExecOpcode(int opcode, int DA, + ((opcode == OP_SRD) ? 1:0); break; case OP_SCT : // Shift accumulator left and count - n = 10 - DA % 10; // shift count (nine's complement of unit digit of DA) + n = 10 - DA % 10; // shift count (nine's complement of unit digit of DA) + neg = AccNegative; // save acc sign + ACC[0] = AbsWord(ACC[0]); + ACC[1] = AbsWord(ACC[1]); if (n==10) n=0; if (ACC[1] == 0) { // upper acc is zero -> will have 10 or more shifts @@ -593,9 +913,10 @@ t_stat ExecOpcode(int opcode, int DA, } n++; } - ACC[0] = SetIA2(ACC[0], n); // replace last two digits by 00 + ACC[0] = SetIA2(ACC[0], n); // replace last two digits by 00 } AccNegativeZeroFlag = 0; + if (neg) {ACC[0] = -ACC[0]; ACC[1] = -ACC[1]; } sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\n", printfa, OV); @@ -612,7 +933,7 @@ t_stat ExecOpcode(int opcode, int DA, DistNegativeZeroFlag = 0; } DIST = (opcode == OP_STU) ? ACC[1] : ACC[0]; - *bWriteDrum = 1; // to write DIST in drum at AR + // sequence chart for store // (1) (0/1) (1) (0..49) (1) (1) (1) // Enable Wait L/U acc Search Store IA to AR Enable PR @@ -622,7 +943,6 @@ t_stat ExecOpcode(int opcode, int DA, + (((opcode == OP_STU) ? DrumAddr:DrumAddr+1) % 2); // wait for odd/even depending on STU/STL opcode break; case OP_STD: // store distributor - *bWriteDrum = 1; // to write DIST in drum at AR *CpuStepsUsed = 1+1+1+1; break; case OP_STDA: // Store Lower Data Address @@ -636,7 +956,6 @@ t_stat ExecOpcode(int opcode, int DA, DistNegativeZeroFlag = 0; } DIST = d; - *bWriteDrum = 1; // to write DIST in drum at AR *CpuStepsUsed = 1+1+1+1 +(DrumAddr % 2); // wait for even break; @@ -651,38 +970,50 @@ t_stat ExecOpcode(int opcode, int DA, DistNegativeZeroFlag = 0; } DIST = d; - *bWriteDrum = 1; // to write DIST in drum at AR *CpuStepsUsed = 1+1+1+1 +(DrumAddr % 2); // wait for even break; case OP_LD: // Load Distributor *CpuStepsUsed = 1+1+1+1; break; - case OP_TLU : // Table lookup - sim_debug(DEBUG_DETAIL, &cpu_dev, "... Search DIST: %06d%04d%c\n", - printfd); + case OP_TLU: // Table lookup + { + char s[6]; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Search DIST: %06d%04d%c '%s'\n", + printfd, + word_to_ascii(s, 1, 5, DIST)); - AR = (DA / 50) * 50; // set AR to start of band based on DA - AR--; n=-1; - while (1) { - AR++; n++; - if (0==IsDrumAddrOk(AR)) { - sim_debug(DEBUG_DETAIL, &cpu_dev, "Invalid AR addr %d ERROR\n", AR); - reason = STOP_ADDR; - break; + bUsingIAS = (AR >= 9000) ? 1:0; + if (bUsingIAS) { + AR = DA; // if TLU is searching on IAS, search starts at given addr + } else { + AR = (DA / 50) * 50; // set AR to start of drum band based on DA } - if ((AR % 50) > 47) continue; // skip addr 48 & 49 of band that cannot be used for tables - if (0==ReadAddr(AR, &d, NULL)) { // read table argument - reason = STOP_ADDR; - break; + AR--; n=-1; + while (1) { + AR++; n++; + if (0==IsDrumAddrOk(AR, vda_DS)) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "Invalid AR addr %d ERROR\n", AR); + reason = STOP_ADDR; + break; + } + if ((bUsingIAS == 0) && ((AR % 50) > 47)) continue; // skip addr 48 & 49 of band that cannot be used for tables + ReadAddr(AR, &d, NULL); // read table argument + if (AbsWord(d) >= AbsWord(DIST)) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Found %04d: %06d%04d%c '%s'\n", + AR, printfw(d,0), + word_to_ascii(s, 1, 5, d)); + break; // found + } } - if (AbsWord(d) >= AbsWord(DIST)) break; // found + // if tlu on ias, incr timing ring at end of instr execution + if (bUsingIAS) IAS_TimingRing = (IAS_TimingRing + 1) % 60; + // set the result as xxNNNNxxxx in lower acc + ACC[0] = SetDA(ACC[0], DA+n); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Result ACC: %06d%04d %06d%04d%c, OV: %d\n", + printfa, + OV); } - // set the result as xxNNNNxxxx in lower acc - ACC[0] = SetDA(ACC[0], DA+n); - sim_debug(DEBUG_DETAIL, &cpu_dev, "... Result ACC: %06d%04d %06d%04d%c, OV: %d\n", - printfa, - OV); *CpuStepsUsed = 1+1+1+1+1+1 +(DrumAddr % 2) // wait for even + n; // number of reads to find the argument searched for @@ -728,7 +1059,7 @@ t_stat ExecOpcode(int opcode, int DA, printfa, OV); if ((ACC[1] != 0) || (ACC[0] != 0)) { - sim_debug(DEBUG_DETAIL, &cpu_dev, "ACC not Zero -> Branch Taken\n"); + sim_debug(DEBUG_DETAIL, &cpu_dev, "Not Zero -> Branch Taken\n"); *bBranchToDA = 1; } *CpuStepsUsed = 1 @@ -740,7 +1071,7 @@ t_stat ExecOpcode(int opcode, int DA, printfa, OV); if (AccNegative) { - sim_debug(DEBUG_DETAIL, &cpu_dev, "ACC is Negative -> Branch Taken\n"); + sim_debug(DEBUG_DETAIL, &cpu_dev, "Is Negative -> Branch Taken\n"); *bBranchToDA = 1; } *CpuStepsUsed = 1+1 @@ -756,51 +1087,288 @@ t_stat ExecOpcode(int opcode, int DA, + ((*bBranchToDA) ? 1:0); // one extra step needed if branch taken break; // Card I/O - case OP_RD : // Read a card - AR = (DA / 50) * 50 + 1; // Read Band is XX01 to XX10 or XX51 to XX60 + case OP_RD: // Read a card + bUsingIAS = (AR >= 9000) ? 1:0; { - uint32 r; - int i; char s[6]; - r = cdr_cmd(&cdr_unit[1], IO_RDS,AR); - if (r == SCPE_NOCARDS) { + if (bUsingIAS == 0) { + AR = (DA / 50) * 50 + 1; // Drum Read Band is XX01 to XX10 or XX51 to XX60 + } + + reason = cdr_cmd(&cdr_unit[1], IO_RDS, AR); + if (reason == SCPE_NOCARDS) { reason = STOP_CARD; break; + } else if (reason != SCPE_OK) { + break; } + // copy card data from IO Sync buffer to drum/ias for (i=0;i<10;i++) { sim_debug(DEBUG_DETAIL, &cpu_dev, "... Read Card %04d: %06d%04d%c '%s'\n", - AR+i, printfw(DRUM[AR+i],DRUM_NegativeZeroFlag[AR+i]), - word_to_ascii(s, 1, 5, DRUM[AR+i])); + AR+i, printfw(IOSync[i],IOSync_NegativeZeroFlag[i]), + word_to_ascii(s, 1, 5, IOSync[i])); + if (bUsingIAS == 0) { + DRUM[AR + i] = IOSync[i]; + DRUM_NegativeZeroFlag[AR + i] = IOSync_NegativeZeroFlag[i]; + } else { + n = AR - 9000 + i; + IAS[n] = IOSync[i]; + IAS_NegativeZeroFlag[n] = IOSync_NegativeZeroFlag[i]; + if ((n % 10) == 9) break; // hit ias end of block, terminate read even if transfered less than 10 words + } } + if (bUsingIAS) IAS_TimingRing = DA; // is using ias, set timing ring on instr completition if (cdr_unit[1].u5 & URCSTA_LOAD) { sim_debug(DEBUG_DETAIL, &cpu_dev, "... Is a LOAD Card\n"); - *bBranchToDA = 1; // load card -> next inste is taken from DA + *bBranchToDA = 1; // load card -> next instr is taken from DA } } // 300 msec read cycle, 270 available for computing - *CpuStepsUsed = 312; // 30 msec / 0.096 msec word time; + *CpuStepsUsed = 312; // 30 msec div 0.096 msec word time; + InterLockCount[IL_RD1] = 3120; // 300 msec for read card processing break; - case OP_PCH : // Punch a card - AR = (DA / 50) * 50 + 27; // Read Band is XX27 to XX36 or XX77 to XX86 + case OP_PCH: // Punch a card + bUsingIAS = (AR >= 9000) ? 1:0; { - uint32 r; - int i; char s[6]; - for (i=0;i<10;i++) { - sim_debug(DEBUG_DETAIL, &cpu_dev, "... Punch Card %04d: %06d%04d%c '%s'\n", - AR+i, printfw(DRUM[AR+i],DRUM_NegativeZeroFlag[AR+i]), - word_to_ascii(s, 1, 5, DRUM[AR+i])); + if (bUsingIAS == 0) { + AR = (DA / 50) * 50 + 27; // Drum Read Band is XX27 to XX36 or XX77 to XX86 } - r = cdp_cmd(&cdp_unit[1], IO_WRS,AR); - if (r == SCPE_NOCARDS) { + + // clear IO Sync buffer + for (i=0;i<10;i++) IOSync[i] = IOSync_NegativeZeroFlag[i] = 0; + // copy card data to IO Sync buffer from drum/ias + for (i=0;i<10;i++) { + if (bUsingIAS == 0) { + IOSync[i] = DRUM[AR + i]; + IOSync_NegativeZeroFlag[i] = DRUM_NegativeZeroFlag[AR + i]; + } else { + n = AR - 9000 + i; + IOSync[i] = IAS[n]; + IOSync_NegativeZeroFlag[i] = IAS_NegativeZeroFlag[n]; + IAS_TimingRing = i; + if ((n % 10) == 9) break; // hit ias end of block, terminate even if transfered less than 10 words + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Punch Card %04d: %06d%04d%c '%s'\n", + AR+i, printfw(IOSync[i],IOSync_NegativeZeroFlag[i]), + word_to_ascii(s, 1, 5, IOSync[i])); + } + + reason = cdp_cmd(&cdp_unit[1], IO_WRS,AR); + if (reason == SCPE_NOCARDS) { reason = STOP_CARD; break; + } else if (reason != SCPE_OK) { + break; } + if (bUsingIAS) IAS_TimingRing = (IAS_TimingRing + 1) % 60; // incr timing ring at end of pch } // 600 msec punch cycle, 565 available for computing - *CpuStepsUsed = 365; // 35 msec / 0.096 msec word time; + *CpuStepsUsed = 365; // 35 msec div 0.096 msec word time; + InterLockCount[IL_WR1] = 6250; // 600 msec for punch card processing + break; + // IAS - Immediate Access Storage + case OP_SET: // Set IAS Timing Ring + *CpuStepsUsed = 1+1+1; + break; + case OP_LDI: // Load IAS (from Drum) + n = TransferIAS("D->I", 0); // transfer drum to ias, end of ias block does not terminate transfer + *CpuStepsUsed = 1+1+1+n; + break; + case OP_STI: // Store IAS (to Drum) + n = TransferIAS("I->D", 0); // transfer ias to drum, end of ias block does not terminate transfer + *CpuStepsUsed = 1+1+1+n; + break; + case OP_LIB: // Load IAS Block (from Drum) + n = TransferIAS("D->I", 1); // transfer drum to ias, end of ias block does not terminate transfer + *CpuStepsUsed = 1+1+1+n; + break; + case OP_SIB: // Store IAS Block (to Drum) + n = TransferIAS("I->D", 1); // transfer ias to drum, end of ias block does not terminate transfer + *CpuStepsUsed = 1+1+1+n; + break; + // Index Register + case OP_AXA: // Add/Substract [with reset] to IRA + case OP_SXA: + case OP_RAA: + case OP_RSA: + n = IR[0]; + if ((opcode == OP_RAA) || (opcode == OP_RSA)) n = 0; + if (DA >= 8000) { + ReadAddr(DA, &d, NULL); + i = (int) (d % D4); + } else { + i = DA; + } + n = n + (((opcode == OP_AXA) || (opcode == OP_RAA)) ? i : -i); + NormalizeAddr(&n); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... IRA: %04d\n", + n); + IR[0] = n; + *CpuStepsUsed = 1+1+1; + break; + case OP_AXB: // Add/Substract [with reset] to IRB + case OP_SXB: + case OP_RAB: + case OP_RSB: + n = IR[1]; + if ((opcode == OP_RAB) || (opcode == OP_RSB)) n = 0; + if (DA >= 8000) { + ReadAddr(DA, &d, NULL); + i = (int) (d % D4); + } else { + i = DA; + } + n = n + (((opcode == OP_AXB) || (opcode == OP_RAB)) ? i : -i); + NormalizeAddr(&n); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... IRB: %04d\n", + n); + IR[1] = n; + *CpuStepsUsed = 1+1+1; + break; + case OP_AXC: // Add/Substract [with reset] to IRC + case OP_SXC: + case OP_RAC: + case OP_RSC: + n = IR[2]; + if ((opcode == OP_RAC) || (opcode == OP_RSC)) n = 0; + if (DA >= 8000) { + ReadAddr(DA, &d, NULL); + i = (int) (d % D4); + } else { + i = DA; + } + n = n + (((opcode == OP_AXC) || (opcode == OP_RAC)) ? i : -i); + NormalizeAddr(&n); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... IRC: %04d\n", + n); + IR[2] = n; + *CpuStepsUsed = 1+1+1; + break; + case OP_BMA: // Branch on IR Minus + case OP_BMB: + case OP_BMC: + i = ((opcode == OP_BMA) ? 0 : (opcode == OP_BMB) ? 1 : 2); + n = IR[i]; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... IR%c: %04d\n", + i+'A', n); + if (n<0) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "Is Negative -> Branch Taken\n"); + *bBranchToDA = 1; + } + *CpuStepsUsed = 1+1 + + ((*bBranchToDA) ? 1:0); // one extra step needed if branch taken + break; + case OP_NZA: // Branch on IR Zero + case OP_NZB: + case OP_NZC: + i = ((opcode == OP_NZA) ? 0 : (opcode == OP_NZB) ? 1 : 2); + n = IR[i]; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... IR%c: %04d\n", + i+'A', n); + if (n==0) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "Is Zero -> Branch Taken\n"); + *bBranchToDA = 1; + } + *CpuStepsUsed = 1+1 + + ((*bBranchToDA) ? 1:0); // one extra step needed if branch taken + break; + // floating point + case OP_FAD: // FP Add + case OP_UFA: // Unnormalized FP Add + case OP_FSB: // FP Sub + case OP_FAM: // FP Add Absolute value + case OP_FSM: // FP Sub Absolute + n = AddFloatToAcc((opcode == OP_FSB) || (opcode == OP_FSM), // subtract? + (opcode == OP_FAM) || (opcode == OP_FSM), // absolute value? + (opcode != OP_UFA) // normalize? + ); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d, DIST: %06d%04d%c\n", + printfa, OV, printfd); + *CpuStepsUsed = 1+1 + +(DrumAddr % 2) // using upper acc -> wait for even + +2+2+2+1 + +n; // Float Add steps + break; + case OP_FMP: // Float Multiply + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Mult ACC: %06d%04d %06d%04d%c, OV: %d\n", + printfa, + OV); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... by DIST: %06d%04d%c\n", + printfd); + OV = 0; + if (((ACC[1] / 100) == 0) || ((DIST / 100) == 0)) { + // if any mantissa is zero -> multiply by zero -> result = 0 + ACC[1] = ACC[0] = 0; + } else { + int exp = GetExp(DIST) + GetExp(ACC[1]) - 50; + + neg = (DIST < 0) ? -1:1; if (AccNegative) neg = -neg; + ACC[1] = SetExp(AbsWord(ACC[1]), 0); + d = SetExp(AbsWord(DIST), 0); + // mult mantissas + for(i=0;i<10;i++) { + n = ShiftAcc(1); + *CpuStepsUsed = *CpuStepsUsed + 2; + while (n-- > 0) { + AddToAcc(0, d, 1); + *CpuStepsUsed = *CpuStepsUsed + 18; + if (OV) break; + } + if (OV) break; + } + MantissaRoundAndNormalizeToFloat(CpuStepsUsed, neg, exp); + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... FP Mult result ACC: %06d%04d %06d%04d%c, OV: %d\n", + printfa, + OV); + *CpuStepsUsed = 1+1+2+2+2+1+ *CpuStepsUsed + +(DrumAddr % 2); // wait for even + break; + case OP_FDV: // Float Divide + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Div ACC: %06d%04d %06d%04d%c, OV: %d\n", + printfa, + OV); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... by DIST: %06d%04d%c\n", + printfd); + OV = 0; + if ((DIST / 100) == 0) { // check mantissa for zero, not exponent + OV = 1; + sim_debug(DEBUG_DETAIL, &cpu_dev, "Divide By Zero -> OV set and ERROR\n"); + reason = STOP_OV; // float divisor zero allways stops the machine + } else if ((ACC[1] / 100) == 0) { + // if dividend is zero -> result = 0 + ACC[1] = ACC[0] = 0; + } else { + int exp = GetExp(ACC[1]) - GetExp(DIST) + 50; + + neg = (DIST < 0) ? -1:1; if (AccNegative) neg = -neg; + + ACC[1] = AbsWord(ACC[1]) / 100; + d = AbsWord(DIST) / 100; + // div mantissas + for(i=0;;i++) { + while (d <= ACC[1]) { + AddToAcc(-d, 0, 0); + *CpuStepsUsed = *CpuStepsUsed + 18; + ACC[0] = ACC[0] + 10; // add to second position of lower + } + if (i > 8) break; + if ((i == 8) && (Get_HiDigit(ACC[0]))) {exp++; break;} + n = ShiftAcc(1); + ACC[1] = ACC[1] + n * D10; // extra digit + *CpuStepsUsed = *CpuStepsUsed + 2; + } + ACC[1] = ACC[0]; + MantissaRoundAndNormalizeToFloat(CpuStepsUsed, neg, exp); + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... FP Div result ACC: %06d%04d %06d%04d%c, OV: %d\n", + printfa, + OV); + *CpuStepsUsed = 1+1+2+2+16+2+1+ *CpuStepsUsed + +(DrumAddr % 2); // wait for even break; default: reason = STOP_UUO; @@ -811,6 +1379,17 @@ t_stat ExecOpcode(int opcode, int DA, return reason; } +// return 1 if must wait for storage +int WaitForStorage(int AR) +{ + if ((AR >= 0) && (AR < DRUMSIZE)) { + if ((AR % 50) != DrumAddr) return 1; // yes, must wait for drum + } else if ((STOR) && (AR >= 9000) && (AR < 9060)) { + if (InterLockCount[IL_IAS] > 0) return 1; // yes, IAS was interlocked. Must wait until interlock is released + } + return 0; +} + t_stat sim_instr(void) { @@ -820,15 +1399,10 @@ sim_instr(void) int instr_count = 0; /* Number of instructions to execute */ const char * opname; /* points to opcode name */ - int IA = 0; // Instr Address: addr of next inst - int DA = 0; // Data Address; addr of data to be used by current inst + int IA = 0; // Instr Address: addr of next inst + int DA = 0; // Data Address; addr of data to be used by current inst - int DrumAddr; // address where drum is currently positioned (0-49) - int MachineCycle, CpuStepsUsed, WaitForInterlock; - - #define IL_RD1 1 // interlock on drum area 01-10/51-60 used in reading with RD1 - #define IL_WR1 2 // interlock on drum area 27-36/77-86 used in writing for WR1 - int InterLockCount[3]; // interlock counters + int MachineCycle, CpuStepsUsed, il, WaitForInterlock; /* How CPU execution is simulated @@ -844,20 +1418,27 @@ sim_instr(void) SimH Real hw equivalent machine cycle half cycle - 0 I-Cycle wait for drum to be positioned at address given by AR cpu register - 1 I-Cycle read the drum to PR register, - decode as opcode, DA, IA, - check if must wait for interlock - if decoded opcode reads data from drum set AR=DA - 2 D-Cycle wait for interlock if needed - wait for drum to be positioned at AR address if decoded opcode reads data from drum - 3 D-Cycle if decoded opcode reads data from drum, read the data in DIST - set interlock if needed - perform opcode operation - 4 D-Cycle wait opcode excution time - wait for drum to be positioned at AR addressif executed opcode writes data to drum - 5 D-Cycle if executed opcode writes data to drum, write DIST to drum - set AR=IA to read next instruction + 0 I-Cycle WAIT FOR INSTR: + wait for drum to be positioned at address given by AR cpu register + 1 I-Cycle FETCH INST: + read the drum to get instr to PR register, + decode PR as opcode, DA, IA, + apply index tags if needed, write back to PR + check if opcode must wait for interlock release + check if opcode reads data from drum + 2 D-Cycle WAIT FOR DATA READ: + wait for interlock release if needed + wait for drum to be positioned at AR address if decoded opcode reads data from drum + 3 D-Cycle EXEC: + get data from storage into DIST if needed + set interlock if needed + execute opcode operation + 4 D-Cycle WAIT FOR DATA WRITE: + wait opcode excution time + wait for drum to be positioned at AR address if executed opcode writes data to drum + 5 D-Cycle WRITEBACK: + if executed opcode writes data to drum, write DIST to drum + set AR=IA to read next instruction */ @@ -870,9 +1451,20 @@ sim_instr(void) MachineCycle = CpuStepsUsed = 0; DrumAddr = 0; + CpuStepsUsed = 0; - WaitForInterlock = 0; - InterLockCount[IL_RD1] = InterLockCount[IL_WR1] = 0; + if ((ProgStopFlag) && + // if last inst was a programmed stop, + // and AR has not been changed (still contains the same value set by stop 01 opcode) + // gets instr to execute from IA instead of AR. This is to simulate the D-Cycle on stop opcode resume + ((PR / D8) == 01) && + (AR == ((PR / D4) % D4))) { + AR = (PR % D4); + ProgStopFlag = 0; + } + + WaitForInterlock = 0; // clear interlocks + for (il=0;il 0) {CpuStepsUsed--; continue;} // yes - // should wait for interlock release? - if (WaitForInterlock) { - if (InterLockCount[WaitForInterlock]) continue; // yes - WaitForInterlock = 0; - } - // should wait for drum to fetch data? - if ((bReadData) && (AR < MEMSIZE)) { - if ((AR % 50) != DrumAddr) continue; // yes - } - MachineCycle = 3; // exec instr - } if (MachineCycle == 4) { - // should wait for cpu to exec the inst? - if (CpuStepsUsed > 0) {CpuStepsUsed--; continue;} // yes - // should wait for drum to store data? - if ((bWriteDrum) && (AR < MEMSIZE)) { - if ((AR % 50) != DrumAddr) continue; // yes - } - MachineCycle = 5; // terminate the instr execution } - // here, MachineCycle is either 1 (decode), 3 (exec-read), 5 (exec-write) - + + /* Main instruction fetch/decode loop */ + sim_interval -= 1; /* count down */ + + // simulate the rotating drum: incr current drum position + DrumAddr = (DrumAddr+1) % 50; + // if any interlock set, decrease it + for (il=0;il 0) InterLockCount[il]--; + // decrease pending to execute step intruction count + if (CpuStepsUsed > 0) CpuStepsUsed--; + + // WAIT FOR INSTR + if (MachineCycle == 0) { + if (HalfCycle == 2 ) { // if D-Half should start + HalfCycle = 1; // bump half cycle to exec I-Half on next scp step + instr_count = 1; // break at the end of D-half execution + MachineCycle = 3; + continue; + } + // should wait for storage to fetch inst? + if (FAST == 0) if (WaitForStorage(AR)) continue; // yes + // init inst execution + CpuStepsUsed = 0; + + MachineCycle = 1; + } + // FETCH INST if (MachineCycle == 1) { - // fetch current intruction from mem, save current instr addr in IC + // get current intruction from storage, save current instr addr in IC IC = AR; if (0==ReadAddr(AR, &PR, NULL)) { reason = STOP_ADDR; goto end_of_cycle; } // decode inst - opname = DecodeOpcode(&opcode, &DA, &IA, &bReadData); + opname = DecodeOpcode(PR, &opcode, &DA, &IA); sim_debug(DEBUG_CMD, &cpu_dev, "Exec %04d: %02d %-6s %04d %04d %s%s\n", IC, opcode, (opname == NULL) ? "???":opname, DA, IA, (DRUM_Symbolic_Buffer[AR * 80] == 0) ? "" : " symb: ", &DRUM_Symbolic_Buffer[AR * 80]); + PROP = (uint16) opcode; if (opname == NULL) { reason = STOP_UUO; goto end_of_cycle; } + // if DA or IA tagged, modify DA or IA to remove tag and set the developed address in PR + if (STOR) { + int nIndexsApplied; + nIndexsApplied = ApplyIndexRegister(&DA) + ApplyIndexRegister(&IA); + if (nIndexsApplied > 0) { + CpuStepsUsed += nIndexsApplied; + PR = (t_int64) opcode * D8 + (t_int64) DA * D4 + (t_int64) IA; + sim_debug(DEBUG_CMD, &cpu_dev, "Exec %04d: %02d %-6s %04d %04d %s\n", + IC, opcode, (opname == NULL) ? "???":opname, DA, IA, + " (developed addr)"); + } + } AR = DA; // allways trasnfer DA to AR even if drum will be not read. This is why // all opcodes must have a valid DA address even if not used to read drum (eg SRT 0003 to shift) + + // simulates the machine working on half cycles + if (HalfCycle == 1) { // if I-Half finished, about to exec D-Half + HalfCycle = 2; // bump half cycle to exec D-Half on next scp step + reason = SCPE_STEP; // then break beacuse I-Half finished + break; + } + + bReadData = (base_ops[opcode].opRW & opReadDA) ? 1:0; + // check if opcode should wait for and already set interlock - if ((opcode == OP_RD) && (InterLockCount[IL_RD1])) { - WaitForInterlock = IL_RD1; - } else if ((opcode == OP_PCH) && (InterLockCount[IL_WR1])) { - WaitForInterlock = IL_WR1; - } else { + WaitForInterlock = base_ops[opcode].opInterLock; + + MachineCycle = 2; + } + // WAIT FOR DATA READ + if (MachineCycle == 2) { + // should wait to exec the inst (the address untagging) ? + if (FAST == 0) if (CpuStepsUsed > 0) continue; // yes + // should wait for interlock release for opcode execution? + if (WaitForInterlock) { + if (FAST == 0) if (InterLockCount[WaitForInterlock] > 0) continue; // interlock makes execution wait + InterLockCount[WaitForInterlock] = 0; // clear interlock WaitForInterlock = 0; } + // should wait for storage to fetch data? + if (bReadData) { + if (FAST == 0) if (WaitForStorage(AR)) continue; // yes + } - MachineCycle = 2; - continue; + MachineCycle = 3; } - - + // EXEC if (MachineCycle == 3) { // decode again PR register to reload internal register DA, IA, AR again. Needed if we are executing half cycles - opname = DecodeOpcode(&opcode, &DA, &IA, &bReadData); + opname = DecodeOpcode(PR, &opcode, &DA, &IA); AR = DA; if (opname == NULL) { reason = STOP_UUO; goto end_of_cycle; } - // fetch data from drum if needed + // even if no data is fetched, DA addr must be a valid one for this opcode + if (0==IsDrumAddrOk(AR, base_ops[opcode].validDA)) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "... %04d: Invalid addr ERROR\n", AR); + reason = STOP_ADDR; + goto end_of_cycle; + } + // get data from if needed + bReadData = (base_ops[opcode].opRW & opReadDA) ? 1:0; if (bReadData) { - if (0==ReadAddr(AR, &DIST, &DistNegativeZeroFlag)) { - sim_debug(DEBUG_DATA, &cpu_dev, "... Read %04d: ???\n", - AR); - reason = STOP_ADDR; - goto end_of_cycle; - } else { - sim_debug(DEBUG_DATA, &cpu_dev, "... Read %04d: %06d%04d%c\n", + ReadAddr(AR, &DIST, &DistNegativeZeroFlag); + sim_debug(DEBUG_DATA, &cpu_dev, "... Read %04d: %06d%04d%c\n", AR, printfd); - } - } else { - if (0==IsDrumAddrOk(AR)) { // even if no data is fetched from drum, DA addr must be a valid one - sim_debug(DEBUG_DETAIL, &cpu_dev, "Invalid AR addr %d ERROR\n", AR); - reason = STOP_ADDR; - goto end_of_cycle; - } - } - - // check if opcode should set interlock - if (opcode == OP_RD) { - InterLockCount[IL_RD1] = 3120; // 300 msec for read card processing - } else if ((opcode == OP_PCH) && (InterLockCount[IL_WR1])) { - InterLockCount[IL_WR1] = 6250; // 600 msec for punch card processing } + bWriteDrum = (base_ops[opcode].opRW & opWriteDA) ? 1:0; reason = ExecOpcode(opcode, DA, - &bWriteDrum, &bBranchToDA, + &bBranchToDA, DrumAddr, &CpuStepsUsed); if (reason != 0) goto end_of_cycle; if (bBranchToDA) IA = DA; MachineCycle = 4; - if (CpuStepsUsed > 2) CpuStepsUsed -= 2; // decrease by 2 as each inst passes at minimum two times by DrumAddr incr - continue; } + // WAIT FOR DATA WRITE + if (MachineCycle == 4) { + // should wait to exec the inst (opcode execution) ? + if (FAST == 0) if (CpuStepsUsed > 0) continue; // yes + // should wait for storage to store data? + if (bWriteDrum) { + if (FAST == 0) if (WaitForStorage(AR)) continue; // yes + } + MachineCycle = 5; + } + // WRITEBACK if (MachineCycle == 5) { if (bWriteDrum) { sim_debug(DEBUG_DATA, &cpu_dev, "... Write %04d: %06d%04d%c\n", AR, printfd); - if (0==WriteDrum(AR, DIST, DistNegativeZeroFlag)) { + if (0==WriteAddr(AR, DIST, DistNegativeZeroFlag)) { reason = STOP_ADDR; goto end_of_cycle; } } // set AR to point to next instr AR = IA; - // do not continue, just go on end_of_cycle + // no more machine cycles } + end_of_cycle: if (instr_count != 0 && --instr_count == 0) { @@ -1068,7 +1671,6 @@ end_of_cycle: } /* Simulation halted */ - return reason; } @@ -1080,9 +1682,12 @@ cpu_reset(DEVICE * dptr) ACC[0] = ACC[1] = DIST = 0; PR = AR = OV = 0; + ProgStopFlag = 0; AccNegativeZeroFlag = 0; DistNegativeZeroFlag = 0; IC = 0; + IAS_TimingRing = 0; + IR[0] = IR[1] = IR[2] = 0; sim_brk_types = sim_brk_dflt = SWMASK('E'); return SCPE_OK; @@ -1118,15 +1723,18 @@ t_stat cpu_dep(t_value val, t_addr addr, UNIT * uptr, int32 sw) { t_int64 d; - if (addr >= MEMSIZE) - return SCPE_NXM; - d = val; + int NegZero; + if (val == NEGZERO_value) { - DRUM[addr] = 0; // Minus Zero is coded as val = NEGZERO_value constant - DRUM_NegativeZeroFlag[addr] = 1; + d = 0; + NegZero = 1; } else { - DRUM[addr] = d; - DRUM_NegativeZeroFlag[addr] = 0; + d = val; + NegZero = 0; + } + + if (0==WriteAddr(addr, d, NegZero)) { + return SCPE_NXM; } return SCPE_OK; } @@ -1142,25 +1750,26 @@ cpu_set_size(UNIT * uptr, int32 val, CONST char *cptr, void *desc) if (v == 0) {v = 1000;} else if (v == 1) {v = 2000;} else if (v == 2) {v = 4000;} else v = 0; - if ((v <= 0) || (v > MAXMEMSIZE)) + if ((v <= 0) || (v > MAXDRUMSIZE)) return SCPE_ARG; if (v < 4000) { - for (i = v; i < MEMSIZE; i++) { + for (i = v; i < MAXDRUMSIZE; i++) { if ((DRUM[i] != 0) || (DRUM_NegativeZeroFlag[i] != 0)) { mc = 1; - break; + break; } } } - for (i=0;i SET CPU nK\r\n\r\n"); + fprintf (st, " sim> SET CPU StorageUnit enables IBM 652 Storage Unit\n"); + fprintf (st, " sim> SET CPU NoStorageUnit disables IBM 652 Storage Unit\n\n"); fprint_set_help(st, dptr); fprint_show_help(st, dptr); return SCPE_OK; diff --git a/I650/i650_defs.h b/I650/i650_defs.h index e13733f0..f39e09f6 100644 --- a/I650/i650_defs.h +++ b/I650/i650_defs.h @@ -36,17 +36,28 @@ /* Memory */ -#define MAXMEMSIZE (4000) -#define MEMSIZE cpu_unit.capac /* actual memory size */ -#define MEMMASK (MEMSIZE - 1) /* Memory bits */ +#define MAXDRUMSIZE (4000) +#define DRUMSIZE ((int)(cpu_unit.capac % 10) * 1000) /* actual drum memory size */ -#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) -extern t_int64 DRUM[MAXMEMSIZE]; -extern int DRUM_NegativeZeroFlag[MAXMEMSIZE]; -extern char DRUM_Symbolic_Buffer[MAXMEMSIZE * 80]; +extern t_int64 DRUM[MAXDRUMSIZE]; +extern int DRUM_NegativeZeroFlag[MAXDRUMSIZE]; +extern char DRUM_Symbolic_Buffer[MAXDRUMSIZE * 80]; + +extern t_int64 IOSync[10]; +extern int IOSync_NegativeZeroFlag[10]; + +#define STOR (cpu_unit.flags & OPTION_STOR) +#define CNTRL (cpu_unit.flags & OPTION_CNTRL) +#define FAST (cpu_unit.flags & OPTION_FAST) + +extern t_int64 IAS[60]; +extern int IAS_NegativeZeroFlag[60]; +extern int IAS_TimingRing; + +extern int WriteAddr(int AR, t_int64 d, int NegZero); +extern int ReadAddr(int AR, t_int64 * d, int * NegZero); +extern CONST char * DecodeOpcode(t_int64 d, int * opcode, int * DA, int * IA); -extern int WriteDrum(int AR, t_int64 d, int NegZero); -extern int ReadDrum(int AR, t_int64 * d, int * NegZero); /* digits contants */ #define D10 (10000000000LL) // ten digits (10 zeroes) @@ -86,10 +97,16 @@ extern DEBTAB crd_debug[]; extern DEVICE cp_dev; #endif +// max number of cards in deck for carddeck internal command +#define MAX_CARDS_IN_DECK 10000 +#define MAX_CARDS_IN_READ_TAKE_HOPPER 10 + extern DIB cdr_dib; extern DEVICE cdr_dev; extern uint32 cdr_cmd(UNIT *, uint16, uint16); extern UNIT cdr_unit[4]; +extern char ReadHopper[3 * MAX_CARDS_IN_READ_TAKE_HOPPER * 80]; +extern int ReadHopperLast[3]; extern DIB cdp_dib; extern DEVICE cdp_dev; @@ -103,58 +120,6 @@ extern UNIT cdp_unit[4]; #define URCSTA_SOAPSYMB 02000 /* Get soap symbolic info when reading the card */ -/* Character codes in IBM 650 as stated in p4 Andree Programming the IBM 650 Mag Drum - Also stated in www.bitsavers.org/pdf/ibm/650/28-4028_FOR_TRANSIT.pdf p37 -*/ -#define CHR_BLANK 00 -#define CHR_DOT 18 // card code: 12-3-8 . -#define CHR_RPARENT 19 // 12-4-8 ) -#define CHR_AMPERSAND 20 // 12 + -#define CHR_DOLLAR 28 // 11-3-8 $ -#define CHR_STAR 29 // 11-4-8 * -#define CHR_NEG 30 // 11 - minus sign for negative value -#define CHR_SLASH 31 // 0-1 / -#define CHR_COMMA 38 // 0-3-8 , -#define CHR_LPARENT 39 // 0-4-8 ( -#define CHR_EQUAL 48 // 3-8 = -#define CHR_MINUS 49 // 4-8 - -#define CHR_A 61 -#define CHR_B 62 -#define CHR_C 63 -#define CHR_D 64 -#define CHR_E 65 -#define CHR_F 66 -#define CHR_G 67 -#define CHR_H 68 -#define CHR_I 69 -#define CHR_J 71 -#define CHR_K 72 -#define CHR_L 73 -#define CHR_M 74 -#define CHR_N 75 -#define CHR_O 76 -#define CHR_P 77 -#define CHR_Q 78 -#define CHR_R 79 -#define CHR_S 82 -#define CHR_T 83 -#define CHR_U 84 -#define CHR_V 85 -#define CHR_W 86 -#define CHR_X 87 -#define CHR_Y 88 -#define CHR_Z 89 -#define CHR_0 90 -#define CHR_1 91 -#define CHR_2 92 -#define CHR_3 93 -#define CHR_4 94 -#define CHR_5 95 -#define CHR_6 96 -#define CHR_7 97 -#define CHR_8 98 -#define CHR_9 99 - extern struct card_wirings { uint32 mode; const char *name; @@ -178,6 +143,7 @@ extern int cycle_time; extern const char *cpu_description(DEVICE *dptr); /* Opcodes */ +// Instructions on Basic machine #define OP_AABL 17 // Add absolute to lower accumulator #define OP_AL 15 // Add to lower accumulator #define OP_AU 10 // Add to upper accumulator @@ -195,33 +161,136 @@ extern const char *cpu_description(DEVICE *dptr); #define OP_BRD8 98 #define OP_BRD9 99 #define OP_BRD10 90 -#define OP_DIV 14 // Divide -#define OP_DIVRU 64 // Divide and reset upper accumulator -#define OP_LD 69 // Load distributor -#define OP_MULT 19 // Multiply -#define OP_NOOP 00 // No operation -#define OP_PCH 71 // Punch a card -#define OP_RD 70 // Read a card -#define OP_RAABL 67 // Reset accumulator and add absolute to lower accumulator -#define OP_RAL 65 // Reset accumulator and add to lower accumulator -#define OP_RAU 60 // Reset accumulator and add to upper accumulator -#define OP_RSABL 68 // Reset accumulator and subtract absolute from lower accumulator -#define OP_RSL 66 // Reset accumulator and subtract from lower accumulator -#define OP_RSU 61 // Reset accumulator and subtract from upper accumulator -#define OP_SLT 35 // Shift accumulator left -#define OP_SCT 36 // Shift accumulator left and count -#define OP_SRT 30 // Shift accumulator right -#define OP_SRD 31 // Shift accumulator right and round accumulator -#define OP_STOP 01 // Stop if console switch is set to stop, otherwise continue as a NO-OP -#define OP_STD 24 // Store distributor into memory -#define OP_STDA 22 // Store lower accumulator data address into distributor, then store distributor into memory -#define OP_STIA 23 // Store lower accumulator instruction address into distributor, then store distributor into memory -#define OP_STL 20 // Store lower accumulator into memory -#define OP_STU 21 // Store upper accumulator into memory -#define OP_SABL 18 // Subtract absolute from lower accumulator -#define OP_SL 16 // Subtract from lower accumulator -#define OP_SU 11 // Subtract from upper accumulator -#define OP_TLU 84 // Table lookup +#define OP_DIV 14 // Divide +#define OP_DIVRU 64 // Divide and reset upper accumulator +#define OP_LD 69 // Load distributor +#define OP_MULT 19 // Multiply +#define OP_NOOP 00 // No operation +#define OP_PCH 71 // Punch a card +#define OP_RD 70 // Read a card +#define OP_RAABL 67 // Reset accumulator and add absolute to lower accumulator +#define OP_RAL 65 // Reset accumulator and add to lower accumulator +#define OP_RAU 60 // Reset accumulator and add to upper accumulator +#define OP_RSABL 68 // Reset accumulator and subtract absolute from lower accumulator +#define OP_RSL 66 // Reset accumulator and subtract from lower accumulator +#define OP_RSU 61 // Reset accumulator and subtract from upper accumulator +#define OP_SLT 35 // Shift accumulator left +#define OP_SCT 36 // Shift accumulator left and count +#define OP_SRT 30 // Shift accumulator right +#define OP_SRD 31 // Shift accumulator right and round accumulator +#define OP_STOP 01 // Stop if console switch is set to stop, otherwise continue as a NO-OP +#define OP_STD 24 // Store distributor into memory +#define OP_STDA 22 // Store lower accumulator data address into distributor, then store distributor into memory +#define OP_STIA 23 // Store lower accumulator instruction address into distributor, then store distributor into memory +#define OP_STL 20 // Store lower accumulator into memory +#define OP_STU 21 // Store upper accumulator into memory +#define OP_SABL 18 // Subtract absolute from lower accumulator +#define OP_SL 16 // Subtract from lower accumulator +#define OP_SU 11 // Subtract from upper accumulator +#define OP_TLU 84 // Table lookup +// Instructions on Storage Unit +// opcodes for indexing +#define OP_AXA 50 // Add to index register A +#define OP_SXA 51 // Substract from index A +#define OP_RAA 80 // Reset Add Index A +#define OP_RSA 81 // Reset Substract Index A +#define OP_NZA 40 // Branch Non Zero Index A +#define OP_BMA 41 // Branch Minus Index A +#define OP_AXB 52 // Add to index register B +#define OP_SXB 53 // Substract from index B +#define OP_RAB 82 // Reset Add Index B +#define OP_RSB 83 // Reset Substract Index B +#define OP_NZB 42 // Branch Non Zero Index B +#define OP_BMB 43 // Branch Minus Index B +#define OP_AXC 58 // Add to index register C +#define OP_SXC 59 // Substract from index C +#define OP_RAC 88 // Reset Add Index C +#define OP_RSC 89 // Reset Substract Index C +#define OP_NZC 48 // Branch Non Zero Index C +#define OP_BMC 49 // Branch Minus Index C +// io for synchronizers 2 & 3 +#define OP_RC1 72 // Read Conditional sync 1 +#define OP_RD2 73 // Read Sync 2 +#define OP_WR2 74 // Write Sync 2 +#define OP_RC2 75 // Read Conditional Sync 2 +#define OP_RD3 76 // Read Sync 3 +#define OP_WR3 77 // Write Sync 3 +#define OP_RC3 78 // Read Conditional Sync 3 +// immediate access storage (ias) +#define OP_LIB 8 // Load IAS block +#define OP_LDI 9 // Load IAS +#define OP_SIB 28 // Store IAS Block +#define OP_STI 29 // Store IAS +#define OP_SET 27 // Set IAS Timing Ring +// floating point +#define OP_FAD 32 // Floating Add +#define OP_FSB 33 // Floating Subtract +#define OP_FMP 39 // Floating Multiply +#define OP_FDV 34 // Floating Divide +#define OP_UFA 02 // Unnormalized Floating Add +#define OP_FAM 37 // Floating Add Absolute (Magnitude) +#define OP_FSM 38 // Floating Subtract Absolute (Magnitude) +// Instructions on Control Unit +// tape +#define OP_RTN 04 // Read Tape Numeric +#define OP_RTA 05 // Read Tape Alphameric +#define OP_WTN 06 // Write Tape Numeric +#define OP_WTA 07 // Write Tape Alphameric +#define OP_RTC 03 // Read Tape for Checking +#define OP_NTS 25 // Branch no Tape Signal +#define OP_NEF 54 // Branch no End of File +#define OP_RWD 55 // Rewind Tape +#define OP_WTM 56 // Write Tape Mark +#define OP_BST 57 // Backspace Tape +// ramac disk +#define OP_SDS 85 // Seek Disk Storage +#define OP_RDS 86 // Read Disk Storage +#define OP_WDS 87 // Write Disk Storage +// inquiry stations +#define OP_BIN 26 // Branch on Inquiry +#define OP_RPY 79 // Reply on Inquiry + +// Valid Data Address (DA) +#define vda_D 1 // 0000-1999 Drum +#define vda_A 2 // 8000-8003 Arithmetic unit registers (ACC Low & Hi), Distributor, Console Switches register +#define vda_I 4 // 8005-8007 Index Registers (IR) +#define vda_T 8 // 8010-8015 Tape address +#define vda_S 16 // 9000-9059 Immediate Access Storage (IAS) +#define vda_9000 32 // 9000 Only addr 9000 valid + +#define vda_DAITS (vda_D | vda_A | vda_I | vda_T | vda_S ) +#define vda_DAIS (vda_D | vda_A | vda_I | vda_S ) +#define vda_DAS (vda_D | vda_A | vda_S ) +#define vda_DS (vda_D | vda_S ) + +#define opReadDA 1 // opcode fetchs data from DA address +#define opWriteDA 2 // opcode write data to DA + +#define opStorUnit 1 // opcode available if IBM 653 Storage Unit is present +#define opCntrlUnit 2 // opcode available if IBM 652 Control Unit is present + +#define IL_RD1 1 // interlock on drum area 01-10/51-60 used in reading with RD1 +#define IL_WR1 2 // interlock on drum area 27-36/77-86 used in writing for WR1 +#define IL_RD23 3 // interlock on drum area 39-48/89-98 used in reading with RD2/RD3 +#define IL_WR23 4 // interlock on drum area 13-22/63-72 used in writing for WR2/WR3 +#define IL_IAS 5 // interlock on ias access +#define IL_array 6 // interlock array definition value + +/* Symbol tables */ +typedef struct +{ + uint16 opbase; // opcode number + const char *name1; // opcode name as in operation manual + const char *name2; // opcode name as in soap + uint8 opRW; // =wDA, rDA or zero + int option; // =0 -> opcode in basic machine, =1 -> Opcode because Storage Unit, =2 -> Opcode because Control Unit + int validDA; // valid data address for this instruction + int opInterLock; // Interlock required by opcode +} +t_opcode; + +extern t_opcode base_ops[100]; + #define NEGZERO_value 0x7fffFFFFffffFFFF #define AccNegative (((AccNegativeZeroFlag) || (ACC[1]<0) || (ACC[0]<0)) ? 1:0) @@ -237,6 +306,7 @@ extern const char *cpu_description(DEVICE *dptr); #define WIRING_SOAP ( 0x100 << UNIT_V_CARD_MODE) #define WIRING_IS ( 0x200 << UNIT_V_CARD_MODE) #define WIRING_IT ( 0x300 << UNIT_V_CARD_MODE) +#define WIRING_FORTRANSIT ( 0x400 << UNIT_V_CARD_MODE) #define UNIT_CARD_ECHO ( 0x1000 << UNIT_V_CARD_MODE) #define UNIT_CARD_PRINT ( 0x2000 << UNIT_V_CARD_MODE) @@ -246,3 +316,4 @@ extern int Shift_Digits(t_int64 * d, int nDigits); extern char * word_to_ascii(char * buf, int CharStart, int CharLen, t_int64 d); + diff --git a/I650/i650_sys.c b/I650/i650_sys.c index adc67545..4b9649ef 100644 --- a/I650/i650_sys.c +++ b/I650/i650_sys.c @@ -98,10 +98,11 @@ DEBTAB crd_debug[] = { // simulator available IBM 533 wirings struct card_wirings wirings[] = { - {WIRING_8WORD, "8WORD"}, - {WIRING_SOAP, "SOAP"}, - {WIRING_IS, "IS"}, - {WIRING_IT, "IT"}, + {WIRING_8WORD, "8WORD"}, + {WIRING_SOAP, "SOAP"}, + {WIRING_IS, "IS"}, + {WIRING_IT, "IT"}, + {WIRING_FORTRANSIT, "FORTRANSIT"}, {0, 0}, }; @@ -177,7 +178,9 @@ void vm_init(void) { int i; // Initialize vm memory to all plus zero - for(i = 0; i < MAXMEMSIZE; i++) DRUM[i] = DRUM_NegativeZeroFlag[i] = 0; + for(i = 0; i < MAXDRUMSIZE; i++) DRUM[i] = DRUM_NegativeZeroFlag[i] = 0; + for(i = 0; i < 60; i++) IAS[i] = IAS_NegativeZeroFlag[i] = 0; + // init specific commands sim_vm_cmd = aux_cmds; /* set up the auxiliary command table */ } @@ -193,68 +196,125 @@ sim_load(FILE * fileref, CONST char *cptr, CONST char *fnam, int flag) /* Currently not implimented until I know format of load files */ return SCPE_NOFNC; } - -/* Symbol tables */ -typedef struct _opcode -{ - uint16 opbase; - const char *name; - uint8 bReadData; // =1 if inst fetchs data from memory -} -t_opcode; + /* Opcodes */ -t_opcode base_ops[] = { - {OP_AABL, "AABL", 1}, - {OP_AL, "AL", 1}, - {OP_AU, "AU", 1}, - {OP_BRNZ, "BRNZ", 0}, - {OP_BRMIN, "BRMIN", 0}, - {OP_BRNZU, "BRNZU", 0}, - {OP_BROV, "BROV", 0}, - {OP_BRD1, "BRD1", 0}, - {OP_BRD2, "BRD2", 0}, - {OP_BRD3, "BRD3", 0}, - {OP_BRD4, "BRD4", 0}, - {OP_BRD5, "BRD5", 0}, - {OP_BRD6, "BRD6", 0}, - {OP_BRD7, "BRD7", 0}, - {OP_BRD8, "BRD8", 0}, - {OP_BRD9, "BRD9", 0}, - {OP_BRD10, "BRD10", 0}, - {OP_DIV, "DIV", 1}, - {OP_DIVRU, "DIVRU", 1}, - {OP_LD, "LD", 1}, - {OP_MULT, "MULT", 1}, - {OP_NOOP, "NOOP", 0}, - {OP_PCH, "PCH", 0}, - {OP_RD, "RD", 0}, - {OP_RAABL, "RAABL", 1}, - {OP_RAL, "RAL", 1}, - {OP_RAU, "RAU", 1}, - {OP_RSABL, "RSABL", 1}, - {OP_RSL, "RSL", 1}, - {OP_RSU, "RSU", 1}, - {OP_SLT, "SLT", 0}, - {OP_SCT, "SCT", 0}, - {OP_SRT, "SRT", 0}, - {OP_SRD, "SRD", 0}, - {OP_STOP, "STOP", 0}, - {OP_STD, "STD", 0}, - {OP_STDA, "STDA", 0}, - {OP_STIA, "STIA", 0}, - {OP_STL, "STL", 0}, - {OP_STU, "STU", 0}, - {OP_SABL, "SABL", 1}, - {OP_SL, "SL", 1}, - {OP_SU, "SU", 1}, - {OP_TLU, "TLU", 0}, - {0, NULL, 0} +t_opcode base_ops[100] = { + // opcode name soap name R/W? option Valid Data Address + {OP_NOOP, "NOOP", "NOP", 0, 0, vda_DAITS}, + {OP_STOP, "STOP", "HLT", 0, 0, vda_DAITS}, + {OP_UFA, "FASN", "UFA", opReadDA, opStorUnit, vda_DAIS}, + {OP_RTC, "RCT", "RTC", 0, opCntrlUnit, vda_T}, + {OP_RTN, "RT", "RTN", 0, opCntrlUnit, vda_T}, + {OP_RTA, "RTA", "RTA", 0, opCntrlUnit, vda_T}, + {OP_WTN, "WT", "WTN", 0, opCntrlUnit, vda_T}, + {OP_WTA, "WTA", "WTA", 0, opCntrlUnit, vda_T}, + {OP_LIB, "LBB", "LIB", opReadDA, opStorUnit, vda_D, IL_IAS}, + {OP_LDI, "LB", "LDI", opReadDA, opStorUnit, vda_D, IL_IAS}, + + {OP_AU, "AU", "AUP", opReadDA, 0, vda_DAIS}, + {OP_SU, "SU", "SUP", opReadDA, 0, vda_DAIS}, + {12, NULL, NULL, 0, 0, 0}, + {13, NULL, NULL, 0, 0, 0}, + {OP_DIV, "DIV", "DIV", opReadDA, 0, vda_DAIS}, + {OP_AL, "AL", "ALO", opReadDA, 0, vda_DAIS}, + {OP_SL, "SL", "SLO", opReadDA, 0, vda_DAIS}, + {OP_AABL, "AABL", "AML", opReadDA, 0, vda_DAIS}, + {OP_SABL, "SABL", "SML", opReadDA, 0, vda_DAIS}, + {OP_MULT, "MULT", "MPY", opReadDA, 0, vda_DAIS}, + + {OP_STL, "STL", "STL", opWriteDA, 0, vda_DS}, + {OP_STU, "STU", "STU", opWriteDA, 0, vda_DS}, + {OP_STDA, "STDA", "SDA", opWriteDA, 0, vda_DS}, + {OP_STIA, "STIA", "SIA", opWriteDA, 0, vda_DS}, + {OP_STD, "STD", "STD", opWriteDA, 0, vda_DS}, + {OP_NTS, "BNTS", "NTS", 0, opCntrlUnit, vda_DAIS}, + {OP_BIN, "BIN", "BIN", 0, opCntrlUnit, vda_D}, + {OP_SET, "SET", "SET", 0, opStorUnit, vda_S, IL_IAS}, + {OP_SIB, "STBB", "SIB", 0, opStorUnit, vda_D, IL_IAS}, + {OP_STI, "STB", "STI", 0, opStorUnit, vda_D, IL_IAS}, + + {OP_SRT, "SRT", "SRT", 0, 0, vda_DAITS}, + {OP_SRD, "SRD", "SRD", 0, 0, vda_DAITS}, + {OP_FAD, "FA", "FAD", opReadDA, opStorUnit, vda_DAIS}, + {OP_FSB, "FS", "FSB", opReadDA, opStorUnit, vda_DAIS}, + {OP_FDV, "FD", "FDV", opReadDA, opStorUnit, vda_DAIS}, + {OP_SLT, "SLT", "SLT", 0, 0, vda_DAITS}, + {OP_SCT, "SCT", "SCT", 0, 0, vda_DAITS}, + {OP_FAM, "FAAB", "FAM", opReadDA, opStorUnit, vda_DAIS}, + {OP_FSM, "FSAB", "FSM", opReadDA, opStorUnit, vda_DAIS}, + {OP_FMP, "FM", "FMP", opReadDA, opStorUnit, vda_DAIS}, + + {OP_NZA, "BNZA", "NZA", 0, opStorUnit, vda_DAIS}, + {OP_BMA, "BMNA", "BMA", 0, opStorUnit, vda_DAIS}, + {OP_NZB, "BNZB", "NZB", 0, opStorUnit, vda_DAIS}, + {OP_BMB, "BMNB", "BMB", 0, opStorUnit, vda_DAIS}, + {OP_BRNZU, "BRNZU", "NZU", 0, 0, vda_DAIS}, + {OP_BRNZ, "BRNZ", "NZE", 0, 0, vda_DAIS}, + {OP_BRMIN, "BRMIN", "BMI", 0, 0, vda_DAIS}, + {OP_BROV, "BROV", "BOV", 0, 0, vda_DAIS}, + {OP_NZC, "BNZC", "NZC", 0, opStorUnit, vda_DAIS}, + {OP_BMC, "BMNC", "BMC", 0, opStorUnit, vda_DAIS}, + + {OP_AXA, "AA", "AXA", 0, opStorUnit, vda_DAS}, + {OP_SXA, "SA", "SXA", 0, opStorUnit, vda_DAS}, + {OP_AXB, "AB", "AXB", 0, opStorUnit, vda_DAS}, + {OP_SXB, "SB", "SXB", 0, opStorUnit, vda_DAS}, + {OP_NEF, "BRNEF", "NEF", 0, opCntrlUnit, vda_DAIS}, + {OP_RWD, "RWD", "RWD", 0, opCntrlUnit, vda_T}, + {OP_WTM, "WTM", "WTM", 0, opCntrlUnit, vda_T}, + {OP_BST, "BSP", "BST", 0, opCntrlUnit, vda_T}, + {OP_AXC, "AC", "AXC", 0, opStorUnit, vda_DAS}, + {OP_SXC, "SC", "SXC", 0, opStorUnit, vda_DAS}, + + {OP_RAU, "RAU", "RAU", opReadDA, 0, vda_DAIS}, + {OP_RSU, "RSU", "RSU", opReadDA, 0, vda_DAIS}, + {62, NULL, NULL, 0, 0, 0}, + {63, NULL, NULL, 0, 0, 0}, + {OP_DIVRU, "DIVRU", "DVR", opReadDA, 0, vda_DAIS}, + {OP_RAL, "RAL", "RAL", opReadDA, 0, vda_DAIS}, + {OP_RSL, "RSL", "RSL", opReadDA, 0, vda_DAIS}, + {OP_RAABL, "RAABL", "RAM", opReadDA, 0, vda_DAIS}, + {OP_RSABL, "RSABL", "RSM", opReadDA, 0, vda_DAIS}, + {OP_LD, "LD", "LDD", opReadDA, 0, vda_DAIS}, + + {OP_RD, "RD", "RD1", 0, 0, vda_DS, IL_RD1}, + {OP_PCH, "PCH", "WR1", 0, 0, vda_DS, IL_WR1}, + {OP_RC1, "RC1", "RC1", 0, opStorUnit, vda_DS, IL_RD1}, + {OP_RD2, "RD2", "RD2", 0, opStorUnit, vda_DS, IL_RD23}, + {OP_WR2, "WR2", "WR2", 0, opStorUnit, vda_DS, IL_WR23}, + {OP_RC2, "RC2", "RC2", 0, opStorUnit, vda_DS, IL_RD23}, + {OP_RD3, "RD3", "RD3", 0, opStorUnit, vda_DS, IL_RD23}, + {OP_WR3, "WR3", "WR3", 0, opStorUnit, vda_DS, IL_WR23}, + {OP_RC3, "RC3", "RC3", 0, opStorUnit, vda_DS, IL_RD23}, + {OP_RPY, "RPY", "RPY", 0, opCntrlUnit, vda_D}, + + {OP_RAA, "RAA", "RAA", 0, opStorUnit, vda_DAS}, + {OP_RSA, "RSA", "RSA", 0, opStorUnit, vda_DAS}, + {OP_RAB, "RAB", "RAB", 0, opStorUnit, vda_DAS}, + {OP_RSB, "RSB", "RSB", 0, opStorUnit, vda_DAS}, + {OP_TLU, "TLU", "TLU", 0, 0, vda_DS}, + {OP_SDS, "SDS", "SDS", 0, opCntrlUnit, vda_9000}, + {OP_RDS, "RDS", "RDS", 0, opCntrlUnit, vda_9000}, + {OP_WDS, "WDS", "WDS", 0, opCntrlUnit, vda_9000}, + {OP_RAC, "RAC", "RAC", 0, opStorUnit, vda_DAS}, + {OP_RSC, "RSC", "RSC", 0, opStorUnit, vda_DAS}, + + {OP_BRD10, "BRD10", "BDO", 0, 0, vda_DAIS}, + {OP_BRD1, "BRD1", "BD1", 0, 0, vda_DAIS}, + {OP_BRD2, "BRD2", "BD2", 0, 0, vda_DAIS}, + {OP_BRD3, "BRD3", "BD3", 0, 0, vda_DAIS}, + {OP_BRD4, "BRD4", "BD4", 0, 0, vda_DAIS}, + {OP_BRD5, "BRD5", "BD5", 0, 0, vda_DAIS}, + {OP_BRD6, "BRD6", "BD6", 0, 0, vda_DAIS}, + {OP_BRD7, "BRD7", "BD7", 0, 0, vda_DAIS}, + {OP_BRD8, "BRD8", "BD8", 0, 0, vda_DAIS}, + {OP_BRD9, "BRD9", "BD9", 0, 0, vda_DAIS} }; /* Print out an instruction */ void -print_opcode(FILE * of, t_int64 val, t_opcode * tab) +print_opcode(FILE * of, t_int64 val) { int sgn; @@ -262,25 +322,21 @@ print_opcode(FILE * of, t_int64 val, t_opcode * tab) int DA; int op; int n; + CONST char * opname; if (val < 0) {sgn = -1; val = -val;} else sgn = 1; - op = Shift_Digits(&val, 2); // opcode - DA = Shift_Digits(&val, 4); // data address - IA = Shift_Digits(&val, 4); // intruction address - while (tab->name != NULL) { - if (tab->opbase == op) { - fputs(tab->name, of); - n = strlen(tab->name); - while (n++<6) fputc(' ', of); - fprintf(of, "%04d ", DA); - fputc(' ', of); - fprintf(of, "%04d ", IA); - return; - } - tab++; + opname = DecodeOpcode(val, &op, &DA, &IA); + if (opname == NULL) { + fprintf(of, " %d Unknown opcode", op); + return; } - fprintf(of, " %d Unknown opcode", op); + fputs(opname, of); + n = strlen(opname); + while (n++<6) fputc(' ', of); + fprintf(of, "%04d ", DA); + fputc(' ', of); + fprintf(of, "%04d ", IA); } /* Symbolic decode @@ -298,7 +354,7 @@ print_opcode(FILE * of, t_int64 val, t_opcode * tab) t_stat fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw) { - t_int64 inst; + t_int64 d, inst; int NegZero; int ch; @@ -318,9 +374,10 @@ fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw) if (sw & SWMASK('C') ) { int i; + d = inst; fputs(" '", of); for (i=0;i<5;i++) { - ch = Shift_Digits(&inst, 2); + ch = Shift_Digits(&d, 2); fputc(mem_to_ascii[ch], of); } fputc('\'', of); @@ -329,20 +386,25 @@ fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw) if (sw & SWMASK('M')) { fputs(" ", of); inst = AbsWord(inst); - print_opcode(of, inst, base_ops); + print_opcode(of, inst); } return SCPE_OK; } -t_opcode * -find_opcode(char *op, t_opcode * tab) +int +find_opcode(char *op) { - while (tab->name != NULL) { - if (*tab->name != '\0' && strcmp(op, tab->name) == 0) - return tab; - tab++; + int i; + if (op == NULL) return -1; + for (i=0;i<100;i++) { + if (base_ops[i].name1 == NULL) continue; + // accept both mnemonic sets: operation manual one (name1) and soap one (name2) + if ((base_ops[i].name1 != NULL) && (strcmp(op, base_ops[i].name1) == 0)) + return i; + if ((base_ops[i].name2 != NULL) && (strcmp(op, base_ops[i].name2) == 0)) + return i; } - return NULL; + return -1; } /* read n digits, optionally with sign NNNN[+|-] @@ -414,9 +476,8 @@ int ascii_to_NN(int ch) t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int32 sw) { t_int64 d; - int da, ia; + int op, da, ia; char ch, opcode[100]; - t_opcode *op; int i; int neg, IsNeg; @@ -429,8 +490,14 @@ t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int3 cptr = get_glyph(cptr, opcode, 0); - op = find_opcode(opcode, base_ops); - if (op == 0) return STOP_UUO; + op = find_opcode(opcode); + if (op < 0) return STOP_UUO; + + if (DecodeOpcode(op * (t_int64) D8, &op, &da, &ia) == NULL) { + // opcode exists, but not availble because associated hw (Storage Unit or Control Unit) + // is not enabled + return STOP_UUO; + } while (isspace(*cptr)) cptr++; /* Collect first argument: da */ @@ -443,13 +510,15 @@ t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int3 cptr = parse_n(&d, cptr, 4); ia = (int) d; // construct inst - d = op->opbase * (t_int64) D8 + da * (t_int64) D4 + (t_int64) ia; + d = op * (t_int64) D8 + da * (t_int64) D4 + (t_int64) ia; } else if (sw & SWMASK('C')) { d = 0; + if ((*cptr == 34) || (*cptr == 39)) cptr++; // skip double or single quotes if present for(i=0; i<5;i++) { d = d * 100; ch = *cptr; if (ch == '\0') continue; + if ((*cptr == 34) || (*cptr == 39)) continue; // double or single quotes mark end of text cptr++; d = d + ascii_to_NN(ch); } @@ -469,24 +538,6 @@ t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int3 return SCPE_OK; } -// get data for opcode -// return pointer to opcode name if opcode found, else NULL -const char * get_opcode_data(int opcode, int * bReadData) -{ - t_opcode * tab = base_ops; - - *bReadData = 0; - while (tab->name != NULL) { - if (tab->opbase == opcode) { - *bReadData = tab->bReadData; - return tab->name; - } - tab++; - } - return NULL; -} - - /* Helper functions */ // set in buf string ascii chars form word d ( chars: c1c2c3c4c5 ) @@ -568,10 +619,10 @@ int Shift_Digits(t_int64 * d, int nDigits) the source deck to be splitted number of cards in each splitted deck. - If count >= 0, indicates the cards on first destination deck file - remaining cards go to the second destination deck - If count < 0, indicates the cards on second destination deck file - (so deck 2 contains lasts count cards from source) + If count > 0, indicates the cards on first destination deck file + remaining cards go to the second destination deck + If count < 0, indicates the cards on second destination deck file + (so deck 2 contains lasts count cards from source) first destination deck file second destination deck file @@ -602,14 +653,20 @@ int Shift_Digits(t_int64 * d, int nDigits) carddeck print + carddeck echolast echo on console last n cards already read that are in the take hopper + + carddeck echolasty + + number of cards to display (upo to 10) + + should be cdr1 to cdr3. Unit for Take hopper + + switches: if present mut be just after carddeck and before deck operation -Q quiet return status. */ -// max number of cards in deck for cadrdeck internal command -#define MAX_CARDS_IN_DECK 10000 - // load card file fn and add its cards to // DeckImage array, up to a max of nMaxCards // increment nCards with the number of added cards @@ -702,6 +759,38 @@ t_stat deck_save(CONST char *fn, uint16 * DeckImage, int card, int nCards) return r; } +// echo/print nCards from DeckImage array +// uses cdp0 device/unit +void deck_print_echo(uint16 * DeckImage, int nCards, int bPrint, int bEcho) +{ + char line[81]; + int i,c,nc; + + for (nc=0; nc static t_stat deck_split_cmd(CONST char *cptr) { @@ -727,14 +816,16 @@ static t_stat deck_split_cmd(CONST char *cptr) cptr = get_glyph (cptr, gbuf, 0); // get cards count param nCards1 = (int32) get_uint (gbuf, 10, 10000, &r); if (r != SCPE_OK) return sim_messagef (SCPE_ARG, "Invalid count value\n"); + if (nCards1 == 0) return sim_messagef (SCPE_ARG, "Count cannot be zero\n"); - cptr = get_glyph (cptr, gbuf, 0); // get dev|file0 param + get_glyph (cptr, gbuf, 0); // get dev param + cptr = get_glyph_quoted (cptr, fn0, 0); // re-read using get_glyph_quoted to do not + // change the capitalization of file name if ((strlen(gbuf) != 4) || (strncmp(gbuf, "CDP", 3)) || (gbuf[3] < '1') || (gbuf[3] > '3') ) { // is a file - strcpy(fn0, gbuf); } else { - // is cpd1 cpd2 or cpd3 device + // is cdp1 cdp2 or cdp3 device dptr = find_unit (gbuf, &uptr); /* locate unit */ if (dptr == NULL) /* found dev? */ return SCPE_NXDEV; @@ -742,6 +833,7 @@ static t_stat deck_split_cmd(CONST char *cptr) return SCPE_NXUN; if ((uptr->flags & UNIT_ATT) == 0) /* attached? */ return SCPE_NOTATT; + // get the file name strcpy(fn0, uptr->filename); sim_card_detach(uptr); // detach file from cdp device to be splitted } @@ -842,11 +934,10 @@ static t_stat deck_join_cmd(CONST char *cptr) static t_stat deck_print_cmd(CONST char *cptr) { char fn[4*CBUFSIZE]; - char line[81]; t_stat r; uint16 DeckImage[80 * MAX_CARDS_IN_DECK]; - int i,c,nc,nCards; + int nCards; while (sim_isspace (*cptr)) cptr++; // trim leading spc cptr = get_glyph_quoted (cptr, fn, 0); // get next param: source filename @@ -858,27 +949,7 @@ static t_stat deck_print_cmd(CONST char *cptr) r = deck_load(fn, DeckImage, &nCards); if (r != SCPE_OK) return sim_messagef (r, "Cannot read deck to print (%s)\n", fn); - for (nc=0; nc +static t_stat deck_echolast_cmd(CONST char *cptr) +{ + char gbuf[4*CBUFSIZE]; + t_stat r; + + uint16 DeckImage[80 * MAX_CARDS_IN_DECK]; + int i,nc,nCards, ic, nh, ncdr; + + while (sim_isspace (*cptr)) cptr++; // trim leading spc + + cptr = get_glyph (cptr, gbuf, 0); // get cards count param + nCards = (int32) get_uint (gbuf, 10, MAX_CARDS_IN_READ_TAKE_HOPPER, &r); + if (r != SCPE_OK) return sim_messagef (SCPE_ARG, "Invalid count value\n"); + if (nCards == 0) return sim_messagef (SCPE_ARG, "Count cannot be zero\n"); + + cptr = get_glyph (cptr, gbuf, 0); // get dev param + if ((strlen(gbuf) != 4) || (strncmp(gbuf, "CDR", 3)) || + (gbuf[3] < '1') || (gbuf[3] > '3') ) { + return sim_messagef (SCPE_ARG, "Device should be CDR1 CDR2 or CDR3\n"); + } + ncdr = gbuf[3] - '1'; // ncdr=0 for cdr1, =1 for cdr2, and so on + if ((ncdr >= 0) && (ncdr < 3)){ + // safety check + } else { + return sim_messagef (SCPE_ARG, "Invalid Device number\n"); + } + + if (*cptr) return sim_messagef (SCPE_ARG, "Extra unknown parameters\n"); + + // get nCards form read card take hopper buffer + // that is, print last nCards read + + // get last nCards cards, so + // first card to echo is count ones before last one + nh = ReadHopperLast[ncdr] - (nCards-1); + nh = nh % MAX_CARDS_IN_READ_TAKE_HOPPER; + for (nc=0; nc= 10E10 THUS CANNOT BE CONVERTED TO FIX + N10 10 0000 0000 + N51 51 0000 0000 + ONET 00 0001 0000 + ERTHX 00 0000 0000 + ARTHA 00 0000 0000 + 1 + 1 (U) AND (ACC) FLOAT <- (L) FIXED POINT + 1 + E00AF STD ARTHA FLOAT TO UP + LDD E00AE AND ACC + STU ACC ARTHA + 1 + 1 (U) FLOAT <- (L) FIXED POINT + 1 + E00AE STD ERTHX FLOAT TO UP + RAU 8002 AE0 ONLY + AE0 SCT 0000 NORMALIZE + STL ARTHB + BOV AD1 ZERO CHECK + RAL 8003 + SRD 0002 ROUND FOR + SLT 0002 PLACING EXP + NZU AE6 CHECK ROUND + LDD 8003 OVERFLOW + SRT 0001 + ALO 8001 AE6 + AE6 BMI AE2 INSERT + ALO AJ3 AE5 EXPONENT + AE2 SLO AJ3 AE5 + AE5 SLO ARTHB + RAU 8002 ERTHX + AJ3 00 0000 0060 + ARTHB 00 0000 0000 + 1 + 1 PUNCH CARD + 1 + E00AR STD ERTHX PUNCH OUT + LDD J0008 + SIA J0008 STORE STMNT + LDD ONET + SDA NVARS AND NVARS TO PCH + SLO 8001 IF STMT ZERO + NZE AR3 PUNCH IF + RAL 8000 8000 IS NEG + BMI AR3 ERTHX ELSE EXIT + AR3 LDD AR3A AR5 INIT PCH CARD + AR3A RAL NVARS DEC NVARS + SLO ONET + BMI AR8 TEST WORD + STL NVARS COUNT + ALO 8002 GET NWORD ADDR + RAL W0002 IN LOWER + LDD NWORD + SDA NWORD STORE NUM OF WORDS TO PUNCH + SLT 0004 + LDD ADWRD + SDA ADWRD AR4 STORE ADDR OF WORD TO PUNCH + AR4 RAL NPCH IS CARD FULL + SLO ARN7 + BMI AR4A + PCH J0001 YES PUNCH AND + LDD AR4A AR5 CALL INIT CARD + AR4A RAL NPCH INCR NO OF + ALO ONET PUNCHED WORDS NPCH + STL NPCH + RAL ADWRD INDR ADWRD + ALO ONET + STL ADWRD + SLO ONET + ALO 8002 GET ADWRD + RAL Y0000 CONTENTS + STL DATWD STORE IN DATWD + RAU DATLD + ALO NPCH STORE AT + ALO 8003 J0000 PLUS + STD J0000 NPCH + RAL NWORD DECR VAR NWORDS + SLO ONET TO BE PUNCHED + NZE AR3A + BMI AR3A + STL NWORD AR4 + AR5 STD AR5X SUB INIT PCH CARD + RAL J0008 INCR CARD + ALO ONET NUMBER + STL J0008 + STU NPCH CARD WITH ZERO + STD J0001 PUNCHED WORDS + STD J0002 SET PUNCH + STD J0003 BAND TO + STD J0004 ZEROES + STD J0005 + STD J0006 + STD J0007 AR5X + AR8 PCH J0001 ERTHX PUNCH + ONET 00 0001 0000 + ARN7 00 0007 0000 + J0008 00 0000 0000 CARD COUNTER + J0010 80 0000 0080 CONTROL CNST + AR5X 00 0000 0000 EXIT FOR SUB INIT PCH CARD + NVARS 00 0000 0000 NUM OF VARS TO PCH + NWORD 00 0000 0000 NUM OF WORDS PER VAR TO PCH + ADWRD 00 0000 0000 ADDR OF WORD TO PCH + NPCH 00 0000 0000 NUM OF WORDS PUNCHED IN CHARD + DATWD 00 0000 0000 DATA WORD TO BE PUNCHED + 1 + 1 READ CARD + 1 + E00AQ STD ERTHX READ IN + LDD ONET + SDA NVARS NVARS TO READ + STU NPCH AQ3A INIT TO ZERO + AQ3A RAL NVARS DEC NVARS + SLO ONET + BMI ERTHX EXIT IF ZERO + STL NVARS + ALO 8002 GET NWORD ADDR + RAL W0002 IN LOWER + LDD NWORD + SDA NWORD STORE NUM OF WORDS TO RD + SLT 0004 + LDD ADWRD + SDA ADWRD AQ4 STORE ADDR OF WORD TO RD + AQ4 RAL NPCH CHECK IF SHOULD RD NEW CARD + NZE AQ4A + RCD P0001 YES READ CARD + LDD ARN7 + STD NPCH AQ4A + AQ4A RAL NPCH DECR NO OF AVAILABLE + SLO ONET PUNCHED WORDS NPCH IN READ CARD + STL NPCH + RAL ARN7 + SLO NPCH GET WORD AT + ALO 8002 P0000 PLUS + LDD P0000 NPCH IN DIST + STD DATWD STORE IT IN DATWD + RAU DATLD + ALO ADWRD INCR ADWRD + ALO ONET + STL ADWRD + SLO ONET + ALO 8003 SET ADWRD + STD Y0000 CONTENTS FROM UPPER + RAL NWORD DECR VAR NWORDS + SLO ONET TO BE READ + NZE AQ3A + BMI AQ3A + STL NWORD AQ4 + ONET 00 0001 0000 + DATLD LDD DATWD 8002 LOAD CARD WORD INTO DIST AND JUMP TO LOWER + 1 + 1 ALARM IF TRY TO USE A NOT DEFINED SUBROUTINE + 1 + E00AK HLT 9010 8001 ALARM FIX ** FIX UNDEF + E00AL HLT 9011 8001 ALARM FLOAT ** FIX UNDEF + E00LQ HLT 9302 8001 ALARM FLOAT ** FLOAT UNDEF + E00AB HLT 9001 8001 ALARM LOGF UNDEF + E00AC HLT 9002 8001 ALARM EXPF UNDEF + E00LO HLT 9300 8001 ALARM LNF UNDEF + E00LP HLT 9301 8001 ALARM EXPNF UNDEF + E00AV HLT 9021 8001 ALARM COSF UNDEF + E00AW HLT 9022 8001 ALARM SINF UNDEF + E00AX HLT 9023 8001 ALARM SQRTF UNDEF + E00AY HLT 9024 8001 ALARM ABSF UNDEF + E00AZ HLT 9025 8001 ALARM INTF UNDEF + E00BA HLT 9026 8001 ALARM MAXF UNDEF + EZZTY HLT 9099 8001 ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + 1 + 1 START OF SUBROUTINES + 1 + 1 (L) AND (ACC) FIXED <- (L) FIXED ** (ACC) FIXED + 1 + E00AK STD ERTHX POWER FIX FIX. M ** P + STL ARTHA AK1 M IS ARGMNT + AK1 RAM ACC P EQUALS + STL ARTHB ABVAL POWER + RAL ONE H IS RESULT + STL ARTHC AK3 INIT TO ONE + AK3 RAU ARTHB P IS GTST + MPY N50 INTGR IN + STU ARTHB P OVER TWO + RAL 8002 IS REMAINDER + NZE AK5 ZERO + RAU ARTHC IF NOT H IS + MPY ARTHA H TIMES M + NZU AK12 + STL ARTHC AK5 + AK5 RAU ARTHB + NZU AK6 IS P ZERO + RAU ARTHA IF NOT + MPY 8001 M EQUALS + NZU AK12 + STL ARTHA AK3 M SQUARED + AK6 RAU ACC IS POWER NEG + BMI AK7 IF SO IS H + RAM ARTHC ZERO + NZE AK8 IF NOT IS H + SLO ONE ONE + NZE AK10 AK7 + AK7 RAL ARTHC AK11 EXHIBIT H + AK10 RAL 8003 AK11 + AK11 STL ACC ERTHX + AK12 LDD ERTHX + HLT 0003 8001 ALARM OVERFLOW. FIX**FIX RESULTS IN VALUE >= 10E10 + AK8 LDD ERTHX + HLT 0010 8001 ALARM ZERO RAISED TO NEG + N50 50 0000 0000 + ONE 00 0000 0001 + ARTHC 00 0000 0000 + 1 + 1 (U) AND (ACC) FLOAT <- (U) FLOAT ** (ACC) FIXED + 1 + E00AL STD ERTHX POWER FLOAT FIX. M ** P + STU ARTHA AL1 M IS ARGMNT + AL1 RAM ACC P EQUALS + STL ARTHB ABVAL POWER + RAL FP1 H IS RESULT + STL ARTHC AL3 INIT TO FLOAT ONE + AL3 RAU ARTHB P IS GTST + MPY N50 INTGR IN + STU ARTHB P OVER TWO + RAL 8002 IS REMAINDER + NZE AL5 ZERO + RAU ARTHC IF NOT H IS + FMP ARTHA H TIMES M + BOV AL12 + STU ARTHC AL5 + AL5 RAU ARTHB + NZU AL6 IS P ZERO + RAU ARTHA IF NOT + FMP 8001 M EQUALS + BOV AL12 + STU ARTHA AL3 M SQUARED + AL6 RAU ACC IS POWER NEG + BMI AL7 IF SO IS H + RAM ARTHC ZERO + NZE AL8 IF NOT CALC + RAU FP1 H RECIPROCAL + FDV ARTHC AL11 + AL7 RAU ARTHC AL11 EXHIBIT H + AL11 STU ACC ERTHX + AL12 LDD ERTHX + HLT 0049 8001 ALARM OVERFLOW. FLOAT**FIX RESULTS IN VALUE >= 10E49 + AL8 LDD ERTHX + HLT 0011 8001 ALARM ZERO RAISED TO NEG + N50 50 0000 0000 + FP1 10 0000 0051 + 1 + 1 (U) FLOAT <- 10 ** (U) FLOAT + 1 + E00AC STD ERTHX EXPONENTIAL + NZE AC5 IS ARGUMENT + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + SRT 0002 ZERO + STU ARTHC IF NOT LET + RSM 8002 N BE MANTSA + ALO N52 X BE POWER + BMI AC4 IS X GRTR + SLT 0001 THAN TEN + NZU AC5 OR LESS THAN + SRT 0005 MINUS EIGHT + ALO AC6 IF X WITHIN + STL ARTHB BOUNDS GEN + RAU ARTHC INT AND + SRT 0006 ARTHB FRACT PARTS + N52 52 0000 0000 OF ARGUMENT + AC6 SRT 0000 IS ARG NEG + BMI AC8 IF SO INT IS + STU ARTHB AC1 INT MINUS 1 + AC8 SUP ONE AND FRACT IS + STU ARTHB FRACT PLUS 1 + RAL 8002 + ALO N999 AC1 + AC1 STL ARTHC ARTHC IS FRAC PART + RAU 8002 ARTHB IS INT PART + MPY AC18 GENERATE + RAU 8003 + AUP AC17 POLYNOMIAL + MPY ARTHC + RAU 8003 APPROXIM + AUP AC16 ATION + MPY ARTHC + RAU 8003 FOR + AUP AC15 + MPY ARTHC EXPONENTIAL + RAU 8003 + AUP AC14 + MPY ARTHC + RAU 8003 + AUP AC13 + MPY ARTHC + RAU 8003 + AUP AC12 + MPY ARTHC SQUARE + RAU 8003 RESULT + AUP N10 SCALE AND + MPY 8003 FLOAT THEN + SRT 0001 EXIT + STU ARTHA + RAU AC19 + AUP ARTHB + BMI AC20 + SRT 0002 + NZU AC21 + AUP ARTHA + SRT 0008 AC20 + AC4 RAL ARTHC + BMI AC21 + RAU 8003 ERTHX RESULT ZERO + AC5 RAU FP1 ERTHX RESULT 1 BECAUSE ARGMNT IS ZERO + AC20 RAU 8002 ERTHX RESULT IN UPPER + AC21 LDD ERTHX + HLT 0049 8001 ALARM OVERFLOW. 10**FLOAT RESULTS IN VALUE >= 10E49 + AC12 11 5129 2776 + AC13 06 6273 0884 + AC14 02 5439 3575 + AC15 00 7295 1737 + AC16 00 1742 1120 + AC17 00 0255 4918 + AC18 00 0093 2643 + AC19 00 0000 0051 + N999 99 9999 9999 + N10 10 0000 0000 + ONE 00 0000 0001 + FP1 10 0000 0051 + ARTHC 00 0000 0000 + 1 + 1 (U) FLOAT <- LOG 10 (U) FLOAT + 1 + E00AB NZE AB10 IF LOG ARG ZERO + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + BMI AB10 OR NEG ALARM + STD ERTHX + SRT 0002 + STL ARTHB STORE POWER + RAU 8003 FORM Z + AUP AB1 EQUAL ARG + STU ARTHC MINUS ROOT + SUP AB2 TEN OVER ARG + DVR ARTHC PLUS ROOT + STL ARTHA TEN + RAU 8002 + MPY 8001 Z SQUARE + STU ARTHC + RAU 8003 GENERATE + MPY AB7 + RAU 8003 POLYNOMIAL + AUP AB6 + MPY ARTHC APPROXIMATN + RAU 8003 + AUP AB5 + MPY ARTHC + RAU 8003 + AUP AB4 + MPY ARTHC + RAU 8003 + AUP AB3 + MPY ARTHA + RAL 8003 + ALO N50 + SRT 0002 + ALO ARTHB ADD POWER + SLO N50 + SRD 0002 ROUND + RAU 8002 + SCT 0000 NORMALIZE + BOV AB12 + BMI AB13 + SUP AB9 AB11 ADJUST + AB11 SUP 8002 AB12 POWER + AB12 RAU 8003 + FSB FP1 ERTHX + AB13 AUP AB9 AB11 + AB10 HLT 0001 8001 ALARM LOG (ZERO OR NEGAVIVE) + AB1 00 3162 2780 + AB2 00 6324 5560 + AB3 86 8591 7180 + AB4 28 9335 5240 + AB5 17 7522 0710 + AB6 09 4376 4760 + AB7 19 1337 7140 + N50 50 0000 0000 + FP1 10 0000 0051 + AB9 00 0000 0054 + ARTHC 00 0000 0000 + 1 + 1 (U) AND (ACC) FLOAT <- (U) FLOAT ** (ACC) FLOAT + 1 U**ACC = 10**(LOG10(U)*ACC) + 1 = EXP(LOG10(U)*ACC) + 1 + E00LQ STD LQ1 + LDD E00AB LOG 10 (U) + FMP ACC MULT BY ACC + LDD LQ1 E00AC 10 ** U + LQ1 00 0000 0000 + 1 + 1 (U) FLOAT <- LOG E (U) FLOAT + 1 LN(U) = LOG(U) / LOG(E) + 1 LOG10(E)=0.4342944819 + 1 + E00LO STD LQ1 + LDD E00AB LOG 10 (U) + FDV LOGE LQ1 DIV BY LOG(E) CONST + LQ1 00 0000 0000 + LOGE 43 4294 4850 + 1 + 1 (U) FLOAT <- E ** (U) FLOAT + 1 EXPN(U) = E ** U = EXP(LOG10(E)*U) + 1 E=2.71828182846 + 1 + E00LP STD LQ1 + FMP LOGE MULT BY LOG(E) CONST + LDD LQ1 E00AC 10 ** U + LQ1 00 0000 0000 + LOGE 43 4294 4850 + 1 + 1 (U) FLOAT <- ABSOLUTE VALUE (U) FLOAT + 1 + E00AY NZE 8001 EXIT IF ZERO + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + STD ERTHX + RAM 8003 REMOVE SGN + RAU 8002 ERTHX RESULT IN UPPER AND EXIT + 1 + 1 (U) FLOAT <- INTEGER PART (U) FLOAT + 1 + E00AZ NZE 8001 EXIT IF ZERO + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + STD ERTHX + STU ARTHC SAVE ARG + SRT 0002 EXP IN LOWER + STU ARTHA MANT IN H + RSM 8002 MAKE EXP NEG + ALO N57 + BMI AZ4 BIG NUM SO NO FRACT PART TO REMOVE + ALO N01 + SLT 0001 + NZU AZ5 SMALL NUM SO NO INT PART + SRT 0005 SET AS RIGHT + ALO AZ6 SHIFTS TO DO + STL ARTHB + RAU ARTHA ARTHB + N57 57 0000 0000 + N01 01 0000 0000 + AZ6 SRT 0000 + RAU 8003 AE0 GO TO FIX TO FLOAT CONVERSION ROUTINE + AZ5 RAU 8002 + RAU 8002 ERTHX RETURN ZERO + AZ4 RAU ARTHC ERTHX RETURN THE ARG UNCHANGED + 1 + 1 (U) FLOAT <- MAX (FLOAT, FLOAT, ...) + 1 SHOULD HAVE TWO OR MORE FLOAT PARAMETERS + 1 + E00BA STD ERTHX + STU ARTHA ARG IS MAX + RAL ERTHX BA0 + BA0 SLO BA10 + BMI BA9 NO MORE ARGS + RAL ERTHX SET ARG ADDR + LDD BA1 TO BE READ + SDA BA1 BA1 + BA1 RAU 0000 READ ARG + STU ARTHB + FSB ARTHA IS GRTR THAN + BMI BA2 CURRENT RESULT + RAU ARTHB YES STORE AS + STU ARTHA BA2 NEW RESULT + BA2 RAL ERTHX SELECT NEXT + SLO ONET ARG + STL ERTHX BA0 + BA9 RAU ARTHA ERTHX RESULT IN UPPER + BA10 00 P0000 0000 FIST ARG ADDR + 1 + 1 (U) FLOAT <- SQUARE ROOT (U) FLOAT + 1 + E00AX NZE 8001 EXIT IF ZERO + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + BMI AX1 ALARM SQRT(NEG) + STD ERTHX + SRT 0002 + NZU AX2 TEST FOR ZRO + SLO N01 CONVERT FORTRANSIT EXP (1.0=1E51) TO IT EXP (1.0=1E50) + STL ARTHB BREAK UP EXP + RAL 8003 AND MANTISSA + SLT 0002 CALCULATE + STL ARTHA INITIAL X + AUP ONE AX3 + AX4 RAU ARTHA CALCULATE + DVR ARTHC NEXT X + SLO 8001 VALUE + NZE AX5 + BMI AX5 TEST FOR END + ALO 8001 + ALO 8001 AX3 + AX3 DVR TWO RECYCLE + STL ARTHC AX4 + AX5 RAL ARTHB MODIFY + ALO N49 EXPONENT + SRT 0008 + DIV TWO + ALO 8003 + STL ARTHB TEST EVEN OR + NZU AX6 ODD EXP + RAU ARTHC EXP ODD + SRT 0001 + MPY AX11 MPY BY SQRT + SRD 0010 AX7 OF 10 + AX7 SLT 0002 + ALO ARTHB + ALO ONE EXP 50 TO 51 + RAU 8002 ERTHX GO TO EXIT + AX6 RAL ARTHC EXP EVEN + SRD 0002 AX7 + AX2 RAU 8003 ERTHX RESULT ZERO + AX1 HLT 0012 8001 ALARM SQRT WITH NEGATIVE ARGUMENT + ONE 00 0000 0001 CONSTANTS + TWO 00 0000 0002 + N49 49 0000 0000 + AX11 03 1622 7766 + 1 + 1 (U) FLOAT <- COSINUS (U) FLOAT (ARG IN RADIANS: COS(PI/2) = 0) + 1 + E00AV STD ERTHX AV0 + AV0 NZE AV4 COS(0) IS ONE + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + SRT 0002 ARGUMENT + STU ARTHA ALARM IF PWR + RSM 8002 OVERSCALE + ALO N01 CONVERT FORTRANSIT EXP (1.0=1E51) TO IT EXP (1.0=1E50) + ALO N57 COSX EQUALS + BMI AV2 ONE IF PWR + SLO AV3 UNDERSCALE + BMI AV4 + SRT 0004 + ALO AV5 + STL AV6 + RAU ARTHA FORM + MPY AV7 AV6 FRACTIONAL + AV6 HLT AV6 AV23 AND INTGRL + AV23 STL ARTHC PARTS + RAU 8003 + MPY N50 FORM S AS + STL ARTHB ONE MINUS + RSM ARTHC TWICE ABVAL + SML 8001 OF FRACTNL + ALO N999 PART + RAU 8002 + STU ARTHA + MPY 8001 FORM SINE + STU ARTHC + RAU AV16 POLYNOMIAL + MPY ARTHC APPROXIMATOR + RAU 8003 + AUP AV15 + MPY ARTHC + RAU 8003 + AUP AV14 + MPY ARTHC + RAU 8003 + AUP AV13 + MPY ARTHC + SRT 0001 + RAU 8003 + AUP PIH EQUALS ONE + MPY ARTHA + SCT 0000 + BOV AV19 + STL ARTHA + RAL 8003 ROUND + SRT 0002 AND + STL ARTHC ADJUST + RSU ARTHA POWER + SRT 0002 + BMI AV25 + SUP 8003 + ALO N50 AV24 + AV24 AUP ARTHC + SLT 0002 AV22 + AV22 STU ARTHA DETERMINE + RAU ARTHB SIGN OF + NZU AV20 RESULT + RSL ARTHA AV26 + AV20 RAL ARTHA AV26 + AV25 SUP 8003 + SLO N50 AV24 + AV2 RAU ARTHB OVERSCALE + LDD ERTHX DISPLAY + HLT 0013 8001 ALARM RADIAN ARG TOO BIG + AV26 RAU 8002 + BMI AV27 + AUP ONE ERTHX + AV27 SUP ONE ERTHX + AV4 RAL AV21 AV26 COSX IS ONE + AV19 RAL 8002 COSX IS ZERO + SLO 8001 AV26 + AV17 RAU AV21 AV22 COSX IS PLUS + AV3 11 0000 0000 OR MINUS 1 + AV5 SRD 0011 AV23 + AV7 31 8309 8862 + PIH 15 7079 6327 PI / 2 INTEGER + AV13 - 64 5963 7111 + AV14 07 9689 6793 + AV15 - 00 4673 7656 + AV16 00 0151 4842 + AV21 10 0000 0050 + N999 99 9999 9999 + N50 50 0000 0000 + ONE 00 0000 0001 + N01 01 0000 0000 + N57 57 0000 0000 + 1 + 1 (U) FLOAT <- SINUS (U) FLOAT (ARG IN RADIANS: SIN(PI/2) = 1) + 1 + E00AW NZE 8001 SIN(0) IS ZERO + NZU EZZTY ALARM FUNCTION ARG IS FIX BUT SHOULD BE FLOAT + STD ERTHX + STU ARTHA + RAU PIHF + FSB ARTHA AV0 SIN A = COS(PI/2 - A) + PIHF 15 7079 6351 PI / 2 FLOAT + 1 + 1 END OF FORTRAN PACKAGE + 1 + \ No newline at end of file diff --git a/I650/sw/fortransit/pack_res1.txt b/I650/sw/fortransit/pack_res1.txt new file mode 100644 index 00000000..73f4d43e --- /dev/null +++ b/I650/sw/fortransit/pack_res1.txt @@ -0,0 +1,21 @@ + 1 + 1 fortran + 1 package reservation + 1 for package build + 1 + 1 includes + 1 - float fix conversions + 1 - fortran read punch statemens + 1 - fortran power operator + 1 - fortran functions + 1 excludes + 1 - nothing + 1 + regy0002 0002 fortransit + 1 vars start addr + blr 0000 1400 reserve all + 1 drum except + 1 pack space + 1 + 1 end of package reservation + 1 diff --git a/I650/sw/fortransit/pack_res2.txt b/I650/sw/fortransit/pack_res2.txt new file mode 100644 index 00000000..f02f853b --- /dev/null +++ b/I650/sw/fortransit/pack_res2.txt @@ -0,0 +1,21 @@ + 1 + 1 fortran + 1 package reservation + 1 for package use + 1 + 1 includes + 1 - float fix conversions + 1 - fortran read punch statemens + 1 - fortran power operator + 1 - fortran functions + 1 excludes + 1 - nothing + 1 + regp1951 1960 read band + regj1977 1986 punch band + regw1988 1998 storage band + blr 1401 1999 reserve + 1 pack space + 1 + 1 end of package reservation + 1 diff --git a/I650/sw/fortransit/pack_src.txt b/I650/sw/fortransit/pack_src.txt new file mode 100644 index 00000000..12dd94b3 --- /dev/null +++ b/I650/sw/fortransit/pack_src.txt @@ -0,0 +1,684 @@ + 1 + 1 fortran package + 1 source code + 1 + blr 1945 1950 entry power subr total reservation + regp1951 1960 read band 1947 - 1999, 0000 + blr 1961 1968 entry built-in subr (54 words) + blr 1969 1976 entry func subr + regj1977 1986 punch band + blr 1987 1987 + regw1988 1998 storage band + 1 + 1 save index registers + 1 + ezzzastdezzzx + ldd 8005 + stdezzia + ldd 8006 + stdezzib + ldd 8007 + stdezzic ezzzx + 1 + 1 restore saved index registers and return to erthx + 1 + ezzzblddezzia + raa 8001 + lddezzib + rab 8001 + lddezzic + rac 8001 erthx + ezzzx 00 0000 0000 + ezzia 00 0000 0000 + ezzib 00 0000 0000 + ezzic 00 0000 0000 + 1 + 1 overflow checking + 1 + e00aabov 8001 + hlt 0100 8001 alarm arithmetic overflow + 1 + 1 (l) fixed point <- (u) float + 1 + e00thstderthx float upper + srt 0002 to fix lower + stuartha save mantissa + ram 8002 test exp + slon51 store zero + bmiad1 if less than + slon10 51 alarm + bmi ad3 if grtr than + srt 0004 60 + aloonet + lddad2a modify + sdaad2 shift + ralartha + slt 0002 ad2 + ad1 ral 8003 erthx store zero + ad2 srt 0000 erthx shift const + ad2a srt 0000 erthx + ad3 ldderthx + hlt 0501 8001 alarm float >= 10e10 thus cannot be converted to fix + n10 10 0000 0000 + n51 51 0000 0000 + onet 00 0001 0000 + erthx 00 0000 0000 + artha 00 0000 0000 + 1 + 1 (u) and (acc) float <- (l) fixed point + 1 + e00afstdartha float to up + ldd e00ae and acc + stuacc artha + 1 + 1 (u) float <- (l) fixed point + 1 + e00aestderthx float to up + rau 8002 ae0 only + ae0 sct 0000 normalize + stlarthb + bovad1 zero check + ral 8003 + srd 0002 round for + slt 0002 placing exp + nzu ae6 check round + ldd 8003 overflow + srt 0001 + alo 8001 ae6 + ae6 bmiae2 insert + aloaj3 ae5 exponent + ae2 sloaj3 ae5 + ae5 sloarthb + rau 8002 erthx + aj3 00 0000 0060 + arthb 00 0000 0000 + 1 + 1 punch card + 1 + e00arstderthx punch out + lddj0008 + siaj0008 store stmnt + lddonet + sdanvars and nvars to pch + slo 8001 if stmt zero + nzear3 punch if + ral 8000 8000 is neg + bmiar3 erthx else exit + ar3 lddar3a ar5 init pch card + ar3a ralnvars dec nvars + sloonet + bmiar8 test word + stlnvars count + alo 8002 get nword addr + ralw0002 in lower + lddnword + sdanword store num of words to punch + slt 0004 + lddadwrd + sdaadwrd ar4 store addr of word to punch + ar4 ralnpch is card full + sloarn7 + bmiar4a + pchj0001 yes punch and + lddar4a ar5 call init card + ar4a ralnpch incr no of + aloonet punched words npch + stlnpch + raladwrd indr adwrd + aloonet + stladwrd + sloonet + alo 8002 get adwrd + raly0000 contents + stldatwd store in datwd + raudatld + alonpch store at + alo 8003 j0000 plus + stdj0000 npch + ralnword decr var nwords + sloonet to be punched + nze ar3a + bmiar3a + stlnword ar4 + ar5 stdar5x sub init pch card + ralj0008 incr card + aloonet number + stlj0008 + stunpch card with zero + stdj0001 punched words + stdj0002 set punch + stdj0003 band to + stdj0004 zeroes + stdj0005 + stdj0006 + stdj0007 ar5x + ar8 pchj0001 erthx punch + onet 00 0001 0000 + arn7 00 0007 0000 + j0008 00 0000 0000 card counter + j0010 80 0000 0080 control cnst + ar5x 00 0000 0000 exit for sub init pch card + nvars 00 0000 0000 num of vars to pch + nword 00 0000 0000 num of words per var to pch + adwrd 00 0000 0000 addr of word to pch + npch 00 0000 0000 num of words punched in chard + datwd 00 0000 0000 data word to be punched + 1 + 1 read card + 1 + e00aqstderthx read in + lddonet + sdanvars nvars to read + stunpch aq3a init to zero + aq3a ralnvars dec nvars + sloonet + bmierthx exit if zero + stlnvars + alo 8002 get nword addr + ralw0002 in lower + lddnword + sdanword store num of words to rd + slt 0004 + lddadwrd + sdaadwrd aq4 store addr of word to rd + aq4 ralnpch check if should rd new card + nzeaq4a + rcdp0001 yes read card + lddarn7 + stdnpch aq4a + aq4a ralnpch decr no of available + sloonet punched words npch in read card + stlnpch + ralarn7 + slonpch get word at + alo 8002 p0000 plus + lddp0000 npch in dist + stddatwd store it in datwd + raudatld + aloadwrd incr adwrd + aloonet + stladwrd + sloonet + alo 8003 set adwrd + stdy0000 contents from upper + ralnword decr var nwords + sloonet to be read + nze aq3a + bmiaq3a + stlnword aq4 + onet 00 0001 0000 + datldldddatwd 8002 load card word into dist and jump to lower + 1 + 1 alarm if try to use a not defined subroutine + 1 + e00akhlt 9010 8001 alarm fix ** fix undef + e00alhlt 9011 8001 alarm float ** fix undef + e00lqhlt 9302 8001 alarm float ** float undef + e00abhlt 9001 8001 alarm logf undef + e00achlt 9002 8001 alarm expf undef + e00lohlt 9300 8001 alarm lnf undef + e00lphlt 9301 8001 alarm expnf undef + e00avhlt 9021 8001 alarm cosf undef + e00awhlt 9022 8001 alarm sinf undef + e00axhlt 9023 8001 alarm sqrtf undef + e00ayhlt 9024 8001 alarm absf undef + e00azhlt 9025 8001 alarm intf undef + e00bahlt 9026 8001 alarm maxf undef + ezztyhlt 9099 8001 alarm function arg is fix but should be float + 1 + 1 start of subroutines + 1 + 1 + 1 (l) and (acc) fixed <- (l) fixed ** (acc) fixed + 1 + e00akstderthx power fix fix. m ** p + stlartha ak1 m is argmnt + ak1 ramacc p equals + stlarthb abval power + ralone h is result + stlarthc ak3 init to one + ak3 rauarthb p is gtst + mpyn50 intgr in + stuarthb p over two + ral 8002 is remainder + nze ak5 zero + rauarthc if not h is + mpyartha h times m + nzuak12 + stlarthc ak5 + ak5 rauarthb + nzu ak6 is p zero + rauartha if not + mpy 8001 m equals + nzuak12 + stlartha ak3 m squared + ak6 rauacc is power neg + bmi ak7 if so is h + ramarthc zero + nze ak8 if not is h + sloone one + nzeak10 ak7 + ak7 ralarthc ak11 exhibit h + ak10 ral 8003 ak11 + ak11 stlacc erthx + ak12 ldderthx + hlt 0003 8001 alarm overflow. fix**fix results in value >= 10e10 + ak8 ldderthx + hlt 0010 8001 alarm zero raised to neg + n50 50 0000 0000 + one 00 0000 0001 + arthc 00 0000 0000 + 1 + 1 (u) and (acc) float <- (u) float ** (acc) fixed + 1 + e00alstderthx power float fix. m ** p + stuartha al1 m is argmnt + al1 ramacc p equals + stlarthb abval power + ralfp1 h is result + stlarthc al3 init to float one + al3 rauarthb p is gtst + mpyn50 intgr in + stuarthb p over two + ral 8002 is remainder + nze al5 zero + rauarthc if not h is + fmpartha h times m + boval12 + stuarthc al5 + al5 rauarthb + nzu al6 is p zero + rauartha if not + fmp 8001 m equals + boval12 + stuartha al3 m squared + al6 rauacc is power neg + bmi al7 if so is h + ramarthc zero + nze al8 if not calc + raufp1 h reciprocal + fdvarthc al11 + al7 rauarthc al11 exhibit h + al11 stuacc erthx + al12 ldderthx + hlt 0049 8001 alarm overflow. float**fix results in value >= 10e49 + al8 ldderthx + hlt 0011 8001 alarm zero raised to neg + n50 50 0000 0000 + fp1 10 0000 0051 + 1 + 1 (u) float <- 10 ** (u) float + 1 + e00acstderthx exponential + nze ac5 is argument + nzu ezzty alarm function arg is fix but should be float + srt 0002 zero + stuarthc if not let + rsm 8002 n be mantsa + alon52 x be power + bmiac4 is x grtr + slt 0001 than ten + nzuac5 or less than + srt 0005 minus eight + aloac6 if x within + stlarthb bounds gen + rauarthc int and + srt 0006 arthb fract parts + n52 52 0000 0000 of argument + ac6 srt 0000 is arg neg + bmiac8 if so int is + stuarthb ac1 int minus 1 + ac8 supone and fract is + stuarthb fract plus 1 + ral 8002 + alon999 ac1 + ac1 stlarthc arthc is frac part + rau 8002 arthb is int part + mpyac18 generate + rau 8003 + aupac17 polynomial + mpyarthc + rau 8003 approximation + aupac16 + mpyarthc + rau 8003 for + aupac15 + mpyarthc exponential + rau 8003 + aupac14 + mpyarthc + rau 8003 + aupac13 + mpyarthc + rau 8003 + aupac12 + mpyarthc square + rau 8003 result + aupn10 scale and + mpy 8003 float then + srt 0001 exit + stuartha + rauac19 + auparthb + bmiac20 + srt 0002 + nzuac21 + aupartha + srt 0008 ac20 + ac4 ralarthc + bmi ac21 + rau 8003 erthx result zero + ac5 raufp1 erthx result 1 because argmnt is zero + ac20 rau 8002 erthx result in upper + ac21 ldderthx + hlt 0049 8001 alarm overflow. 10**float results in value >= 10e49 + ac12 11 5129 2776 + ac13 06 6273 0884 + ac14 02 5439 3575 + ac15 00 7295 1737 + ac16 00 1742 1120 + ac17 00 0255 4918 + ac18 00 0093 2643 + ac19 00 0000 0051 + n999 99 9999 9999 + n10 10 0000 0000 + one 00 0000 0001 + fp1 10 0000 0051 + arthc 00 0000 0000 + 1 + 1 (u) float <- log 10 (u) float + 1 + e00abnze ab10 if log arg zero + nzu ezzty alarm function arg is fix but should be float + bmiab10 or neg alarm + stderthx + srt 0002 + stlarthb store power + rau 8003 form z + aupab1 equal arg + stuarthc minus root + supab2 ten over arg + dvrarthc plus root + stlartha ten + rau 8002 + mpy 8001 z square + stuarthc + rau 8003 generate + mpyab7 + rau 8003 polynomial + aupab6 + mpyarthc approximatn + rau 8003 + aupab5 + mpyarthc + rau 8003 + aupab4 + mpyarthc + rau 8003 + aupab3 + mpyartha + ral 8003 + alon50 + srt 0002 + aloarthb add power + slon50 + srd 0002 round + rau 8002 + sct 0000 normalize + bovab12 + bmi ab13 + supab9 ab11 adjust + ab11 sup 8002 ab12 power + ab12 rau 8003 + fsbfp1 erthx + ab13 aupab9 ab11 + ab10 hlt 0001 8001 alarm log (zero or negavive) + ab1 00 3162 2780 + ab2 00 6324 5560 + ab3 86 8591 7180 + ab4 28 9335 5240 + ab5 17 7522 0710 + ab6 09 4376 4760 + ab7 19 1337 7140 + n50 50 0000 0000 + fp1 10 0000 0051 + ab9 00 0000 0054 + arthc 00 0000 0000 + 1 + 1 (u) and (acc) float <- (u) float ** (acc) float + 1 u**acc = 10**(log10(u)*acc) + 1 = exp(log10(u)*acc) + 1 + e00lqstdlq1 + ldd e00ab log 10 (u) + fmpacc mult by acc + lddlq1 e00ac 10 ** u + lq1 00 0000 0000 + 1 + 1 (u) float <- log e (u) float + 1 ln(u) = log(u) / log(e) + 1 log10(e)=0.4342944819 + 1 + e00lostdlq1 + ldd e00ab log 10 (u) + fdvloge lq1 div by log(e) const + lq1 00 0000 0000 + loge 43 4294 4850 + 1 + 1 (u) float <- e ** (u) float + 1 expn(u) = e ** u = exp(log10(e)*u) + 1 e=2.71828182846 + 1 + e00lpstdlq1 + fmploge mult by log(e) const + lddlq1 e00ac 10 ** u + lq1 00 0000 0000 + loge 43 4294 4850 + 1 + 1 (u) float <- absolute value (u) float + 1 + e00aynze 8001 exit if zero + nzu ezzty alarm function arg is fix but should be float + stderthx + ram 8003 remove sgn + rau 8002 erthx result in upper and exit + 1 + 1 (u) float <- integer part (u) float + 1 + e00aznze 8001 exit if zero + nzu ezzty alarm function arg is fix but should be float + stderthx + stuarthc save arg + srt 0002 exp in lower + stuartha mant in h + rsm 8002 make exp neg + alon57 + bmiaz4 big num so no fract part to remove + alon01 + slt 0001 + nzuaz5 small num so no int part + srt 0005 set as right + aloaz6 shifts to do + stlarthb + rauartha arthb + n57 57 0000 0000 + n01 01 0000 0000 + az6 srt 0000 + rau 8003 ae0 go to fix to float conversion routine + az5 rau 8002 + rau 8002 erthx return zero + az4 rauarthc erthx return the arg unchanged + 1 + 1 (u) float <- max (float, float, ...) + 1 should have two or more float parameters + 1 + e00bastderthx + stuartha arg is max + ralerthx ba0 + ba0 sloba10 + bmiba9 no more args + ralerthx set arg addr + lddba1 to be read + sdaba1 ba1 + ba1 rau 0000 read arg + stuarthb + fsbartha is grtr than + bmiba2 current result + rauarthb yes store as + stuartha ba2 new result + ba2 ralerthx select next + sloonet arg + stlerthx ba0 + ba9 rauartha erthx result in upper + ba10 00p0000 0000 fist arg addr + 1 + 1 (u) float <- square root (u) float + 1 + e00axnze 8001 exit if zero + nzu ezzty alarm function arg is fix but should be float + bmiax1 alarm sqrt(neg) + stderthx + srt 0002 + nzu ax2 test for zro + slon01 convert fortransit exp (1.0=1e51) to it exp (1.0=1e50) + stlarthb break up exp + ral 8003 and mantissa + slt 0002 calculate + stlartha initial x + aupone ax3 + ax4 rauartha calculate + dvrarthc next x + slo 8001 value + nze ax5 + bmi ax5 test for end + alo 8001 + alo 8001 ax3 + ax3 dvrtwo recycle + stlarthc ax4 + ax5 ralarthb modify + alon49 exponent + srt 0008 + divtwo + alo 8003 + stlarthb test even or + nzu ax6 odd exp + rauarthc exp odd + srt 0001 + mpyax11 mpy by sqrt + srd 0010 ax7 of 10 + ax7 slt 0002 + aloarthb + aloone exp 50 to 51 + rau 8002 erthx go to exit + ax6 ralarthc exp even + srd 0002 ax7 + ax2 rau 8003 erthx result zero + ax1 hlt 0012 8001 alarm sqrt with negative argument + one 00 0000 0001 constants + two 00 0000 0002 + n49 49 0000 0000 + ax11 03 1622 7766 + 1 + 1 (u) float <- cosinus (u) float (arg in radians: cos(pi/2) = 0) + 1 + e00avstderthx av0 + av0 nze av4 cos(0) is one + nzu ezzty alarm function arg is fix but should be float + srt 0002 argument + stuartha alarm if pwr + rsm 8002 overscale + alon01 convert fortransit exp (1.0=1e51) to it exp (1.0=1e50) + alon57 cosx equals + bmiav2 one if pwr + sloav3 underscale + bmi av4 + srt 0004 + aloav5 + stlav6 + rauartha form + mpyav7 av6 fractional + av6 hltav6 av23 and intgrl + av23 stlarthc parts + rau 8003 + mpyn50 form s as + stlarthb one minus + rsmarthc twice abval + sml 8001 of fractnl + alon999 part + rau 8002 + stuartha + mpy 8001 form sine + stuarthc + rauav16 polynomial + mpyarthc approximator + rau 8003 + aupav15 + mpyarthc + rau 8003 + aupav14 + mpyarthc + rau 8003 + aupav13 + mpyarthc + srt 0001 + rau 8003 + auppih equals one + mpyartha + sct 0000 + bovav19 + stlartha + ral 8003 round + srt 0002 and + stlarthc adjust + rsuartha power + srt 0002 + bmi av25 + sup 8003 + alon50 av24 + av24 auparthc + slt 0002 av22 + av22 stuartha determine + rauarthb sign of + nzu av20 result + rslartha av26 + av20 ralartha av26 + av25 sup 8003 + slon50 av24 + av2 rauarthb overscale + ldderthx display + hlt 0013 8001 alarm radian arg too big + av26 rau 8002 + bmiav27 + aupone erthx + av27 supone erthx + av4 ralav21 av26 cosx is one + av19 ral 8002 cosx is zero + slo 8001 av26 + av17 rauav21 av22 cosx is plus + av3 11 0000 0000 or minus 1 + av5 srd 0011 av23 + av7 31 8309 8862 + pih 15 7079 6327 pi / 2 integer + -av13 64 5963 7111 + av14 07 9689 6793 + -av15 00 4673 7656 + av16 00 0151 4842 + av21 10 0000 0050 + n999 99 9999 9999 + n50 50 0000 0000 + one 00 0000 0001 + n01 01 0000 0000 + n57 57 0000 0000 + 1 + 1 (u) float <- sinus (u) float (arg in radians: sin(pi/2) = 1) + 1 + e00awnze 8001 sin(0) is zero + nzu ezzty alarm function arg is fix but should be float + stderthx + stuartha + raufpih + fsbartha av0 sin a = cos(pi/2 - a) + fpih 15 7079 6351 pi / 2 float + 1 + 1 end of fortran package + 1 diff --git a/I650/sw/soapII.dck b/I650/sw/fortransit/soapII.dck similarity index 100% rename from I650/sw/soapII.dck rename to I650/sw/fortransit/soapII.dck diff --git a/I650/sw/it/00_readme.txt b/I650/sw/it/00_readme.txt new file mode 100644 index 00000000..03d67eab --- /dev/null +++ b/I650/sw/it/00_readme.txt @@ -0,0 +1,58 @@ + +Restoration comments May/2018 + +Internal Translator (IT Compiler) + +From Bitsavers Manual CarnegieInternalTranslator.pdf + +The run_it.ini script uses P1 run-time package that +provides floating point +,-,/,* PUNCH and READ, that's +all. In particular, it does not provides power functions +so using power operator in IT program will crash the +object program in run-time. + +To allow the use of IT power operator, replace _P1 +package by _P2, _P3 or _P4 (depending on what is needed) + +In the original listing found in manual, some opcodes has +a different name of the standard SOAP II ones. +They have been changed to regular SOAP names + + Mnemonic in Standard SOAP + original listing equivalent mnemonic + + AAB -> AML + SAB -> SML + NZA -> NZE + RAB -> RAM + RSB -> RSM + RDS -> RD1 + +IT compiler generates also these opcodes in object +program, to be assembled by IT modified y SOAP I. As +SOAP I is not available, the IT compiler has been +modified to produce standard SOAP II opcodes. + +These modifications are done in lines 394-410, file +it_compiler_listing.txt with a comment to signal it. + +Also all the correction to the listing stated in the +manual has been applied. They are stated at the +end of it_compiler_listing.txt file. + +Original listing in manual describes the modifications +to apply to standard SOAP I deck in order to assemble +IT compiler produced SOAP code (soap_patch_listing.txt). + +As SOAP I is not available, an equivalent set of modifications +has been written to be applies to SOAP II in order to +allow to assemble IT produced compiled code (soapII_patch.txt) + +Floating point numbers are encoded as + + 2300000049 = 0.23 + 1000000050 = 1.0 + 1500000052 = 150.0 + + + diff --git a/I650/sw/it_compiler.dck b/I650/sw/it/it_compiler.dck similarity index 100% rename from I650/sw/it_compiler.dck rename to I650/sw/it/it_compiler.dck diff --git a/I650/sw/it_compiler_listing.txt b/I650/sw/it/it_compiler_listing.txt similarity index 98% rename from I650/sw/it_compiler_listing.txt rename to I650/sw/it/it_compiler_listing.txt index daa23bbc..bf1b82a8 100644 --- a/I650/sw/it_compiler_listing.txt +++ b/I650/sw/it/it_compiler_listing.txt @@ -1754,7 +1754,7 @@ A794 LDD NGLFT 1752 69 1144 0947 4 5 5 5 ERRATA BUGFIX 6 5 -1442X STU OPSGN 1334 21 0524 1902 +1442 STU OPSGN 1334 21 0524 1902 1442A STD V1 1384 1902 24 0488 1384 1 5 2 5 CARNEGIE TECH COMPILER IT @@ -1762,26 +1762,26 @@ A794 LDD NGLFT 1752 69 1144 0947 4 5 5 5 ERRATA BUGFIX 6 5 - 341X SUP A0001 OUT IF JAY 1065 11 0383 1137 -A341X STU NEWAB 0887 1137 21 0845 0887 - 603X BS LDD DROPU DCRMNT U 0987 69 0690 0893 -A603X RAL NEWAB 0690 65 0845 0298 -B603X NZE BSA 0640 0298 45 0786 0640 - 606X STL A0001 BSA 1485 20 0383 0786 - 607X BSA RAU N BN1 0786 60 0484 1039 - 650X LDD 1377 LDSR COMPILE 1413 69 1377 1038 - X NEWAB 00 0000 0000 0845 00 0000 0000 + 341 SUP A0001 OUT IF JAY 1065 11 0383 1137 +A341 STU NEWAB 0887 1137 21 0845 0887 + 603 BS LDD DROPU DCRMNT U 0987 69 0690 0893 +A603 RAL NEWAB 0690 65 0845 0298 +B603 NZE BSA 0640 0298 45 0786 0640 + 606 STL A0001 BSA 1485 20 0383 0786 + 607 BSA RAU N BN1 0786 60 0484 1039 + 650 LDD 1377 LDSR COMPILE 1413 69 1377 1038 + NEWAB 00 0000 0000 0845 00 0000 0000 1 5 2 5 CARNEGIE TECH COMPILER IT 3 5 NO DATE 4 5 5 5 ERRATA BUGFIX 6 5 - 793X LDD ML1A TKNZ1 TKNZ1AND ML1 0940 69 1802 1094 - 799X MY1 LDD ML1A TKNZ2 1178 69 1802 1194 -A793X ML1A SLO 8002 1802 16 8002 1852 -B793X STL ABVAL ML1 1852 20 0366 1291 - 804X LDD 1971 GENN RAL AJAY 1139 69 1971 1681 + 793 LDD ML1A TKNZ1 TKNZ1AND ML1 0940 69 1802 1094 + 799 MY1 LDD ML1A TKNZ2 1178 69 1802 1194 +A793 ML1A SLO 8002 1802 16 8002 1852 +B793 STL ABVAL ML1 1852 20 0366 1291 + 804 LDD 1971 GENN RAL AJAY 1139 69 1971 1681 diff --git a/I650/sw/it_example_1_data.txt b/I650/sw/it/it_example_1_data.txt similarity index 100% rename from I650/sw/it_example_1_data.txt rename to I650/sw/it/it_example_1_data.txt diff --git a/I650/sw/it_example_1_out.txt b/I650/sw/it/it_example_1_out.txt similarity index 100% rename from I650/sw/it_example_1_out.txt rename to I650/sw/it/it_example_1_out.txt diff --git a/I650/sw/it_example_1_src.txt b/I650/sw/it/it_example_1_src.txt similarity index 100% rename from I650/sw/it_example_1_src.txt rename to I650/sw/it/it_example_1_src.txt diff --git a/I650/sw/it_example_2_src.txt b/I650/sw/it/it_example_2_src.txt similarity index 92% rename from I650/sw/it_example_2_src.txt rename to I650/sw/it/it_example_2_src.txt index d32e3d21..312d5c4f 100644 --- a/I650/sw/it_example_2_src.txt +++ b/I650/sw/it/it_example_2_src.txt @@ -23,7 +23,11 @@ prime number generator using the sieve of eratosthenes converted to ibm 650 IT compliler - IT system syntax IT notation in manual c-like equivalent syntax +note: ibm 650 terminates card reading on "ff" statement (numbered as 10), so +it is safe to add text and comments below that + + + IT syntax IT notation in manual c-like equivalent syntax 1+ 2k i1k 1k 1k 50k 1: 2,i1,1,1,50, for(num=1,num<=50;num++) 2+ ci1 z 1j 2: ci1 <- 1. prime(num) = 1.0 diff --git a/I650/sw/it_package_p1.dck b/I650/sw/it/it_package_p1.dck similarity index 100% rename from I650/sw/it_package_p1.dck rename to I650/sw/it/it_package_p1.dck diff --git a/I650/sw/it_package_p1_listing.txt b/I650/sw/it/it_package_p1_listing.txt similarity index 100% rename from I650/sw/it_package_p1_listing.txt rename to I650/sw/it/it_package_p1_listing.txt diff --git a/I650/sw/it_package_p2.dck b/I650/sw/it/it_package_p2.dck similarity index 100% rename from I650/sw/it_package_p2.dck rename to I650/sw/it/it_package_p2.dck diff --git a/I650/sw/it_package_p2_listing.txt b/I650/sw/it/it_package_p2_listing.txt similarity index 98% rename from I650/sw/it_package_p2_listing.txt rename to I650/sw/it/it_package_p2_listing.txt index 2af19c87..20f5b637 100644 --- a/I650/sw/it_package_p2_listing.txt +++ b/I650/sw/it/it_package_p2_listing.txt @@ -3,7 +3,7 @@ 5 PLUS THE FOLLOWING 5 ROUTINES 5 E00AK POWER FIX FIX - 5 E00Am POWER FIX FIX REVERSE + 5 E00AM POWER FIX FIX REVERSE 5 E00AL POWER FLOAT FIX 5 E00AN POWER FLOAT FIX REVERSE 1 E00AI STD ARTHX AI1 ADD 1833 24 1786 1789 diff --git a/I650/sw/it_package_p3.dck b/I650/sw/it/it_package_p3.dck similarity index 100% rename from I650/sw/it_package_p3.dck rename to I650/sw/it/it_package_p3.dck diff --git a/I650/sw/it_package_p3_listing.txt b/I650/sw/it/it_package_p3_listing.txt similarity index 98% rename from I650/sw/it_package_p3_listing.txt rename to I650/sw/it/it_package_p3_listing.txt index 4d9600df..502bd36a 100644 --- a/I650/sw/it_package_p3_listing.txt +++ b/I650/sw/it/it_package_p3_listing.txt @@ -3,7 +3,7 @@ 5 PLUS THE FOLLOWING 5 ROUTINES 5 E00AC EXPONENTIAL SUBROUTINE - 5 E00A8 L0G SUBROUTINE + 5 E00AB LOG SUBROUTINE 1 E00AI STD ARTHX AI1 ADD 1833 24 1786 1789 2 AI1 STL ARTHG 1789 20 1794 1799 3 LDD ARTHB 1799 69 1802 1805 diff --git a/I650/sw/it_package_p4.dck b/I650/sw/it/it_package_p4.dck similarity index 100% rename from I650/sw/it_package_p4.dck rename to I650/sw/it/it_package_p4.dck diff --git a/I650/sw/it_package_p4_listing.txt b/I650/sw/it/it_package_p4_listing.txt similarity index 100% rename from I650/sw/it_package_p4_listing.txt rename to I650/sw/it/it_package_p4_listing.txt diff --git a/I650/sw/it_reservation_p1.dck b/I650/sw/it/it_reservation_p1.dck similarity index 100% rename from I650/sw/it_reservation_p1.dck rename to I650/sw/it/it_reservation_p1.dck diff --git a/I650/sw/it_reservation_p1_listing.txt b/I650/sw/it/it_reservation_p1_listing.txt similarity index 100% rename from I650/sw/it_reservation_p1_listing.txt rename to I650/sw/it/it_reservation_p1_listing.txt diff --git a/I650/sw/it_reservation_p2.dck b/I650/sw/it/it_reservation_p2.dck similarity index 100% rename from I650/sw/it_reservation_p2.dck rename to I650/sw/it/it_reservation_p2.dck diff --git a/I650/sw/it_reservation_p2_listing.txt b/I650/sw/it/it_reservation_p2_listing.txt similarity index 100% rename from I650/sw/it_reservation_p2_listing.txt rename to I650/sw/it/it_reservation_p2_listing.txt diff --git a/I650/sw/it_reservation_p3.dck b/I650/sw/it/it_reservation_p3.dck similarity index 100% rename from I650/sw/it_reservation_p3.dck rename to I650/sw/it/it_reservation_p3.dck diff --git a/I650/sw/it_reservation_p3_listing.txt b/I650/sw/it/it_reservation_p3_listing.txt similarity index 100% rename from I650/sw/it_reservation_p3_listing.txt rename to I650/sw/it/it_reservation_p3_listing.txt diff --git a/I650/sw/it_reservation_p4.dck b/I650/sw/it/it_reservation_p4.dck similarity index 100% rename from I650/sw/it_reservation_p4.dck rename to I650/sw/it/it_reservation_p4.dck diff --git a/I650/sw/it_reservation_p4_listing.txt b/I650/sw/it/it_reservation_p4_listing.txt similarity index 100% rename from I650/sw/it_reservation_p4_listing.txt rename to I650/sw/it/it_reservation_p4_listing.txt diff --git a/I650/sw/it_subr_cos_listing.txt b/I650/sw/it/it_subr_cos_listing.txt similarity index 79% rename from I650/sw/it_subr_cos_listing.txt rename to I650/sw/it/it_subr_cos_listing.txt index eb473489..12f289ef 100644 --- a/I650/sw/it_subr_cos_listing.txt +++ b/I650/sw/it/it_subr_cos_listing.txt @@ -1,12 +1,12 @@ 5 SUBROUTINE 21 COSINE - E00AV STO ARTHX BEGIN CISINE + E00AV STD ARTHX BEGIN COSINE SLT 0008 ARGUMENT STU ARTHF ALARM IF PWR RSM 8002 OVERSCALE ALO AV1 COSX EQUALS BMI AV2 ONE IF PWR SLO AV3 UNDERSCALE - BMI AV4 + BMI AV4 SRT 0004 ALO AV5 STL AV6 @@ -22,13 +22,13 @@ ALO AV9 PART RAU 8002 STU ARTHF - MPY 8001 FORM SINE + MPY 8001 FORM SINE STU ARTHG RAU AV16 POLYNOMIAL MPY ARTHG APPROXIMATOR RAU 8003 AUP AV15 - MPY AR7HG + MPY ARTHG RAU 8003 AUP AV14 MPY ARTHG @@ -37,27 +37,27 @@ MPY ARTHG SRT 0001 RAU 8003 - AUP AV12 EQUALS ONE + AUP AV12 EQUALS ONE MPY ARTHF SCT 0000 BOV AV19 - STL AR7HF - RAL 8003 ROUND - SRT 0002 AND - STL ARTHG ADJUST - RSU ARTHF POWER + STL ARTHF + RAL 8003 ROUND + SRT 0002 AND + STL ARTHG ADJUST + RSU ARTHF POWER SRT 0002 - BMI AV25 + BMI AV25 SUP 8003 - ALO AV8 AV24 + ALO AV8 AV24 AV24 AUP ARTHG - SLT 0002 AV22 + SLT 0002 AV22 AV22 STU ARTHF DETERMINE RAU ARTHE SIGN OF - NZU AV20 RESULT - AV20 RSL ARTHF ARTHX - AV25 RAL ARTHF ARTHX - SUP 8003 + NZU AV20 RESULT + RSL ARTHF ARTHX + AV20 RAL ARTHF ARTHX + AV25 SUP 8003 SLO AV8 AV24 AV2 RAL ARTHE OVERSCALE LDD ARTHX 3211 DISPLAY diff --git a/I650/sw/it_subr_sqrt_listing.txt b/I650/sw/it/it_subr_sqrt_listing.txt similarity index 100% rename from I650/sw/it_subr_sqrt_listing.txt rename to I650/sw/it/it_subr_sqrt_listing.txt diff --git a/I650/sw/it/soapII.dck b/I650/sw/it/soapII.dck new file mode 100644 index 00000000..26acff42 --- /dev/null +++ b/I650/sw/it/soapII.dck @@ -0,0 +1,1400 @@ +0?0000800? 0001 1 soap 2 +0?0000800? 0002 1 +0?0000800? 0003 1 symbolic optimal assembly prog +0?0000800? 0004 1 +0?0000800? 0005 1 for the +0?0000800? 0006 1 +0?0000800? 0007 1 ibm 650 +0?0000800? 0008 1 +0?0000800? 0009 1 data processing system +0?0000800? 0010 1 +0?0000800? 0011 regs0000 0399 symbol tab +0?0000800? 0012 rege0400 0599 equiv tabl +0?0000800? 0013 rega0600 0799 avail tabl +0?0000800? 0014 regn0800 0899 num op tab +0?0000800? 0015 blr 1000 1000 entry +0?0000800? 0016 blr 1001 1012 pseudo ent +0?0000800? 0017 blr 1021 1049 reg table +0?0000800? 0018 regc1050 1164 sym op tab +0?0000800? 0019 bla 1098 1099 +0?0000800? 0020 bla 1148 1149 +0?0000800? 0021 blr 1900 1900 manual pat +0?0000800? 0022 synreadc 1950 +0?0000800? 0023 blr 1951 1962 read area +0?0000800? 0024 regt1990 1992 type +0?0000800? 0025 regp1977 1986 punch area +0?0000800? 0026 blr 1998 1999 +0?0000800? 0027 equxxxx1 1961 +0?0000800? 0028 equxxxx2 1962 +0?0000800? 0029 blr 1563 1570 type2 +0?0000800? 0030 bla 1565 1565 +0?0000800? 0031 bla 1569 1569 +0?0000800? 0032 regb0900 0901 sub 2 +0?0000800? 0033 regh0902 0904 type 2 +0?0000800? 0034 regm0905 0907 +0?0000800? 0035 regq0908 0909 +0?0000800? 0036 regr1200 1207 sub 5 +0?0000800? 0037 regu1250 1259 sub 13 +0?0000800? 0038 regv0910 0912 equ syn +0?0000800? 0039 regx0913 0914 type 0 +0?0000800? 0040 regy0915 0916 equ syn +0?0000800? 0041 regz0917 0919 +0?0000800? 0042 regw0920 0922 +0?0000800? 0043 blr 0923 0968 multiple r +0?0000800? 0044 regi1300 1307 sub 13 +0?0000800? 0045 1 +0?0000800? 0046 1 control program +0?0000800? 0047 1 +6I1954195C 0048241000800?691950135C 1000lddreadc sub16 entry +0?0000800? 0049 1 +6I1954195C 0050241950800?701999199H readcrcd 1999 1998 read card +6I1954195C 0051241998800?691951135D 1998ldd 1951 transfer +6I1954195C 0052241354800?241977098? stdp0001 alphabetic +6I1954195C 0053240980800?691952135E ldd 1952 input +6I1954195C 0054241355800?241978098A stdp0002 to +6I1954195C 0055240981800?691953135F ldd 1953 output +6I1954195C 0056241356800?241979098B stdp0003 +6I1954195C 0057240982800?691954135G ldd 1954 +6I1954195C 0058241357800?241980098C stdp0004 +6I1954195C 0059240983800?691955120H ldd 1955 +6I1954195C 0060241208800?241981098D stdp0005 +6I1954195C 0061240984800?691956120I ldd 1956 +6I1954195C 0062241209800?241982098E stdp0006 +6I1954195C 0063240985800?651985098I ralp0009 step +6I1954195C 0064240989800?150992099G alo1ixxx card +6I1954195C 0065240997800?201985098H stlp0009 number +6I1954195C 0066240988800?601960101E rau 1960 store +6I1954195C 0067241015800?300002097A srt 0002 control +6I1954195C 0068240971800?211984098G stup0008 info +6I1954195C 0069240987800?100990099E auptorg +6I1954195C 0070240995800?201986800C stlp0010 8003 transfer +6I1954800? 0071248003800?000000999I 8003nop 0000 9999 to type +0?0000800? 0072 1 +6I1954195C 0073241350800?711977195? punchpchp0001 readc punch read +0?0000800? 0074 1 +6I1954195C 0075241400800?601950140E setccraureadc sub10 sudo exit +0?0000800? 0076 1 +6I1954195C 0077241900800?691950140C 1900lddreadc sub14 manual pat +6I1954195C 0078241990800?690993099F t0001lddx subr3 type 0 +0?0000800? 0079 1 +6I1954195C 0080240913800?691016096I x0001ldd procl 650 +6I1954195C 0081241016800?691019097B ldd procd command or +6I1954195C 0082241019800?691350145C lddpunch proci constants +0?0000800? 0083 1 +6I1954195C 0084240914800?000000800C x0002nop 0000 8003 pseudo op +0?0000800? 0085 1 +6I1954195C 0086241991800?601950140E t0002raureadc sub10 type 1 com +0?0000800? 0087 1 +6I1954195C 0088240993800?000000091C x 00 0000 x0001 +0?0000800? 0089 1 +0?0000800? 0090 1 relocate routine +0?0000800? 0091 1 +0?0000800? 0092 hedt +6I1954195C 0093241992800?691195099F t0003lddq subr3 process op +6I1954195C 0094240909800?000000101C q0002nop 0000 illop illegal op +6I1954195C 0095240908800?651951145E q0001ral 1951 is l fixed +6I1954195C 0096241455800?350002121A slt 0002 +6I1954195C 0097241211800?441165116F nzu rel +6I1954195C 0098241165800?601957126A rau 1957 fixed l +6I1954195C 0099241261800?111014116I sup2000i drum core +6I1954195C 0100241169800?461172097C bmi fc +6I1954195C 0101241172800?108001097I aup 8001 res fixed drum +6I1954195C 0102240973800?651957131A fc ral 1957 setl fixed core +6I1954195C 0103241450800?651961131A sr ralxxxx1 setl set l +6I1954195C 0104241311800?350004117A setl slt 0004 +6I1954195C 0105241171800?691984118G lddp0008 +6I1954195C 0106241187800?221984123G sdap0008 prod +6I1954195C 0107241166800?601957136A rel rau 1957 drum core +6I1954195C 0108241361800?111014121I sup2000i +6I1954195C 0109241219800?461222117C bmi rc +6I1954195C 0110241222800?100975117I aupddiff relocate +6I1954195C 0111241179800?461182118C bmi bl drum addr +6I1954195C 0112241182800?101014097I aup2000i res +6I1954195C 0113240979800?211961121D res stuxxxx1 +6I1954195C 0114241214800?691450150C lddsr sub2r reserve l +6I1954195C 0115241173800?651957141A rc ral 1957 relocate +6I1954195C 0116241411800?151264126I alocdiff core +6I1954195C 0117241269800?161272097G slo9060 +6I1954195C 0118240977800?461180118C bmi bl +6I1954195C 0119241180800?158001131A alo 8001 setl +6I1954195C 0120241183800?601237099A bl rauprod sub12 blank l +0?0000800? 0121 1 +0?0000800? 0122 regj0944 0944 d type 2 +0?0000800? 0123 regg0941 0941 +0?0000800? 0124 1 +6I1954195C 0125241237800?691190119C prod lddproi set d exit +6I1954195C 0126241193800?241196099I stdexitx +6I1954195C 0127240999800?601952140G rau 1952 what is d +6I1954195C 0128241407800?691210121C lddh subr4 +6I1954195C 0129240902800?651958126C h0001ral 1958 relocate +6I1954195C 0130241263800?161014131I slo2000i d or c +6I1954195C 0131241319800?461564156C bmi 1564 1563 +6I1954195C 0132240903800?300008122A h0002srt 0008 c d or f +6I1954195C 0133241221800?100974800C aup1500 8003 +6I1954195C 0134241563800?651264136I 1563ralcdiff cdd c +6I1954195C 0135241564800?650975136I 1564ralddiff cdd d +6I1954195C 0136241566800?651958094D 1566ral 1958 j0001 f +6I1954195C 0137241369800?151958094D cdd alo 1958 j0001 +6I1954195C 0138240904800?000000094C h0003nop 0000 g0003 symbolic +0?0000800? 0139 1 +0?0000800? 0140 regj0960 0960 i +0?0000800? 0141 regf0955 0955 +0?0000800? 0142 1 +6I1954195C 0143241190800?691350155C proi lddpunch set i exit +6I1954195C 0144241553800?241196109I stdexitx +6I1954195C 0145241099800?601953145G rau 1953 what is i +6I1954195C 0146241457800?691260121C lddm subr4 +6I1954195C 0147240905800?651959131C m0001ral 1959 relocate +6I1954195C 0148241313800?161014141I slo2000i d or c +6I1954195C 0149241419800?461568156G bmi 1568 1567 +6I1954195C 0150240906800?300008117E m0002srt 0008 c d or f +6I1954195C 0151241175800?100978800C aup1504 8003 +6I1954195C 0152241567800?651264146I 1567ralcdiff cdi c +6I1954195C 0153241568800?650975146I 1568ralddiff cdi d +6I1954195C 0154241570800?651959096? 1570ral 1959 j0001 f +6I1954195C 0155241469800?151959096? cdi alo 1959 j0001 +6I1954195C 0156240907800?000000095G m0003nop 0000 f0003 symbolic +0?0000800? 0157 1 +6I1954195C 0158241195800?000000090H q 00 0000 q0001 constants +6I1954195C 0159241272800?000000906? 9060 00 0000 9060 +6I1954195C 0160241210800?000000090B h 00 0000 h0001 +6I1954195C 0161240974800?000000150? 1500 00 0000 1500 +6I1954195C 0162241260800?000000090E m 00 0000 m0001 +6I1954195C 0163240978800?000000150D 1504 00 0000 1504 +6I1954195C 0164241961800?010000196A xxxx1 01 0000 xxxx1 eraseable +0?0000800? 0165 hed +0?0000800? 0166 1 +0?0000800? 0167 1 bop routine +0?0000800? 0168 1 +6I1954195C 0169241001800?691404135C 1001ldd sub16 initialize +6I1954195C 0170241404800?601950140E raureadc sub10 punch +0?0000800? 0171 1 +0?0000800? 0172 1 blr routine +0?0000800? 0173 1 +6I1954195C 0174241002800?651959136C 1002ral 1959 blr reserve +6I1954195C 0175241363800?161958141C blr slo 1958 fwa to +6I1954195C 0176241413800?108001127A aup 8001 lwa +6I1954195C 0177241271800?691400150C lddsetcc sub2r +0?0000800? 0178 1 +0?0000800? 0179 1 rbr routine +0?0000800? 0180 1 +6I1954195C 0181241012800?600975122I 1012rauddiff +6I1954195C 0182241229800?151959136C alo 1959 blr +0?0000800? 0183 1 +0?0000800? 0184 1 bla routine +0?0000800? 0185 1 +6I1954195C 0186241003800?691406130I 1003lddh8xxx set drum +6I1954195C 0187241309800?241212121E stddrumt tag to 8 +6I1954195C 0188241215800?651959146C ral 1959 unreserve +6I1954195C 0189241463800?161958151C slo 1958 fwa +6I1954195C 0190241513800?108001132A aup 8001 to +6I1954195C 0191241321800?691400160C lddsetcc sub2u lwa +0?0000800? 0192 1 +0?0000800? 0193 1 reg routine +0?0000800? 0194 1 +0?0000800? 0195 hedr +6I1954195C 0196241004800?651952150G 1004ral 1952 is +6I1954195C 0197241507800?300008122E srt 0008 region +6I1954195C 0198241225800?161178123C slo90xxx character +6I1954195C 0199241233800?460986100B bmi 1002 alphabetic +6I1954195C 0200240986800?151189124C alo29xxx +6I1954195C 0201241243800?461002119G bmi 1002 +6I1954195C 0202241197800?350004155G slt 0004 store +6I1954195C 0203241557800?151310126E alost region +6I1954195C 0204241265800?101958161C aup 1958 origin +6I1954195C 0205241613800?101216800B auph9xxx 8002 +6I1954800? 0206248002800?219999100B 8002stu 9999 1002 +0?0000800? 0207 1 +6I1954195C 0208241310800?211021100B st stu 1021 1002 constants +0?0000800? 0209 hed +0?0000800? 0210 1 +0?0000800? 0211 1 equ req and syn routine +0?0000800? 0212 1 +0?0000800? 0213 hedz +6I1954195C 0214241005800?691406135I 1005lddh8xxx both equ +6I1954195C 0215241006800?691216135I 1006lddh9xxx both syn +6I1954195C 0216241359800?241262131E both stdtag +6I1954195C 0217241315800?601953160G rau 1953 what is i +6I1954195C 0218241607800?691360121C lddz subr4 +6I1954195C 0219240917800?651959091E z0001ral 1959 y0001 absolute +6I1954195C 0220240918800?691371117D z0002lddy subr9 regional +6I1954195C 0221240915800?201519132B y0001stle td +6I1954195C 0222240916800?651986119A y0002ralp0010 bp reg error +6I1954195C 0223240919800?691372127E z0003lddw subr6 symbolic +6I1954195C 0224240920800?651223091E w0001ralequiv y0001 s defined +6I1954195C 0225240921800?651986119A w0002ralp0010 bp s undefind +6I1954195C 0226240922800?651986119A w0003ralp0010 bp s tab full +0?0000800? 0227 1 +6I1954195C 0228241322800?601952165G td rau 1952 head d +6I1954195C 0229241657800?691410166C ldd sub15 and equate +6I1954195C 0230241410800?691713127E lddv subr6 to e +6I1954195C 0231240912800?651986119A v0003ralp0010 bp s tab full +6I1954195C 0232240910800?151519127C v0001aloe sd +6I1954195C 0233240911800?151519127C v0002aloe sd +6I1954195C 0234241273800?690976127I sd lddtt subr7 +0?0000800? 0235 1 +6I1954195C 0236240976800?691262136E tt lddtag test tag +6I1954195C 0237241365800?901400097? bdosetcc +6I1954195C 0238240970800?601519132C raue reserve e +6I1954195C 0239241323800?691400150C lddsetcc sub2r +0?0000800? 0240 1 +6I1954195C 0241241011800?691406140I 1011lddh8xxx req +6I1954195C 0242241409800?241262141E stdtag routine +6I1954195C 0243241415800?651959176C ral 1959 is i +6I1954195C 0244241763800?161014156I slo2000i drum o cor +6I1954195C 0245241569800?461422137C bmid +6I1954195C 0246241373800?151264161I alocdiff cd +6I1954195C 0247241422800?150975161I d aloddiff cd +6I1954195C 0248241619800?151014091E cd alo2000i y0001 +0?0000800? 0249 1 +6I1954195C 0250241360800?000000091G z 00 0000 z0001 constants +6I1954195C 0251241371800?000089091E y 00 0089 y0001 +6I1954195C 0252241372800?000000092? w 00 0000 w0001 +6I1954195C 0253241713800?000000091? v 00 0000 v0001 +6I1954195C 0254241500800?008800000? 88 00 8800 0000 +0?0000800? 0255 1 +6I1954195C 0256241191800?151500150E bp alo88 by pass +6I1954195C 0257241505800?201986135? stlp0010 punch +0?0000800? 0258 1 +6I1954195C 0259241262800?010000126B tag 01 0000 tag eraseable +6I1954195C 0260241519800?010000151I e 01 0000 e +0?0000800? 0261 hed +0?0000800? 0262 1 +0?0000800? 0263 1 alf routine +0?0000800? 0264 1 +6I1954195C 0265241007800?691460096I 1007ldd procl proces loc +6I1954195C 0266241460800?691952155E ldd 1952 +6I1954195C 0267241555800?241983118F stdp0007 +6I1954195C 0268241186800?651953170G ral 1953 replace +6I1954195C 0269241707800?451350146A nzepunch blank i +6I1954195C 0270241461800?691314101G lddsoap2 by +6I1954195C 0271241017800?241979135? stdp0003 punch soap2 +6I1954195C 0272241314800?827661779B soap2alfsoap2 soap2 constant +0?0000800? 0273 1 +0?0000800? 0274 1 pat routine +0?0000800? 0275 1 +6I1954195C 0276241008800?601511140E 1008rau sub10 +6I1954195C 0277241511800?691950140C lddreadc sub14 +0?0000800? 0278 1 +0?0000800? 0279 1 hed routine +0?0000800? 0280 1 +6I1954195C 0281241009800?651952175G 1009ral 1952 store +6I1954195C 0282241757800?300008132E srt 0008 heading +6I1954195C 0283241325800?201329140? stl0000h setcc character +0?0000800? 0284 1 +0?0000800? 0285 1 rel routine +0?0000800? 0286 1 +0?0000800? 0287 hedm +6I1954195C 0288241010800?651952180G 1010ral 1952 set +6I1954195C 0289241807800?451510156A nze sdd drum +6I1954195C 0290241510800?651958156A ral 1958 sdd and +6I1954195C 0291241561800?200975122H sdd stlddiff core +6I1954195C 0292241228800?651953185G ral 1953 deltas +6I1954195C 0293241857800?451560161A nze scd +6I1954195C 0294241560800?651959161A ral 1959 scd +6I1954195C 0295241611800?201264140? scd stlcdiff setcc +0?0000800? 0296 1 +6I1954195C 0297240975800?010000097E ddiff 01 0000 ddiff eraseable +6I1954195C 0298241264800?010000126D cdiff 01 0000 cdiff +0?0000800? 0299 hed +0?0000800? 0300 1 +0?0000800? 0301 1 load availablity table +0?0000800? 0302 1 +0?0000800? 0303 hedl +6I1954195C 0304241999800?651951160E 1999ral 1951 calc +6I1954195C 0305241605800?300004146E srt 0004 loc +6I1954195C 0306241465800?350004137E slt 0004 w2 +6I1954195C 0307241375800?158002128C alo 8002 +6I1954195C 0308241283800?158002124A alo 8002 +6I1954195C 0309241241800?150994114I aloc1 +6I1954195C 0310241149800?101352800C aupc2 8003 +6I1954800? 0311248003800?699995800B 8003ldd 9995 8002 load +6I1954800? 0312248002800?249994124G 8002std 9994 tup table +6I1954195C 0313241247800?111550165E tup suptw +6I1954195C 0314241655800?441459195? nzu readc +6I1954195C 0315241459800?101312116G auptwp2 +6I1954195C 0316241167800?151020800C alo1dxxx 8003 +0?0000800? 0317 1 +6I1954195C 0318240994800?240600124G c1 stda0001 tup constants +6I1954195C 0319241352800?691952800B c2 ldd 1952 8002 +6I1954195C 0320241550800?691958800B tw ldd 1958 8002 +6I1954195C 0321241312800?691960800B twp2 ldd 1960 8002 +0?0000800? 0322 hed +0?0000800? 0323 1 optimizing table +0?0000800? 0324 1 +6I1954195C 0325240800800?000404099H n0001 00 0404 0998 nop +6I1954195C 0326240801800?000404099H n0002 00 0404 0998 hlt +6I1954195C 0327240802800?332322099I n0003 33 2322 0999 ufa +6I1954195C 0328240803800?000505099H n0004 00 0505 0998 rtc +6I1954195C 0329240804800?000505099H n0005 00 0505 0998 rtn +6I1954195C 0330240805800?000505099H n0006 00 0505 0998 rta +6I1954195C 0331240806800?000505099H n0007 00 0505 0998 wtn +6I1954195C 0332240807800?000505099H n0008 00 0505 0998 wta +6I1954195C 0333240808800?331212099I n0009 33 1212 0999 lib +6I1954195C 0334240809800?330202099I n0010 33 0202 0999 ldi +6I1954195C 0335240810800?330504099I n0011 33 0504 0999 aup +6I1954195C 0336240811800?330504099I n0012 33 0504 0999 sup +6I1954195C 0337240812800?999999999I n0013 99 9999 9999 not used +6I1954195C 0338240813800?999999999I n0014 99 9999 9999 not used +6I1954195C 0339240814800?331110099I n0015 33 1110 0999 div +6I1954195C 0340240815800?330504099I n0016 33 0504 0999 alo +6I1954195C 0341240816800?330504099I n0017 33 0504 0999 slo +6I1954195C 0342240817800?330504099I n0018 33 0504 0999 aml +6I1954195C 0343240818800?330504099I n0019 33 0504 0999 sml +6I1954195C 0344240819800?332120099I n0020 33 2120 0999 mpy +6I1954195C 0345240820800?540303099I n0021 54 0303 0999 stl +6I1954195C 0346240821800?450303099I n0022 45 0303 0999 stu +6I1954195C 0347240822800?340303099I n0023 34 0303 0999 sda +6I1954195C 0348240823800?340303099I n0024 34 0303 0999 sia +6I1954195C 0349240824800?330303099I n0025 33 0303 0999 std +6I1954195C 0350240825800?440505099H n0026 44 0505 0998 nts +6I1954195C 0351240826800?000505099H n0027 00 0505 0998 bin +6I1954195C 0352240827800?000505099H n0028 00 0505 0998 set +6I1954195C 0353240828800?331212099I n0029 33 1212 0999 sib +6I1954195C 0354240829800?330202099I n0030 33 0202 0999 sti +6I1954195C 0355240830800?000000098H n0031 00 0000 0988 srt +6I1954195C 0356240831800?000000088H n0032 00 0000 0888 srd +6I1954195C 0357240832800?332726099I n0033 33 2726 0999 fad +6I1954195C 0358240833800?332726099I n0034 33 2726 0999 fsb +6I1954195C 0359240834800?330000099I n0035 33 0000 0999 fdv +6I1954195C 0360240835800?000000098H n0036 00 0000 0988 slt +6I1954195C 0361240836800?000000098H n0037 00 0000 0988 sct +6I1954195C 0362240837800?332726099I n0038 33 2726 0999 fam +6I1954195C 0363240838800?332726099I n0039 33 2726 0999 fsm +6I1954195C 0364240839800?330000099I n0040 33 0000 0999 fmp +6I1954195C 0365240840800?330404099H n0041 33 0404 0998 nza +6I1954195C 0366240841800?330404099H n0042 33 0404 0998 bmz +6I1954195C 0367240842800?330404099H n0043 33 0404 0998 nzb +6I1954195C 0368240843800?330404099H n0044 33 0404 0998 bmb +6I1954195C 0369240844800?340405099H n0045 34 0405 0998 nzu +6I1954195C 0370240845800?430504099H n0046 43 0504 0998 nze +6I1954195C 0371240846800?330404099H n0047 33 0404 0998 bmi +6I1954195C 0372240847800?330505099H n0048 33 0505 0998 bov +6I1954195C 0373240848800?330404099H n0049 33 0404 0998 nzc +6I1954195C 0374240849800?330404099H n0050 33 0404 0998 bmc +6I1954195C 0375240850800?000000089H n0051 00 0000 0898 axa +6I1954195C 0376240851800?000000089H n0052 00 0000 0898 sxa +6I1954195C 0377240852800?000000089H n0053 00 0000 0898 axb +6I1954195C 0378240853800?000000089H n0054 00 0000 0898 sxb +6I1954195C 0379240854800?440505099H n0055 44 0505 0998 nef +6I1954195C 0380240855800?000505099H n0056 00 0505 0998 rwd +6I1954195C 0381240856800?000505099H n0057 00 0505 0998 wtm +6I1954195C 0382240857800?000505099H n0058 00 0505 0998 bst +6I1954195C 0383240858800?000000089H n0059 00 0000 0898 axc +6I1954195C 0384240859800?000000089H n0060 00 0000 0898 sxc +6I1954195C 0385240860800?330504099I n0061 33 0504 0999 rau +6I1954195C 0386240861800?330504099I n0062 33 0504 0999 rsu +6I1954195C 0387240862800?999999999I n0063 99 9999 9999 not used +6I1954195C 0388240863800?999999999I n0064 99 9999 9999 not used +6I1954195C 0389240864800?331110099I n0065 33 1110 0999 dvr +6I1954195C 0390240865800?330504099I n0066 33 0504 0999 ral +6I1954195C 0391240866800?330504099I n0067 33 0504 0999 rsl +6I1954195C 0392240867800?330504099I n0068 33 0504 0999 ram +6I1954195C 0393240868800?330504099I n0069 33 0504 0999 rsm +6I1954195C 0394240869800?330303099I n0070 33 0303 0999 ldd +6I1954195C 0395240870800?000000099I n0071 00 0000 0999 rd1 +6I1954195C 0396240871800?000000099I n0072 00 0000 0999 wr1 +6I1954195C 0397240872800?000000099I n0073 00 0000 0999 rc1 +6I1954195C 0398240873800?000000099I n0074 00 0000 0999 rd2 +6I1954195C 0399240874800?000000099I n0075 00 0000 0999 wr2 +6I1954195C 0400240875800?000000099I n0076 00 0000 0999 rc2 +6I1954195C 0401240876800?000000099I n0077 00 0000 0999 rd3 +6I1954195C 0402240877800?000000099I n0078 00 0000 0999 wr3 +6I1954195C 0403240878800?000000099I n0079 00 0000 0999 rc3 +6I1954195C 0404240879800?000505099I n0080 00 0505 0999 rpy +6I1954195C 0405240880800?000000089H n0081 00 0000 0898 raa +6I1954195C 0406240881800?000000089H n0082 00 0000 0898 rsa +6I1954195C 0407240882800?000000089H n0083 00 0000 0898 rab +6I1954195C 0408240883800?000000089H n0084 00 0000 0898 rsb +6I1954195C 0409240884800?330506099I n0085 33 0506 0999 tlu +6I1954195C 0410240885800?000606099H n0086 00 0606 0998 sds +6I1954195C 0411240886800?000606099H n0087 00 0606 0998 rds +6I1954195C 0412240887800?000606099H n0088 00 0606 0998 wds +6I1954195C 0413240888800?000000089H n0089 00 0000 0898 rac +6I1954195C 0414240889800?000000089H n0090 00 0000 0898 rsc +6I1954195C 0415240890800?440505099H n0091 44 0505 0998 bdo +6I1954195C 0416240891800?330505099H n0092 33 0505 0998 bd1 +6I1954195C 0417240892800?330505099H n0093 33 0505 0998 bd2 +6I1954195C 0418240893800?330505099H n0094 33 0505 0998 bd3 +6I1954195C 0419240894800?330505099H n0095 33 0505 0998 bd4 +6I1954195C 0420240895800?330505099H n0096 33 0505 0998 bd5 +6I1954195C 0421240896800?330505099H n0097 33 0505 0998 bd6 +6I1954195C 0422240897800?330505099H n0098 33 0505 0998 bd7 +6I1954195C 0423240898800?330505099H n0099 33 0505 0998 bd8 +6I1954195C 0424240899800?440505099H n0100 44 0505 0998 bd9 +0?0000800? 0425 1 +0?0000800? 0426 1 symbolic op table +0?0000800? 0427 1 +6I1954195C 0428241050800?617366100G c0001 61 7366 1007 alf +6I1954195C 0429241051800?617376001E c0002 61 7376 0015 alo +6I1954195C 0430241052800?617473001G c0003 61 7473 0017 aml +6I1954195C 0431241053800?618477001? c0004 61 8477 0010 aup +6I1954195C 0432241054800?618761005? c0005 61 8761 0050 axa +6I1954195C 0433241055800?618762005B c0006 61 8762 0052 axb +6I1954195C 0434241056800?618763005H c0007 61 8763 0058 axc +6I1954195C 0435241057800?626476009? c0008 62 6476 0090 bdo +6I1954195C 0436241058800?626491009A c0009 62 6491 0091 bd1 +6I1954195C 0437241059800?626492009B c0010 62 6492 0092 bd2 +6I1954195C 0438241060800?626493009C c0011 62 6493 0093 bd3 +6I1954195C 0439241061800?626494009D c0012 62 6494 0094 bd4 +6I1954195C 0440241062800?626495009E c0013 62 6495 0095 bd5 +6I1954195C 0441241063800?626496009F c0014 62 6496 0096 bd6 +6I1954195C 0442241064800?626497009G c0015 62 6497 0097 bd7 +6I1954195C 0443241065800?626498009H c0016 62 6498 0098 bd8 +6I1954195C 0444241066800?626499009I c0017 62 6499 0099 bd9 +6I1954195C 0445241067800?626975002F c0018 62 6975 0026 bin +6I1954195C 0446241068800?627361100C c0019 62 7361 1003 bla +6I1954195C 0447241069800?627379100B c0020 62 7379 1002 blr +6I1954195C 0448241070800?627461004A c0021 62 7461 0041 bma +6I1954195C 0449241071800?627462004C c0022 62 7462 0043 bmb +6I1954195C 0450241072800?627463004I c0023 62 7463 0049 bmc +6I1954195C 0451241073800?627469004F c0024 62 7469 0046 bmi +6I1954195C 0452241074800?627677100A c0025 62 7677 1001 bop +6I1954195C 0453241075800?627685004G c0026 62 7685 0047 bov +6I1954195C 0454241076800?628283005G c0027 62 8283 0057 bst +6I1954195C 0455241077800?646985001D c0028 64 6985 0014 div +6I1954195C 0456241078800?648579006D c0029 64 8579 0064 dvr +6I1954195C 0457241079800?657884100E c0030 65 7884 1005 equ +6I1954195C 0458241080800?666164003B c0031 66 6164 0032 fad +6I1954195C 0459241081800?666174003G c0032 66 6174 0037 fam +6I1954195C 0460241082800?666485003D c0033 66 6485 0034 fdv +6I1954195C 0461241083800?667477003I c0034 66 7477 0039 fmp +6I1954195C 0462241084800?668262003C c0035 66 8262 0033 fsb +6I1954195C 0463241085800?668274003H c0036 66 8274 0038 fsm +6I1954195C 0464241086800?686564100I c0037 68 6564 1009 hed +6I1954195C 0465241087800?687383000A c0038 68 7383 0001 hlt +6I1954195C 0466241088800?736464006I c0039 73 6464 0069 ldd +6I1954195C 0467241089800?736469000I c0040 73 6469 0009 ldi +6I1954195C 0468241090800?736962000H c0041 73 6962 0008 lib +6I1954195C 0469241091800?747788001I c0042 74 7788 0019 mpy +6I1954195C 0470241092800?756566005D c0043 75 6566 0054 nef +6I1954195C 0471241093800?757677000? c0044 75 7677 0000 nop +6I1954195C 0472241094800?758382002E c0045 75 8382 0025 nts +6I1954195C 0473241095800?758961004? c0046 75 8961 0040 nza +6I1954195C 0474241096800?758962004B c0047 75 8962 0042 nzb +6I1954195C 0475241097800?758963004H c0048 75 8963 0048 nzc +6I1954195C 0476241100800?758965004E c0051 75 8965 0045 nze +6I1954195C 0477241101800?758984004D c0052 75 8984 0044 nzu +6I1954195C 0478241102800?776183100H c0053 77 6183 1008 pat +6I1954195C 0479241103800?776368007A c0054 77 6368 0071 pch +6I1954195C 0480241104800?796161008? c0055 79 6161 0080 raa +6I1954195C 0481241105800?796162008B c0056 79 6162 0082 rab +6I1954195C 0482241106800?796163008H c0057 79 6163 0088 rac +6I1954195C 0483241107800?796173006E c0058 79 6173 0065 ral +6I1954195C 0484241108800?796174006G c0059 79 6174 0067 ram +6I1954195C 0485241109800?796184006? c0060 79 6184 0060 rau +6I1954195C 0486241110800?796279101B c0061 79 6279 1012 rbr +6I1954195C 0487241111800?796364007? c0062 79 6364 0070 rcd +6I1954195C 0488241112800?796391007B c0063 79 6391 0072 rc1 +6I1954195C 0489241113800?796392007E c0064 79 6392 0075 rc2 +6I1954195C 0490241114800?796393007H c0065 79 6393 0078 rc3 +6I1954195C 0491241115800?796482008F c0066 79 6482 0086 rds +6I1954195C 0492241116800?796491007? c0067 79 6491 0070 rd1 +6I1954195C 0493241117800?796492007C c0068 79 6492 0073 rd2 +6I1954195C 0494241118800?796493007F c0069 79 6493 0076 rd3 +6I1954195C 0495241119800?796567100D c0070 79 6567 1004 reg +6I1954195C 0496241120800?796573101? c0071 79 6573 1010 rel +6I1954195C 0497241121800?796578101A c0072 79 6578 1011 req +6I1954195C 0498241122800?797788007I c0073 79 7788 0079 rpy +6I1954195C 0499241123800?798261008A c0074 79 8261 0081 rsa +6I1954195C 0500241124800?798262008C c0075 79 8262 0083 rsb +6I1954195C 0501241125800?798263008I c0076 79 8263 0089 rsc +6I1954195C 0502241126800?798273006F c0077 79 8273 0066 rsl +6I1954195C 0503241127800?798274006H c0078 79 8274 0068 rsm +6I1954195C 0504241128800?798284006A c0079 79 8284 0061 rsu +6I1954195C 0505241129800?798361000E c0080 79 8361 0005 rta +6I1954195C 0506241130800?798363000C c0081 79 8363 0003 rtc +6I1954195C 0507241131800?798375000D c0082 79 8375 0004 rtn +6I1954195C 0508241132800?798664005E c0083 79 8664 0055 rwd +6I1954195C 0509241133800?826383003F c0084 82 6383 0036 sct +6I1954195C 0510241134800?826461002B c0085 82 6461 0022 sda +6I1954195C 0511241135800?826482008E c0086 82 6482 0085 sds +6I1954195C 0512241136800?826583002G c0087 82 6583 0027 set +6I1954195C 0513241137800?826961002C c0088 82 6961 0023 sia +6I1954195C 0514241138800?826962002H c0089 82 6962 0028 sib +6I1954195C 0515241139800?827376001F c0090 82 7376 0016 slo +6I1954195C 0516241140800?827383003E c0091 82 7383 0035 slt +6I1954195C 0517241141800?827473001H c0092 82 7473 0018 sml +6I1954195C 0518241142800?827964003A c0093 82 7964 0031 srd +6I1954195C 0519241143800?827983003? c0094 82 7983 0030 srt +6I1954195C 0520241144800?828364002D c0095 82 8364 0024 std +6I1954195C 0521241145800?828369002I c0096 82 8369 0029 sti +6I1954195C 0522241146800?828373002? c0097 82 8373 0020 stl +6I1954195C 0523241147800?828384002A c0098 82 8384 0021 stu +6I1954195C 0524241150800?828477001A c0101 82 8477 0011 sup +6I1954195C 0525241151800?828761005A c0102 82 8761 0051 sxa +6I1954195C 0526241152800?828762005C c0103 82 8762 0053 sxb +6I1954195C 0527241153800?828763005I c0104 82 8763 0059 sxc +6I1954195C 0528241154800?828875100F c0105 82 8875 1006 syn +6I1954195C 0529241155800?837384008D c0106 83 7384 0084 tlu +6I1954195C 0530241156800?846661000B c0107 84 6661 0002 ufa +6I1954195C 0531241157800?866482008G c0108 86 6482 0087 wds +6I1954195C 0532241158800?867991007A c0109 86 7991 0071 wr1 +6I1954195C 0533241159800?867992007D c0110 86 7992 0074 wr2 +6I1954195C 0534241160800?867993007G c0111 86 7993 0077 wr3 +6I1954195C 0535241161800?868361000G c0112 86 8361 0007 wta +6I1954195C 0536241162800?868374005F c0113 86 8374 0056 wtm +6I1954195C 0537241163800?868375000F c0114 86 8375 0006 wtn +6I1954195C 0538241164800?999999000A c0115 99 9999 0001 table end +0?0000800? 0539 1 +0?0000800? 0540 1 sub 1 store k in fwa to lwa +0?0000800? 0541 1 +0?0000800? 0542 hed1 +6I1954195C 0543241600800?241196119I subr1stdexitx store exit +6I1954195C 0544241199800?211961136D stuxxxx1 store k +6I1954195C 0545241364800?691217117? lddfwa set +6I1954195C 0546241170800?221217122? sdafwa fwa +6I1954195C 0547241220800?350004118A slt 0004 lwa +6I1954195C 0548241181800?221962151E sdaxxxx2 addresses +6I1954195C 0549241515800?601217142A raufwa +6I1954195C 0550241421800?151961800C aloxxxx1 8003 +6I1954800? 0551248003800?209999140B 8003stl 9999 next store k +6I1954195C 0552241402800?111962126G next supxxxx2 end of +6I1954195C 0553241267800?441471119F nzu exitx loop test +6I1954195C 0554241471800?108001137I aup 8001 +6I1954195C 0555241379800?101020800C aup1dxxx 8003 step +0?0000800? 0556 1 +6I1954195C 0557241217800?209998140B fwa stl 9998 next constants +6I1954195C 0558241962800?010000196B xxxx2 01 0000 xxxx2 eraseable +0?0000800? 0559 hed +0?0000800? 0560 1 +0?0000800? 0561 1 sub 2 reserve unreserve +0?0000800? 0562 1 +0?0000800? 0563 hed2 +6I1954195C 0564241503800?241813131F sub2rstdexity reserve +6I1954195C 0565241316800?691769147B lddz ru entry +6I1954195C 0566241603800?241813136F sub2ustdexity unreserve +6I1954195C 0567241366800?691565147B ldd1i ru entry +6I1954195C 0568241472800?241246129I ru stdw set w +6I1954195C 0569241299800?201653155F stln store n +6I1954195C 0570241556800?168001191C slo 8001 calc ao +6I1954195C 0571241913800?108003157A aup 8003 and po +6I1954195C 0572241571800?300003147I srt 0003 +6I1954195C 0573241479800?211284128G stux +6I1954195C 0574241287800?118001124E sup 8001 +6I1954195C 0575241245800?350001145A slt 0001 +6I1954195C 0576241451800?211606160I stup +6I1954195C 0577241609800?118001136G sup 8001 +6I1954195C 0578241367800?350002147C slt 0002 +6I1954195C 0579241473800?108003128A aup 8003 +6I1954195C 0580241281800?101284123I aupx +6I1954195C 0581241239800?151606171A alop +6I1954195C 0582241711800?350004162A slt 0004 +6I1954195C 0583241621800?151506176A aloc1 +6I1954195C 0584241761800?200901155D stlb0002 +6I1954195C 0585241554800?691188129A lddc2 +6I1954195C 0586241291800?221231133D sdaspr +6I1954195C 0587241334800?101337142C aupc3 su +6I1954195C 0588241423800?211401160D su stusa +6I1954195C 0589241604800?101558800C aupc4 8003 +6I1954800? 0590248003800?659992090A 8003ral 9992 b0002 +6I1954195C 0591240901800?350009152A b0002slt 0009 xx +6I1954195C 0592241521800?211176142I xx stuuh +6I1954195C 0593241429800?350001118E slt 0001 +6I1954195C 0594241185800?658002129C ral 8002 +6I1954195C 0595241293800?101246135A aupw +6I1954195C 0596241351800?300001190G srt 0001 +6I1954195C 0597241907800?101176123A aupuh spr +6I1954195C 0598241231800?300009140A spr srt 0009 sa +6I1954195C 0599241401800?209983090? sa stl 9983 b0001 +6I1954195C 0600240900800?651653130H b0001raln is n zero +6I1954195C 0601241308800?451362181C nze exity +6I1954195C 0602241362800?161565166I slo1i reduce n +6I1954195C 0603241669800?201653145F stln by 1 +6I1954195C 0604241456800?601401170E rausa is ai +6I1954195C 0605241705800?111358186C supa197 in last +6I1954195C 0606241863800?461266131G bmi tp block of +6I1954195C 0607241266800?101719142C aupa201 su 4 +0?0000800? 0608 1 +6I1954195C 0609241317800?651231123E tp ralspr is p 9 +6I1954195C 0610241235800?161188134C sloc2 +6I1954195C 0611241343800?451296129G nze zp +6I1954195C 0612241296800?151249170C aloc5 step p +6I1954195C 0613241703800?691506150I lddc1 +6I1954195C 0614241509800?220901145D sdab0002 +6I1954195C 0615241454800?201231118D stlspr +6I1954195C 0616241184800?601401175E rausa reduce ai +6I1954195C 0617241755800?111408142C supc6 su by 196 +0?0000800? 0618 1 +6I1954195C 0619241297800?691506155I zp lddc1 set p +6I1954195C 0620241559800?240901150D stdb0002 to zero +6I1954195C 0621241504800?691458166A lddc7 +6I1954195C 0622241661800?241231123D stdspr +6I1954195C 0623241234800?601401180E rausa reduce ai +6I1954195C 0624241805800?111508142C supc8 su by 195 +0?0000800? 0625 1 +6I1954195C 0626241506800?350000152A c1 slt 0000 xx constants +6I1954195C 0627241188800?300009140A c2 srt 0009 sa +6I1954195C 0628241337800?200600090? c3 stla0001 b0001 +6I1954195C 0629241558800?450000000A c4 45 0000 0001 +6I1954195C 0630241565800?000000000A 1i 00 0000 0001 +6I1954195C 0631241358800?200796090? a197 stla0197 b0001 +6I1954195C 0632241719800?200800090? a201 stla0201 b0001 +6I1954195C 0633241249800?300010140A c5 srt 0010 sa +6I1954195C 0634241408800?000196000? c6 00 0196 0000 +6I1954195C 0635241458800?300000140A c7 srt 0000 sa +6I1954195C 0636241508800?000195000? c8 00 0195 0000 +6I1954195C 0637241769800?000000000? z 00 0000 0000 +6I1954195C 0638241246800?010000124F w 01 0000 w eraseable +6I1954195C 0639241653800?010000165C n 01 0000 n +6I1954195C 0640240901800?010000090A b0002 01 0000 b0002 +6I1954195C 0641241231800?010000123A spr 01 0000 spr +6I1954195C 0642241401800?010000140A sa 01 0000 sa +6I1954195C 0643241176800?010000117F uh 01 0000 uh +6I1954195C 0644241284800?010000128D x 01 0000 x +0?0000800? 0645 hed +0?0000800? 0646 1 +0?0000800? 0647 1 sub 3 process op code +0?0000800? 0648 1 +0?0000800? 0649 hed3 +6I1954195C 0650240996800?241196134I subr3stdexitx store exit +6I1954195C 0651241349800?651954165I ral 1954 +6I1954195C 0652241659800?300004181I srt 0004 is op +6I1954195C 0653241819800?451522101C nze illop blank +6I1954195C 0654241522800?350006138G slt 0006 is op +6I1954195C 0655241387800?441341119B nzu num numeric +6I1954195C 0656241341800?300002134G srt 0002 +6I1954195C 0657241347800?201961141D stlxxxx1 search +6I1954195C 0658241414800?168001167A slo 8001 symbolic +6I1954195C 0659241671800?841050185E tluc0001 op table +6I1954195C 0660241855800?151608800B alo1 8002 +6I1954800? 0661248002800?659997150A 8002ral 9997 next is +6I1954195C 0662241501800?161961161E next sloxxxx1 sym op +6I1954195C 0663241615800?350006152I slt 0006 legal +6I1954195C 0664241529800?441013138D nzuillop +6I1954195C 0665241384800?350001139A slt 0001 test for +6I1954195C 0666241391800?441295134F nzupseu pseudo op +6I1954195C 0667241346800?350001175C slt 0001 sno store num +6I1954195C 0668241753800?201983123F sno stlp0007 650 op +6I1954195C 0669241236800?300004139G srt 0004 get optim +6I1954195C 0670241397800?151650800B alo3 8002 constants +6I1954800? 0671248002800?699996139I 8002ldd 9996 nex +6I1954195C 0672241399800?241452119F nex stdoptim exitx +0?0000800? 0673 1 +6I1954195C 0674241192800?161345144I num slo4 form +6I1954195C 0675241449800?350002190E slt 0002 numeric +6I1954195C 0676241905800?168002196C slo 8002 op +6I1954195C 0677241963800?300001186I srt 0001 code +6I1954195C 0678241869800?158001175C alo 8001 sno +0?0000800? 0679 1 +6I1954195C 0680241013800?651986144A illopralp0010 illegal op +6I1954195C 0681241441800?151194149I alo5 set 8 +6I1954195C 0682241499800?201986128I stlp0010 for blank +6I1954195C 0683241289800?691242139I ldd6 nex op +0?0000800? 0684 1 +6I1954195C 0685241295800?350003180C pseu slt 0003 pseudo +6I1954195C 0686241803800?151196155A aloexitx op +6I1954195C 0687241551800?150992800B alo1ixxx 8002 +0?0000800? 0688 1 +6I1954195C 0689241608800?650000150A 1 ral 0000 next constants +6I1954195C 0690241700800?100000000? 2 10 0000 0000 +6I1954195C 0691241650800?690800139I 3 lddn0001 nex +6I1954195C 0692241345800?909000000? 4 90 9000 0000 +6I1954195C 0693241194800?000000000H 5 00 0000 0008 +6I1954195C 0694241242800?550505099I 6 55 0505 0999 +0?0000800? 0695 hed +0?0000800? 0696 1 +0?0000800? 0697 1 sub 4 what is address +0?0000800? 0698 1 +0?0000800? 0699 hed4 +6I1954195C 0700241213800?241416191I subr4stdexitz store exit +6I1954195C 0701241919800?211961146D stuxxxx1 store addr +6I1954195C 0702241464800?300008133C srt 0008 is c5 +6I1954195C 0703241333800?441437141F nzu exitz blank +6I1954195C 0704241437800?211962166E stuxxxx2 save c5 +6I1954195C 0705241665800?608002152C rau 8002 are low 4 +6I1954195C 0706241523800?101178138C aup90xxx characters +6I1954195C 0707241383800?471286128F bovloop loop numeric +6I1954195C 0708241286800?101339139C loop auph1 +6I1954195C 0709241393800?471396099H bov sym +6I1954195C 0710241396800?350002185C slt 0002 +6I1954195C 0711241853800?441286165H nzuloop +6I1954195C 0712241658800?651962141G ralxxxx2 low 4 num +6I1954195C 0713241417800?161178143C slo90xxx is c5 +6I1954195C 0714241433800?461336099H bmi sym alphabetic +6I1954195C 0715241336800?151189144C alo29xxx +6I1954195C 0716241443800?460998144G bmisym +6I1954195C 0717241447800?650992149G ral1ixxx regional +6I1954195C 0718241497800?101961171E aupxxxx1 aex +6I1954195C 0719241715800?151416172A aex aloexitz +6I1954195C 0720241721800?168002800A slo 8002 8001 +6I1954195C 0721240998800?601961176E sym rauxxxx1 hed symbol +6I1954195C 0722241765800?691018166C ldd sub15 +6I1954195C 0723241018800?151771142E alo2ixxx step exit +6I1954195C 0724241425800?211230171E stuhsymb aex +6I1954195C 0725241339800?100000000? h1 10 0000 0000 +6I1954195C 0726241230800?010000123? hsymb 01 0000 hsymb eraseable +0?0000800? 0727 hed +0?0000800? 0728 1 +0?0000800? 0729 1 sub 5 test absolute address +0?0000800? 0730 1 +0?0000800? 0731 hed5 +6I1954195C 0732241750800?241416196I subr5stdexitz store exit +6I1954195C 0733241969800?201961151D stlxxxx1 store a +6I1954195C 0734241514800?350004147E slt 0004 +6I1954195C 0735241475800?168002148C slo 8002 +6I1954195C 0736241483800?841200165F tlur0001 tlu +6I1954195C 0737241656800?151709800B aloget 8002 range +6I1954800? 0738248002800?609972117G 8002rau 9972 x table +6I1954195C 0739241177800?350006149A x slt 0006 +6I1954195C 0740241491800?300006170F srt 0006 +6I1954195C 0741241706800?101416182A aupexitz +6I1954195C 0742241821800?151961181E aloxxxx1 +6I1954195C 0743241815800?118003800A sup 8003 8001 +6I1954195C 0744241709800?600000117G get rau 0000 x +6I1954195C 0745241200800?001999000? r0001 00 1999 0000 range +6I1954195C 0746241201800?007999000C r0002 00 7999 0003 table +6I1954195C 0747241202800?008003000A r0003 00 8003 0001 +6I1954195C 0748241203800?008004000C r0004 00 8004 0003 +6I1954195C 0749241204800?008007000A r0005 00 8007 0001 +6I1954195C 0750241205800?008999000C r0006 00 8999 0003 +6I1954195C 0751241206800?009059000B r0007 00 9059 0002 +6I1954195C 0752241207800?999999000C r0008 99 9999 0003 +0?0000800? 0753 hed +0?0000800? 0754 1 +0?0000800? 0755 1 sub 6 symbol test routine +0?0000800? 0756 1 +0?0000800? 0757 hed6 +6I1954195C 0758241275800?241416132? subr6stdexitz store exit +6I1954195C 0759241320800?211601165D stus store symb +6I1954195C 0760241654800?691758186A lddswof set switch +6I1954195C 0761241861800?241610176D stdsw off +6I1954195C 0762241764800?191517123H mpysc scramble +6I1954195C 0763241238800?658002154G ral 8002 symbol +6I1954195C 0764241547800?350003180F slt 0003 giving +6I1954195C 0765241806800?191759133? mpycf lo +6I1954195C 0766241330800?300001158G srt 0001 +6I1954195C 0767241587800?350004159G slt 0004 set +6I1954195C 0768241597800?151850185F alol1p1 test +6I1954195C 0769241856800?201865116H stllop1 word +6I1954195C 0770241168800?161020152E slo1dxxx +6I1954195C 0771241525800?201903148G stllo sli save lo +6I1954195C 0772241487800?201614800A sli stlli 8001 init li +6I1954800? 0773248001800?659990139E 8001ral 9990 a is cont of +6I1954195C 0774241395800?451098154I a nze und li zero +6I1954195C 0775241098800?161601175F slos is cont of +6I1954195C 0776241756800?451610181A nzesw def li symb +6I1954195C 0777241610800?651614127? sw ralli off is li +6I1954195C 0778241270800?161573122G off slolmax maximum +6I1954195C 0779241227800?451280133A nze max +6I1954195C 0780241280800?151533148G alolmp1 sli step li +6I1954195C 0781241800800?161903170H on slolo is li equa +6I1954195C 0782241708800?451412166D nze swsym to lo +6I1954195C 0783241412800?151865148G alolop1 sli step li +6I1954195C 0784241331800?691434153G max lddswon set +6I1954195C 0785241537800?241610171D stdsw switch on +6I1954195C 0786241714800?651467148G rall1 sli zero li +0?0000800? 0787 1 +6I1954195C 0788241549800?651416187A und ralexitz undefined +6I1954195C 0789241871800?150992164G alo1ixxx step +6I1954195C 0790241647800?201416137? stlexitz exit +6I1954195C 0791241370800?651614142? ralli +6I1954195C 0792241420800?161467192A slol1 +6I1954195C 0793241921800?201575127H stllsymb asu +0?0000800? 0794 1 +6I1954195C 0795241811800?651614147? def ralli defined +6I1954195C 0796241470800?691278138A lddasu subr8 get +6I1954195C 0797241278800?101601141F asu aups exitz equivalent +0?0000800? 0798 1 +6I1954195C 0799241664800?010111121H swsymhlt 0111 symof s tab full +6I1954195C 0800241218800?691971122D symoflddsymon set sw sym +6I1954195C 0801241224800?241664197A stdswsym symon on +6I1954195C 0802241971800?651416157B symonralexitz +6I1954195C 0803241572800?151771800B alo2ixxx 8002 +0?0000800? 0804 1 +6I1954195C 0805241758800?651614127? swof ralli off constants +6I1954195C 0806241434800?651614180? swon ralli on +6I1954195C 0807241517800?100100100A sc 10 0100 1001 +6I1954195C 0808241759800?000000000D cf 00 0000 0004 +6I1954195C 0809241467800?650000139E l1 ral 0000 a +6I1954195C 0810241850800?650001139E l1p1 ral 0001 a +6I1954195C 0811241573800?650399139E lmax rale0000 a +6I1954195C 0812241533800?650400139E lmp1 rale0001 a +6I1954195C 0813241601800?010000160A s 01 0000 s erasable +6I1954195C 0814241610800?010000161? sw 01 0000 sw +6I1954195C 0815241903800?010000190C lo 01 0000 lo +6I1954195C 0816241614800?010000161D li 01 0000 li +6I1954195C 0817241575800?010000157E lsymb 01 0000 lsymb +0?0000800? 0818 hed +0?0000800? 0819 1 +0?0000800? 0820 1 sub 7 store symbol and equiv +0?0000800? 0821 1 +0?0000800? 0822 hed7 +6I1954195C 0823241279800?241416152? subr7stdexitz store exit +6I1954195C 0824241520800?691623122F lddss +6I1954195C 0825241226800?221962800A sdaxxxx2 8001 store +6I1954800? 0826248001800?219988154A 8001stu 9988 a symbol +6I1954195C 0827241541800?118001159I a sup 8001 +6I1954195C 0828241599800?201961181D stlxxxx1 save e +6I1954195C 0829241814800?300004162E srt 0004 +6I1954195C 0830241625800?141771123B div2ixxx calculate +6I1954195C 0831241232800?350004149C slt 0004 location +6I1954195C 0832241493800?151446165A aloc1 of +6I1954195C 0833241651800?691704180H lddc2 e +6I1954195C 0834241808800?221911186D sdasel and +6I1954195C 0835241864800?691617162? lddc3 store +6I1954195C 0836241620800?221673127F sdaser +6I1954195C 0837241276800?201431148D stlobee +6I1954195C 0838241484800?168001159A slo 8001 +6I1954195C 0839241591800?151961143A aloxxxx1 obee +6I1954195C 0840241431800?699986138I obee ldd 9986 b +6I1954195C 0841241389800?441673124D b nzuser +6I1954195C 0842241244800?350004191A slt 0004 sel +6I1954195C 0843241623800?219987154A ss stu 9987 a constants +6I1954195C 0844241446800?690400138I c1 ldde0001 b +6I1954195C 0845241704800?229985141F c2 sda 9985 exitz +6I1954195C 0846241617800?239984141F c3 sia 9984 exitz +6I1954195C 0847241431800?010000143A obee 01 0000 obee erasable +6I1954195C 0848241911800?010000191A sel 01 0000 sel +6I1954195C 0849241673800?010000167C ser 01 0000 ser +0?0000800? 0850 hed +0?0000800? 0851 1 +0?0000800? 0852 1 sub 8 given sym loc get equiv +0?0000800? 0853 1 +0?0000800? 0854 hed8 +6I1954195C 0855241381800?241534163G subr8stdexit store exit +6I1954195C 0856241637800?698003129D ldd 8003 +6I1954195C 0857241294800?221575132H sdalsymb store l +6I1954195C 0858241328800?658001128E ral 8001 +6I1954195C 0859241285800?141288114H div2dxxx +6I1954195C 0860241148800?350004180I slt 0004 +6I1954195C 0861241809800?151462800B aloe1 8002 +6I1954800? 0862248002800?699975137H 8002ldd 9975 tr +6I1954195C 0863241378800?441481128B tr nzu lh +6I1954195C 0864241481800?678001143I ram 8001 lr get e rh +6I1954195C 0865241282800?678001148I lh ram 8001 get e lh +6I1954195C 0866241489800?300004143I srt 0004 lr +6I1954195C 0867241439800?698003149F lr ldd 8003 +6I1954195C 0868241496800?231223132F siaequiv +6I1954195C 0869241326800?651575153D rallsymb exit +6I1954195C 0870241462800?690400137H e1 ldde0001 tr constant +6I1954195C 0871241534800?010000153D exit 01 0000 exit eraseable +6I1954195C 0872241223800?010000122C equiv 01 0000 equiv +0?0000800? 0873 hed +0?0000800? 0874 1 +0?0000800? 0875 1 sub 9 calculate reg address +0?0000800? 0876 hed9 +6I1954195C 0877241174800?241416167? subr9stdexitz store exit +6I1954195C 0878241670800?300008153I srt 0008 +6I1954195C 0879241539800?658003169G ral 8003 +6I1954195C 0880241697800?350004185H slt 0004 +6I1954195C 0881241858800?151512800B aloc 8002 is +6I1954800? 0882248002800?659991144E 8002ral 9991 nex region +6I1954195C 0883241445800?901649170A nex bdoill defined +6I1954195C 0884241701800?350001190H slt 0001 +6I1954195C 0885241908800?658002166G ral 8002 +6I1954195C 0886241667800?300001172C srt 0001 +6I1954195C 0887241723800?691416172? lddexitz +6I1954195C 0888241720800?961773167E bd6 l +6I1954195C 0889241773800?951376142H bd5d i +6I1954195C 0890241675800?151957156B l alo 1957 all +6I1954195C 0891241376800?151958156B d alo 1958 all +6I1954195C 0892241428800?151959156B i alo 1959 all +6I1954195C 0893241562800?160992174G all slo1ixxx +6I1954195C 0894241747800?461649141F bmiill exitz +6I1954195C 0895241649800?651416162B ill ralexitz undefined +6I1954195C 0896241622800?150992800B alo1ixxx 8002 or illeg +0?0000800? 0897 1 +6I1954195C 0898241512800?650960144E c ral 0960 nex constant +0?0000800? 0899 hed +0?0000800? 0900 1 sub 10 set cc 8 and punch +0?0000800? 0901 1 +6I1954195C 0902241405800?151986164A sub10alop0010 +6I1954195C 0903241641800?151344169I alo84th +6I1954195C 0904241699800?201986158I stlp0010 +6I1954195C 0905241589800?711977800C pchp0001 8003 +0?0000800? 0906 1 +6I1954195C 0907241344800?000800000? 84th 00 0800 0000 constant +0?0000800? 0908 1 +0?0000800? 0909 1 sub 11 find and reserve best +0?0000800? 0910 1 +0?0000800? 0911 hed0 +6I1954195C 0912241801800?691212196E sub11ldddrumt test +6I1954195C 0913241965800?901770182? bdo sex drum tag +6I1954195C 0914241770800?201725147H stlexit is adr l +6I1954195C 0915241478800?961531163C bd6di +6I1954195C 0916241633800?658003174A ral 8003 ssw l +6I1954195C 0917241531800?691634178G di lddf d or i +6I1954195C 0918241787800?221961196D sdaxxxx1 sub13 find optim +6I1954195C 0919241851800?350004176B gda slt 0004 dynam adr +6I1954195C 0920241762800?158002167B alo 8002 +6I1954195C 0921241672800?158002174A alo 8002 ssw +6I1954195C 0922241741800?691444179G ssw lddoff set sw off +6I1954195C 0923241797800?241584183G stdsw +6I1954195C 0924241837800?151290149E aloa1p1 get table +6I1954195C 0925241495800?201915126H stlbp1 start addr +6I1954195C 0926241268800?161020177E slo1dxxx +6I1954195C 0927241775800?201804161B stlao sai save ao +6I1954195C 0928241612800?201687800A sai stlai 8001 +6I1954800? 0929248001800?609975157I 8001rau 9975 ta is locat +6I1954195C 0930241579800?441583158D ta nzuyes sw available +6I1954195C 0931241584800?601687169A sw rauai swof +6I1954195C 0932241691800?161394174I swof sloamax is ai max +6I1954195C 0933241749800?451502175D nze max +6I1954195C 0934241502800?151906161B aloamp1 sai step ai +6I1954195C 0935241751800?161804185I swon sloao is ai equa +6I1954195C 0936241859800?451662191D nze full to ao +6I1954195C 0937241662800?151915161B alobp1 sai step ai +6I1954195C 0938241754800?691909171B max lddon set sw on +6I1954195C 0939241712800?241584173G stdsw +6I1954195C 0940241737800?651240161B rala1 sai set ai to +0?0000800? 0941 1 +6I1954195C 0942241914800?010222131H full hlt 0222 drum paked +6I1954195C 0943241318800?691216187? lddh9xxx set drum +6I1954195C 0944241870800?241212146F stddrumt tag to 9 +6I1954195C 0945241466800?651725182? ralexit sex step exit +6I1954195C 0946241820800?150992800B sex alo1ixxx 8002 +0?0000800? 0947 1 +6I1954195C 0948241583800?360000166? yes sct 0000 reserve +6I1954195C 0949241660800?350001171G slt 0001 location +6I1954195C 0950241717800?300001182C srt 0001 found +6I1954195C 0951241823800?201962151F stlxxxx2 save p +6I1954195C 0952241516800?118003187C sup 8003 +6I1954195C 0953241873800?350004168C slt 0004 +6I1954195C 0954241683800?108001179A aup 8001 +6I1954195C 0955241791800?151494800B alosrp 8002 +6I1954800? 0956248002800?300009172B 8002srt 0009 sca nulify sct +6I1954195C 0957241722800?608003162I sca rau 8003 +6I1954195C 0958241629800?151687184A aloai +6I1954195C 0959241841800?691544184G lddst +6I1954195C 0960241847800?221901800A sdaeras 8001 +6I1954800? 0961248001800?219972182E 8001stu 9972 ca +6I1954195C 0962241825800?118001173C ca sup 8001 calculate +6I1954195C 0963241733800?161240154E sloa1 location +6I1954195C 0964241545800?300004171? srt 0004 found +6I1954195C 0965241710800?141616142F div4i +6I1954195C 0966241426800?191679155B mpy500 +6I1954195C 0967241552800?158003176? alo 8003 +6I1954195C 0968241760800?118001176G sup 8001 +6I1954195C 0969241767800?101962181G aupxxxx2 +6I1954195C 0970241817800?191920134? mpy50 +6I1954195C 0971241340800?158003189G alo 8003 +6I1954195C 0972241897800?118001172E sup 8001 exit +6I1954195C 0973241634800?000000185A f 00 0000 gda constants +6I1954195C 0974241444800?651687169A off ralai swof +6I1954195C 0975241290800?600601157I a1p1 raua0002 ta +6I1954195C 0976241394800?600799157I amax raua0200 ta +6I1954195C 0977241906800?600800157I amp1 raua0201 ta +6I1954195C 0978241909800?651687175A on ralai swon +6I1954195C 0979241240800?600600157I a1 raua0001 ta +6I1954195C 0980241494800?300000172B srp srt 0000 sca +6I1954195C 0981241544800?219999182E st stu 9999 ca +6I1954195C 0982241616800?000000000D 4i 00 0000 0004 +6I1954195C 0983241679800?000000050? 500 00 0000 0500 +6I1954195C 0984241920800?000000005? 50 00 0000 0050 +6I1954195C 0985241602800?658001181? fon ral 8001 stepx +6I1954195C 0986241804800?010000180D ao 01 0000 ao erasable +6I1954195C 0987241687800?010000168G ai 01 0000 ai +6I1954195C 0988241915800?010000191E bp1 01 0000 bp1 +6I1954195C 0989241725800?010000172E exit 01 0000 exit +0?0000800? 0990 hed +0?0000800? 0991 1 +0?0000800? 0992 1 sub 12 set blank l 8 +0?0000800? 0993 1 +6I1954195C 0994240991800?151986189A sub12alop0010 +6I1954195C 0995241891800?151594179I alo87th +6I1954195C 0996241799800?201986800C stlp0010 8003 +0?0000800? 0997 1 +6I1954195C 0998241594800?000000800? 87th 00 0000 8000 constant +0?0000800? 0999 1 +0?0000800? 1000 1 sub 13 cal optimum dynamic adr +0?0000800? 1001 1 +0?0000800? 1002 hedy +6I1954195C 1003241964800?241416197? sub13stdexitz store exit +6I1954195C 1004241970800?951923187E bd5 i d or i +6I1954195C 1005241923800?651452186? raloptim d +6I1954195C 1006241860800?350001186G slt 0001 +6I1954195C 1007241867800?168002192E slo 8002 +6I1954195C 1008241925800?350001158A slt 0001 +6I1954195C 1009241581800?158001163I alo 8001 +6I1954195C 1010241639800?300003194G srt 0003 seo +6I1954195C 1011241875800?651452191? i raloptim i +6I1954195C 1012241910800?921666171F bd2shop shift test +6I1954195C 1013241716800?931772182B bd3xas xas test +6I1954195C 1014241822800?350002194G slt 0002 seo +6I1954195C 1015241947800?201961176F seo stlxxxx1 save ev od +6I1954195C 1016241766800?651872127G ralopreg is base +6I1954195C 1017241277800?141771133B div2ixxx even or od +6I1954195C 1018241332800?608003168I rau 8003 +6I1954195C 1019241689800?151961181F aloxxxx1 +6I1954195C 1020241816800?441922197B nzu rb +6I1954195C 1021241922800?350002172I slt 0002 +6I1954195C 1022241729800?658002197B ral 8002 rb +6I1954195C 1023241972800?300008194A rb srt 0008 get base +6I1954195C 1024241941800?151872132G aloopreg plus delta +6I1954195C 1025241327800?141380139? div50 mod 50 +6I1954195C 1026241390800?658003141F ral 8003 exitz +0?0000800? 1027 1 +6I1954195C 1028241666800?651983188G shop ralp0007 tlu units +6I1954195C 1029241887800?300004199G srt 0004 digit of +6I1954195C 1030241997800?350009191G slt 0009 d address +6I1954195C 1031241917800?168002197E slo 8002 +6I1954195C 1032241975800?841250181B tluu0001 +6I1954195C 1033241812800?151866800B alogu 8002 +6I1954800? 1034248002800?659969197C 8002ral 9969 top +6I1954195C 1035241973800?350002177I top slt 0002 +6I1954195C 1036241779800?691452186B lddoptim is op srd +6I1954195C 1037241862800?931916194G bd3 seo +6I1954195C 1038241916800?350004194G slt 0004 seo srd +0?0000800? 1039 1 +6I1954195C 1040241772800?651983193G xas ralp0007 tlu +6I1954195C 1041241937800?300004119H srt 0004 d address +6I1954195C 1042241198800?350006196F slt 0006 +6I1954195C 1043241966800?168002147F slo 8002 +6I1954195C 1044241476800?841300191B tlui0001 +6I1954195C 1045241912800?151967800B alogxd 8002 +6I1954800? 1046248002800?659968127D 8002ral 9968 nxt +6I1954195C 1047241274800?350004194G nxt slt 0004 seo +0?0000800? 1048 1 +6I1954195C 1049241250800?002322252D u0001 00 2322 2524 shift +6I1954195C 1050241251800?100706070F u0002 10 0706 0706 optimizing +6I1954195C 1051241252800?200706090H u0003 20 0706 0908 table +6I1954195C 1052241253800?300908111? u0004 30 0908 1110 +6I1954195C 1053241254800?401110131B u0005 40 1110 1312 +6I1954195C 1054241255800?501312151D u0006 50 1312 1514 +6I1954195C 1055241256800?601514171F u0007 60 1514 1716 +6I1954195C 1056241257800?701716191H u0008 70 1716 1918 +6I1954195C 1057241258800?801918212? u0009 80 1918 2120 +6I1954195C 1058241259800?902120232B u0010 90 2120 2322 +0?0000800? 1059 1 +6I1954195C 1060241300800?199906060? i0001 19 9906 0600 x accum +6I1954195C 1061241301800?799907070? i0002 79 9907 0700 add sub +6I1954195C 1062241302800?800008080? i0003 80 0008 0800 table +6I1954195C 1063241303800?800106060? i0004 80 0106 0600 +6I1954195C 1064241304800?800209080? i0005 80 0209 0800 +6I1954195C 1065241305800?800308090? i0006 80 0308 0900 +6I1954195C 1066241306800?905908080? i0007 90 5908 0800 +6I1954195C 1067241307800?999909090? i0008 99 9909 0900 +0?0000800? 1068 1 +6I1954195C 1069241866800?650000197C gu ral 0000 top constants +6I1954195C 1070241967800?650000127D gxd ral 0000 nxt +6I1954195C 1071241380800?000000005? 50 00 0000 0050 +0?0000800? 1072 hed +0?0000800? 1073 1 +0?0000800? 1074 1 sub 14 punch avail table +0?0000800? 1075 1 +0?0000800? 1076 hedp +6I1954195C 1077241403800?241196184I sub14stdexitx store exit +6I1954195C 1078241849800?691652136H ldd85th set punch +6I1954195C 1079241368800?241986173I stdp0010 8 +6I1954195C 1080241739800?691292159E ldda1 init a1 +6I1954195C 1081241595800?241961141H stdxxxx1 +6I1954195C 1082241418800?651324182I ralrs1 loop init rs +6I1954195C 1083241829800?101382800A loop aupc1 8001 +6I1954800? 1084248001800?209999170B 8001stl 9999 next set locat +6I1954195C 1085241702800?111468137D next suptw1 +6I1954195C 1086241374800?441377152H nzu srs +6I1954195C 1087241377800?101430133E aupc2 +6I1954195C 1088241335800?151338800C aloc3 8003 +6I1954195C 1089241528800?201962151H srs stlxxxx2 save rs +6I1954195C 1090241518800?601424187I rauc4 +6I1954195C 1091241879800?151961800B aloxxxx1 8002 +6I1954800? 1092248002800?699998800C 8002ldd 9998 8003 store +6I1954800? 1093248003800?249997175B 8003std 9997 tp av table +6I1954195C 1094241752800?111618147D tp suptw2 +6I1954195C 1095241474800?441427157H nzu pun +6I1954195C 1096241427800?101480138E aupc5 +6I1954195C 1097241385800?151388800B aloc6 8002 +6I1954195C 1098241578800?711977147G pun pchp0001 +6I1954195C 1099241477800?161530143E sloaim is ai max +6I1954195C 1100241435800?451438119F nze exitx +6I1954195C 1101241438800?151342124H aloamp1 step ai +6I1954195C 1102241248800?201961166H stlxxxx1 +6I1954195C 1103241668800?651962171H ralxxxx2 +6I1954195C 1104241718800?161524182I sloc7 loop +0?0000800? 1105 1 +6I1954195C 1106241382800?201977170B c1 stlp0001 next constants +6I1954195C 1107241430800?201985170B c2 stlp0009 next +6I1954195C 1108241338800?000500050? c3 00 0500 0500 +6I1954195C 1109241424800?241978175B c4 stdp0002 tp +6I1954195C 1110241480800?241986175B c5 stdp0010 tp +6I1954195C 1111241388800?000001000? c6 00 0001 0000 +6I1954195C 1112241524800?001499149I c7 00 1499 1499 +6I1954195C 1113241468800?201983170B tw1 stlp0007 next +6I1954195C 1114241618800?241984175B tw2 stdp0008 tp +6I1954195C 1115241652800?000080000? 85th 00 0080 0000 +6I1954195C 1116241292800?690600800C a1 ldda0001 8003 +6I1954195C 1117241324800?000000045? rs1 00 0000 0450 +6I1954195C 1118241530800?690799800C aim ldda0200 8003 +6I1954195C 1119241342800?690800800C amp1 ldda0201 8003 +0?0000800? 1120 hed +0?0000800? 1121 1 +0?0000800? 1122 1 sub 15 heading routine +0?0000800? 1123 1 +0?0000800? 1124 hedh +6I1954195C 1125241663800?241813176H sub15stdexity save exit +6I1954195C 1126241768800?698003157D ldd 8003 is c1 +6I1954195C 1127241574800?350008154C slt 0008 blank +6I1954195C 1128241543800?441298134H nzudh +6I1954195C 1129241348800?608001181H rau 8001 head +6I1954195C 1130241818800?101329181C aup0000h exity +6I1954195C 1131241298800?608001181C dh rau 8001 exity dont head +0?0000800? 1132 hed +0?0000800? 1133 1 +0?0000800? 1134 1 sub 16 initialization +0?0000800? 1135 1 +6I1954195C 1136241353800?241813186H sub16stdexity store exit +6I1954195C 1137241868800?651624192I rali1 +6I1954195C 1138241929800?211985148H stup0009 zero card +6I1954195C 1139241488800?241329143B std0000h zero head +6I1954195C 1140241432800?691485160? ldd subr1 zero sym t +6I1954195C 1141241485800?651538159C rali2 make drum +6I1954195C 1142241593800?101546180B aupi3 available +6I1954195C 1143241802800?691918160? ldd subr1 +6I1954195C 1144241918800?691406196H lddh8xxx set drum +6I1954195C 1145241968800?241212167D stddrumt tag to 8 +6I1954195C 1146241674800?691527158? lddi4 set swsym +6I1954195C 1147241580800?241664172D stdswsym off +6I1954195C 1148241724800?651577163A rali5 undefine +6I1954195C 1149241631800?101406177D auph8xxx regions +6I1954195C 1150241774800?691813160? lddexity subr1 +0?0000800? 1151 1 +6I1954195C 1152241624800?000000059I i1 00s0001 e0200 constants +6I1954195C 1153241538800?000600079I i2 00a0001 a0200 +6I1954195C 1154241546800?111111111A i3 11 1111 1111 +6I1954195C 1155241527800?010111121H i4 01 0111 symof +6I1954195C 1156241577800?001021104I i5 00 1021 1049 +6I1954195C 1157241852800?961824187D pacofbd6findi findl +0?0000800? 1158 1 +0?0000800? 1159 1 sub 17 calc 800x equivalent +0?0000800? 1160 1 +0?0000800? 1161 hedx +6I1954195C 1162241902800?691924162G sb17dldddeq di d equiv +6I1954195C 1163241854800?691974162G sb17ilddieq di i equiv +6I1954195C 1164241627800?241961152F di stdxxxx1 save tag +6I1954195C 1165241526800?211813157F stuexity store exit +6I1954195C 1166241576800?201962162F stlxxxx2 store 800x +6I1954195C 1167241626800?691961196D lddxxxx1 sub13 get optim +6I1954195C 1168241904800?201961167F sda stlxxxx1 dynam addr +6I1954195C 1169241676800?141771148B div2ixxx is dy addr +6I1954195C 1170241482800?441535138F nzuod ev even or od +6I1954195C 1171241535800?651588164C od ral8002 eo +6I1954195C 1172241386800?651789164C ev ral8003 eo +6I1954195C 1173241643800?161962172F eo sloxxxx2 +6I1954195C 1174241726800?451630168A nze add1 +6I1954195C 1175241630800?651961181C ralxxxx1 exity +6I1954195C 1176241681800?651961177F add1 ralxxxx1 +6I1954195C 1177241776800?150992181C alo1ixxx exity +0?0000800? 1178 1 +6I1954195C 1179241924800?000008190D deq 00 0008 sda constants +6I1954195C 1180241974800?000009190D ieq 00 0009 sda +6I1954195C 1181241588800?000000800B 8002 00 0000 8002 +6I1954195C 1182241789800?000000800C 8003 00 0000 8003 +0?0000800? 1183 hed +0?0000800? 1184 1 +0?0000800? 1185 1 sub 18 index address +0?0000800? 1186 1 +0?0000800? 1187 hedw +6I1954195C 1188241826800?241813187F indexstdexity store exit +6I1954195C 1189241876800?201961192F stlxxxx1 store addr +6I1954195C 1190241926800?601954197F rau 1954 +6I1954195C 1191241976800?350007169C slt 0007 +6I1954195C 1192241693800?691813167G lddexity +6I1954195C 1193241677800?951680153B bd5d d or i +6I1954195C 1194241532800?350002168? slt 0002 d +6I1954195C 1195241680800?300009172G d srt 0009 +6I1954195C 1196241727800?191014168D mpy2000i +6I1954195C 1197241684800?691813177G lddexity +6I1954195C 1198241777800?961730158B bd6ds drum 0 cor +6I1954195C 1199241582800?300001173? srt 0001 ds core +6I1954195C 1200241730800?151961181C ds aloxxxx1 exity +0?0000800? 1201 1 +6I1954195C 1202241813800?010000181C exity 01 0000 exity erasabele +0?0000800? 1203 hed +0?0000800? 1204 1 +0?0000800? 1205 1 sub 19 process location +0?0000800? 1206 1 +0?0000800? 1207 regd0923 0923 proc l +0?0000800? 1208 regg0925 0925 +0?0000800? 1209 regj0928 0928 +0?0000800? 1210 regk0931 0931 +0?0000800? 1211 regl0933 0933 +0?0000800? 1212 1 +0?0000800? 1213 heda +6I1954195C 1214240969800?241196189I proclstdexitx store exit +6I1954195C 1215241899800?601951182G rau 1951 is l blank +6I1954195C 1216241827800?441731163B nzunb +6I1954195C 1217241632800?691212187G ldddrumt blank test +6I1954195C 1218241877800?901781092D bdob d0002 drum tag +6I1954195C 1219241781800?651872192G b ralopreg setl blank +6I1954195C 1220241927800?350004198G setl slt 0004 set l +6I1954195C 1221241987800?691984163H lddp0008 to dr +6I1954195C 1222241638800?221984119F sdap0008 exitx +6I1954195C 1223241731800?691734121C nb lddg subr4 what is l +6I1954195C 1224240925800?651957093A g0001ral 1957 k0001 absolute +6I1954195C 1225240926800?691780117D g0002lddk subr9 regional +6I1954195C 1226240927800?691830127E g0003lddj subr6 symbolic +6I1954195C 1227240931800?691784175? k0001lddl subr5 test range +6I1954195C 1228240932800?601585183I k0002rau87th x reg error +6I1954195C 1229241839800?101986139B x aupp0010 set blank +6I1954195C 1230241392800?211986192G stup0010 setl l8 +6I1954195C 1231240933800?201872192G l0001stlopreg setl drum addr +6I1954195C 1232240934800?101688174C l0002aup86th 800x 800x +6I1954195C 1233240935800?691738144B l0003lddorceq 89x core addr +6I1954195C 1234240936800?601585183I l0004rau87th x other +6I1954195C 1235241743800?691596144B 800x lddorxeq 89x +6I1954195C 1236241442800?241872183I 89x stdopreg x +6I1954195C 1237240928800?651223093A j0001ralequiv k0001 sym defind +6I1954195C 1238240929800?651682180A j0002rald sub11 sym undef +6I1954195C 1239240930800?601585183I j0003rau87th x s tab full +6I1954195C 1240240923800?201872162H d0001stlopreg ss s eq found +6I1954195C 1241240924800?601585183I d0002rau87th x drum paked +6I1954195C 1242241628800?101230163E ss auphsymb store +6I1954195C 1243241635800?151575188? alolsymb symbol +6I1954195C 1244241880800?691781127I lddb subr7 +0?0000800? 1245 1 +6I1954195C 1246241734800?000000092E g 00 0000 g0001 constants +6I1954195C 1247241780800?000090093A k 00 0090 k0001 +6I1954195C 1248241830800?000000092H j 00 0000 j0001 +6I1954195C 1249241784800?000000093C l 00 0000 l0001 +6I1954195C 1250241682800?000090092C d 00 0090 d0001 +6I1954195C 1251241688800?000008000? 86th 00 0008 0000 +6I1954195C 1252241585800?000000800? 87th 00 0000 8000 +6I1954195C 1253241196800?010000119F exitx 01 0000 exitx eraseable +0?0000800? 1254 hed +0?0000800? 1255 1 +0?0000800? 1256 1 sub 20 process data address +0?0000800? 1257 1 +0?0000800? 1258 regd0937 0937 proc d +0?0000800? 1259 regf0939 0939 +0?0000800? 1260 regg0941 0941 +0?0000800? 1261 regj0944 0944 +0?0000800? 1262 regk0946 0946 +0?0000800? 1263 regl0949 0949 +0?0000800? 1264 1 +0?0000800? 1265 hedb +6I1954195C 1266240972800?241196194I procdstdexitx store exit +6I1954195C 1267241949800?601952167H rau 1952 is d blank +6I1954195C 1268241678800?441831173B nzunb +6I1954195C 1269241732800?651685180A rald sub11 find +6I1954195C 1270240937800?201492095B d0001stlorbal l0004 optimum +6I1954195C 1271240938800?601542139H d0002rau88th x drum paked +6I1954195C 1272241728800?691452177H bt lddoptim is op +6I1954195C 1273241778800?911196178C bd1exitx a branch +6I1954195C 1274241783800?201872119F stlopreg exitx d to or +6I1954195C 1275241398800?101986159B x aupp0010 set blank +6I1954195C 1276241592800?211986119F stup0010 exitx +6I1954195C 1277241831800?691834121C nb lddg subr4 what is d +6I1954195C 1278240941800?651958094D g0001ral 1958 j0001 absolute +6I1954195C 1279240942800?691645117D g0002lddj subr9 regional +6I1954195C 1280240943800?691646127E g0003lddk subr6 symbolic +6I1954195C 1281240944800?691448175? j0001lddl subr5 test range +6I1954195C 1282240945800?601542139H j0002rau88th x reg error +6I1954195C 1283240949800?691828182F l0001lddaxd index drum addr +6I1954195C 1284240950800?350004187H l0002slt 0004 800x 800x +6I1954195C 1285240951800?691928182F l0003lddaxc index core addr +6I1954195C 1286240952800?350004193? l0004slt 0004 sd other +6I1954195C 1287241878800?691983143F 800x lddp0007 set 800x d +6I1954195C 1288241436800?221983148F sdap0007 +6I1954195C 1289241486800?300004149H srt 0004 +6I1954195C 1290241498800?101881190B aupxeq sb17d get 800x e +6I1954195C 1291241931800?350004164B scd slt 0004 set core d +6I1954195C 1292241642800?691983153F lddp0007 +6I1954195C 1293241536800?221983158F sdap0007 +6I1954195C 1294241586800?300004154H srt 0004 +6I1954195C 1295241548800?691782196D lddceq sub13 get core e +6I1954195C 1296241832800?201738172H sceq stlorceq bt save core +6I1954195C 1297240946800?651223094D k0001ralequiv j0001 sym defind +6I1954195C 1298240947800?651882180A k0002ralf sub11 sym undef +6I1954195C 1299240948800?601542139H k0003rau88th x s tab full +6I1954195C 1300240939800?201793169F f0001stleq ss save eq +6I1954195C 1301240940800?601542139H f0002rau88th x drum paked +6I1954195C 1302241696800?101230173E ss auphsymb store +6I1954195C 1303241735800?151575193B alolsymb symbol +6I1954195C 1304241932800?691785127I ldd subr7 +6I1954195C 1305241785800?651793095B raleq l0004 +6I1954195C 1306241930800?691983163F sd lddp0007 set d addr +6I1954195C 1307241636800?221983168F sdap0007 +6I1954195C 1308241686800?300004172H srt 0004 bt +6I1954195C 1309241685800?000088093G d 00 0088 d0001 constants +6I1954195C 1310241834800?000000094A g 00 0000 g0001 +6I1954195C 1311241645800?000088094D j 00 0088 j0001 +6I1954195C 1312241448800?000000094I l 00 0000 l0001 +6I1954195C 1313241882800?000088093I f 00 0088 f0001 +6I1954195C 1314241646800?000000094F k 00 0000 k0001 +6I1954195C 1315241828800?000088093G axd 00 0088 d0001 +6I1954195C 1316241928800?000098193A axc 00 0098 scd +6I1954195C 1317241881800?201596172H xeq stlorxeq bt +6I1954195C 1318241782800?000008183B ceq 00 0008 sceq +6I1954195C 1319241542800?000000080? 88th 00 0000 0800 +6I1954195C 1320241793800?010000179C eq 01 0000 eq erasable +0?0000800? 1321 hed +0?0000800? 1322 1 +0?0000800? 1323 1 sub 21 process instr address +0?0000800? 1324 1 +0?0000800? 1325 regd0953 0953 proc i +0?0000800? 1326 regf0955 0955 +0?0000800? 1327 regg0958 0958 +0?0000800? 1328 regj0960 0960 +0?0000800? 1329 regk0962 0962 +0?0000800? 1330 regl0965 0965 +0?0000800? 1331 1 +0?0000800? 1332 hedc +6I1954195C 1333241453800?241196183C procistdexitx store exit +6I1954195C 1334241833800?601953188C rau 1953 is i blank +6I1954195C 1335241883800?441788183H nzunb +6I1954195C 1336241838800?601952193C rau 1952 is d blank +6I1954195C 1337241933800?441888193H nzudnb +6I1954195C 1338241938800?691212188D ldddrumt d i blank +6I1954195C 1339241884800?901988095I bdo g0002 test drum +6I1954195C 1340241988800?651492096H ralorbal l0004 tag +6I1954195C 1341241888800?651692180A dnb rald sub11 find best +6I1954195C 1342240953800?201492096H d0001stlorbal l0004 found +6I1954195C 1343240954800?651986174B d0002ralp0010 x drum paked +6I1954195C 1344241742800?151695193D x alo89th +6I1954195C 1345241934800?201986119F stlp0010 exitx +6I1954195C 1346241788800?691792121C nb lddf subr4 what is i +6I1954195C 1347240955800?651959096? f0001ral 1959 j0001 absolute +6I1954195C 1348240956800?691835117D f0002lddj subr9 regional +6I1954195C 1349240957800?691885127E f0003lddk subr6 symbolic +6I1954195C 1350240960800?691935175? j0001lddl subr5 test range +6I1954195C 1351240961800?651986174B j0002ralp0010 x reg error +6I1954195C 1352240965800?691736182F l0001lddaxd index drum addr +6I1954195C 1353240966800?691983178F l0002lddp0007 800x 800x +6I1954195C 1354240967800?691836182F l0003lddaxc index core addr +6I1954195C 1355240968800?691983188F l0004lddp0007 other +6I1954195C 1356241886800?231983193F siap0007 mor +6I1954195C 1357241786800?231983188I 800x siap0007 +6I1954195C 1358241889800?101842185D aupxeq sb17i get 800x e +6I1954195C 1359241939800?691983198I 90xx lddp0007 set core +6I1954195C 1360241989800?231983144? siap0007 address +6I1954195C 1361241440800?691843196D lddceq sub13 get core e +6I1954195C 1362240962800?651223096? k0001ralequiv j0001 sym defind +6I1954195C 1363240963800?651490180A k0002ralg sub11 sym undef +6I1954195C 1364240964800?651986174B k0003ralp0010 x s tab full +6I1954195C 1365240958800?691983154? g0001lddp0007 si found best +6I1954195C 1366240959800?651986174B g0002ralp0010 x drum paked +6I1954195C 1367241540800?231983159? si siap0007 +6I1954195C 1368241590800?101230164? auphsymb store +6I1954195C 1369241640800?151575169? alolsymb symbol +6I1954195C 1370241690800?691936127I lddmor subr7 +6I1954195C 1371241936800?691492174E mor lddorbal set or +6I1954195C 1372241745800?241872119F stdopreg exitx to orb +6I1954195C 1373241740800?201738193F sceq stlorceq mor save core +0?0000800? 1374 1 +6I1954195C 1375241692800?000089095C d 00 0089 d0001 constants +6I1954195C 1376241792800?000000095E f 00 0000 f0001 +6I1954195C 1377241835800?000089096? j 00 0089 j0001 +6I1954195C 1378241885800?000000096B k 00 0000 k0001 +6I1954195C 1379241935800?000000096E l 00 0000 l0001 +6I1954195C 1380241490800?000089095H g 00 0089 g0001 +6I1954195C 1381241695800?000000008? 89th 00 0000 0080 +6I1954195C 1382241736800?000089096H axd 00 0089 l0004 +6I1954195C 1383241836800?000099193I axc 00 0099 90xx +6I1954195C 1384241842800?201596193F xeq stlorxeq mor +6I1954195C 1385241843800?000009174? ceq 00 0009 sceq +0?0000800? 1386 hed +0?0000800? 1387 1 +6I1954195C 1388240992800?000000000A 1ixxx 00 0000 0001 constants +6I1954195C 1389241020800?000001000? 1dxxx 00 0001 0000 +6I1954195C 1390241771800?000000000B 2ixxx 00 0000 0002 +6I1954195C 1391241288800?000002000? 2dxxx 00 0002 0000 +6I1954195C 1392241406800?800000000? h8xxx 80 0000 0000 +6I1954195C 1393241216800?900000000? h9xxx 90 0000 0000 +6I1954195C 1394241178800?000000009? 90xxx 00 0000 0090 +6I1954195C 1395241189800?000000002I 29xxx 00 0000 0029 +6I1954195C 1396241014800?000000200? 2000i 00 0000 2000 constant +6I1954195C 1397240990800?000000199? torg 00 0000 t0001 +0?0000800? 1398 1 +0?0000800? 1399 pat +0A0000100? 1400 diff --git a/I650/sw/it_soapII_patch.dck b/I650/sw/it/soapII_patch.dck similarity index 100% rename from I650/sw/it_soapII_patch.dck rename to I650/sw/it/soapII_patch.dck diff --git a/I650/sw/it_soapII_patch.txt b/I650/sw/it/soapII_patch.txt similarity index 92% rename from I650/sw/it_soapII_patch.txt rename to I650/sw/it/soapII_patch.txt index 6b570c61..1d561837 100644 --- a/I650/sw/it_soapII_patch.txt +++ b/I650/sw/it/soapII_patch.txt @@ -1,6 +1,7 @@ ; These are the patches needed to make ; SOAP II to run with IT +; (patches on original listing are for SOAP I) ; free address 1993, using 1945 instead dep 0954 65 1986 1945 diff --git a/I650/sw/it_soapIIA_patch_listing.txt b/I650/sw/it/soap_patch_listing.txt similarity index 100% rename from I650/sw/it_soapIIA_patch_listing.txt rename to I650/sw/it/soap_patch_listing.txt diff --git a/I650/sw/it_subr_sin_listing.txt b/I650/sw/it_subr_sin_listing.txt deleted file mode 100644 index 00b09cde..00000000 --- a/I650/sw/it_subr_sin_listing.txt +++ /dev/null @@ -1,87 +0,0 @@ - 5 SUBROUTINE 22 SINE - E00AW STD ARTHX BEGIN SINE - STL ARTHE SUBROUTINE - SLT 0008 STORE - STU ARTHF ARGUMENT - RSM 8002 IS POWER - ALO AW1 OVERSCALE - BMI AW2 IF SO ALARM - SLO AW3 IS P0WER - BMI AW4 UNDERSCALE - SRT 0004 IF SO SINX - ALO AW5 EQUALS X - STL AW6 - RAU ARTHF F0RM FRACTL - MPY AW7 AW6 PART - AW6 HLT AW6 AW23 - AW23 STL ARTHG - RAU 8003 IS INTGRAL - MPY AW8 PAR7 0DD - RAL 8002 - NZE AW9 IF SO FLIP - RSL ARTHE SGN OF X - STL ARTHE AW9 - AW9 RSM ARTHG FORM S AS 2 - SML 8001 MINUS 2 ALPH - NZU AW10 IF 2 ALPH - AUP AW11 GRTG 1 OR 2 - NZU AW17 AW10 ALPH OTHER - AU10 RAM 8002 WISE - STL ARTHF FORM SINE - RAU 8002 POLYNOMIAL - MPY 8001 - STU ARTHG APPROXIMATOR - RAU AW16 - MPY ARTHG - RAU 8003 - AUP AW15 - MPY ARTHG - RAU 8003 - AUP AW14 - MPY ARTHG - RAU 8003 - AUP AW13 - MPY ARTHG - SRT 0001 - RAU 8003 - AUP AW12 - MPY ARTHF - SCT 0000 - BOV AW19 - STL ARTHF SINE TO 0 - RAL 8003 - SRT 0002 ROUND - STL ARTHG - RSU ARTHF - SRT 0002 ADJUST POWER - BMI AW25 - SUP 8003 - ALO AW8 AW24 - AW24 AUP ARTHG - SLT 0002 AW22 - AW25 SUP 8003 - SLO AW8 AW24 - AW22 STU ARTHF DETERMINE - RAL ARTHE PROPER SIGN - BMI AW20 OF RESULT - RSL ARTHF ARTHX EXIT - AW20 RAL ARTHF ARTHX EXIT - AW4 RAL ARTHE ARTHX SINX IS X - AW17 RAU AW21 AW22 SINX IS ONE - AW19 RAL 8002 SINX IS ZERO - SLO 8001 ARTHX - AW1 57 0000 0000 CONSTANTS - AW3 09 0000 0000 - AW5 SRT 0009 AW23 - AW7 31 8309 8862 - AW8 50 0000 0000 - AW11 00 0000 0002 - AW12 15 7079 6318 - AW13 - 64 5963 7111 - AW14 07 9689 6793 - AW15 - 00 4673 7656 - AW16 00 0151 4842 - AW21 10 0000 0050 - AW2 RAL ARTHE ALARM FOR - LDD ARTHX 3221 SINE - 5 LAST CARD SUBROUTINE 22 diff --git a/I650/sw/run_fortransit.ini b/I650/sw/run_fortransit.ini new file mode 100644 index 00000000..20218c79 --- /dev/null +++ b/I650/sw/run_fortransit.ini @@ -0,0 +1,247 @@ + +; set console -n log=log.txt +; set debug -n debug.txt +; set debug stdout +; set cpu debug=cmd;data;detail + + +; params: %1 source program card deck to compile +; %2 input program data card deck (if empty, do not attach input card) +; %3 output program data card deck (if empty, attach deck_out.dck file) + +set cpu 2k +set cpu StorageUnit + +att cdp0 -n -q print.txt + +; print FORTRANSIT source program + +echo +carddeck -q print %1 + +; load FORTRANSIT translator but do not execute it + +echo *** +echo *** Load FORTRANSIT translator deck into drum +echo *** + +att cdr1 -q -l fortransit/fortransit_translator.dck + +d csw 70 1951 9999 +d ar 8000 +go + +; attach and load reconstructed add function title deck + +att cdr1 -q -l fortransit/fortransit_addfn.dck + +d csw 70 1951 9999 +d ar 8000 +go + +echo *** +echo *** Run FORTRANSIT translator +echo *** + +; Now put source cards in reader and start translator (phase I) + +att cdr1 -q %1 +set cdr1 wiring=fortransit + +att cdp1 -n -q deck_it.dck +set cdp1 echo, print, wiring=fortransit + +d csw 00 0000 1999 +d ar 8000 +go + +; check if programed stop because an error is detected +if not prop=01 goto translate_ok1 + +echo +echo *** (translation error code in Address Register AR) +echo + +ex ar + +echo +echo *** (show last three source fortransit cards processed) +echo +carddeck -q echolast 3 cdr1 + +goto end + +:translate_ok1 + +; check if programed stop because normal termination +if prop=70 if ar=1951 goto translate_ok2 +goto end + +:translate_ok2 + +; separate last card (header card), and put it in the +; top of deck + +carddeck -q split -1 cdp1 deck_it.dck deck_it_header.dck +carddeck -q join deck_it_header.dck deck_it.dck as deck_it.dck +det cdr1 + +; load IT compiler but do not execute it + +echo *** +echo *** Load IT compiler deck into drum +echo *** + +att cdr1 -q -l fortransit/it_compiler.dck + +d csw 70 1951 9999 +d ar 8000 +go + +echo *** +echo *** Run IT compiler +echo *** + +; Now put IT source cards in reader and start compiler (phase II) + +att cdr1 -q deck_it.dck +att cdp1 -n -q deck_out.dck + +d csw 00 0000 1999 +d ar 8000 +go + +; check if programed stop because an error is detected +if not prop=01 if not ar=1234 goto compile_ok1 + +echo +echo *** (compilation error code in Upper ACC) +echo + +ex accup +goto end + +:compile_ok1 + +; check if programed stop because normal termination +if prop=70 if ar=1951 goto compile_ok2 +goto end + +:compile_ok2 + +; separate first card (reservation card), from +; generated soap source code deck + +carddeck -q split 1 cdp1 deck_res.dck deck_soap.dck +det cdr1 + +; Load soap deck into drum (1 word per card format), but does not execute it + +echo *** +echo *** Load SOAP deck into drum +echo *** + +att cdr1 -q -l fortransit/soapII.dck + +d csw 7019519999 +d ar 8000 +go + +; create the phase III deck with +; - entry point cards for subroutines +; - reservation cards from phase II +; - package reservation cards +; - subroutines in symbolic SOAP format (if any) +; - rest of compilation output from phase II + +carddeck -q join fortransit/pack_entry_src.txt deck_res.dck fortransit/pack_res2.txt deck_soap.dck as deck_soap.dck + +echo *** +echo *** Run SOAP assembler +echo *** + +att cdr1 deck_soap.dck +set cdr1 wiring=soap + +att cdp1 -n -q deck_out.dck +set cdp1 echo, print, wiring=soap + +d ar 1000 +go + +; check if programed stop because an error is detected +if not prop=01 goto assemble_ok1 + +echo +echo *** (assembling error code in AR) +echo + +ex ar +goto end + +:assemble_ok1 + +; check if programed stop because normal termination +if prop=70 if ar=1951 goto assemble_ok2 +goto end + +:assemble_ok2 + +det cdr1 +det cdp1 + +; create object program deck with +; - package cards +; - assembled program cards from phase III + +carddeck -q join fortransit/pack.dck deck_out.dck as deck_out.dck + +echo *** +echo *** Read Object Program Deck +echo *** + +; Load assembled deck into drum +; -l switch allows to load the symbolic info so debug cmd info will show +; soap source code read from card. + +set cdr1 wiring=8WORD +att cdr1 -l deck_out.dck + +d csw 7019519999 +d ar 8000 +go + +; attach input and output data deck + +det cdr1 + +if "%2" == "" goto run1 +att cdr1 -q %2 +set cdr1 wiring=fortransit +:run1 + +if "%3" != "" att cdp1 -n -q %3 +if "%3" == "" att cdp1 -n -q deck_out.dck +set cdp1 echo, print, wiring=fortransit + +; Now execute the loaded program object deck + +echo *** +echo *** Run Program +echo *** + +; set csw negative to activate conditional punch statement +; normal program termination will halt cpu at AR=9999 + +d csw -01 0000 9999 +d ar 1999 +go + +; clean up + +del deck_it_header.dck +del deck_it.dck +del deck_res.dck +del deck_soap.dck + +:end diff --git a/I650/sw/is_run.ini b/I650/sw/run_is.ini similarity index 89% rename from I650/sw/is_run.ini rename to I650/sw/run_is.ini index 7e1de297..dac2b32d 100644 --- a/I650/sw/is_run.ini +++ b/I650/sw/run_is.ini @@ -16,7 +16,7 @@ echo *** echo *** Load is main deck into drum echo *** -att cdr1 -q is.dck +att cdr1 -q bell/is.dck d csw 7019519999 d ar 8000 @@ -27,7 +27,7 @@ go carddeck -q join %1 as deck_in.dck if "%2" != "" carddeck -q join deck_in.dck %2 as deck_in.dck -att cdr1 deck_in.dck +att cdr1 -q deck_in.dck set cdr1 wiring=is att cdp1 -n -q deck_out_run.dck diff --git a/I650/sw/it_run.ini b/I650/sw/run_it.ini similarity index 78% rename from I650/sw/it_run.ini rename to I650/sw/run_it.ini index 18ec092c..3b654f0b 100644 --- a/I650/sw/it_run.ini +++ b/I650/sw/run_it.ini @@ -5,9 +5,9 @@ ; set cpu debug=cmd;data;detail -; params: %1 source progrma card deck to compile with it +; params: %1 source program card deck to compile with it ; %2 input program data card deck (if empty, do not attach input card) -; %3 output program data card deck (if empty, do not attach input card) +; %3 output program data card deck (if empty, attach deck_out.dck file) set cpu 2k att cdp0 -n -q print.txt @@ -23,7 +23,7 @@ echo *** echo *** Load IT compiler deck into drum echo *** -att cdr1 -q -l it_compiler.dck +att cdr1 -q -l it/it_compiler.dck d csw 70 1951 3000 d ar 8000 @@ -69,7 +69,7 @@ det cdr1 ; 2) package used reservation deck ; 3) rest of compilation output -carddeck -q join deck_res.dck it_reservation_p1.dck deck_soap.dck as deck_pit.dck +carddeck -q join deck_res.dck it/it_reservation_p1.dck deck_soap.dck as deck_pit.dck ; Load soap deck into drum (1 word per card format), but does not execute it @@ -78,7 +78,7 @@ echo *** echo *** Load soap deck into drum echo *** -att cdr1 -q -l soapII.dck +att cdr1 -q -l it/soapII.dck d csw 7019519999 d ar 8000 @@ -88,7 +88,7 @@ echo *** echo *** Apply IT modifications to soap deck echo *** -att cdr1 -q -l it_soapII_patch.dck +att cdr1 -q -l it/soapII_patch.dck d csw 7019519999 d ar 8000 @@ -101,7 +101,7 @@ echo *** echo *** Assemble PIT deck echo *** -att cdr1 deck_pit.dck +att cdr1 -q deck_pit.dck set cdr1 wiring=soap att cdp1 -n -q deck_out.dck @@ -119,7 +119,7 @@ go det cdr1 det cdp1 -carddeck -q join it_package_p1.dck deck_out.dck as deck_spit.dck +carddeck -q join it/it_package_p1.dck deck_out.dck as deck_spit.dck ; Load deck into drum (1 word per card format), but does not execute it @@ -132,7 +132,7 @@ echo *** ; soap source code read from card. set cdr1 wiring=8WORD -att cdr1 -l deck_spit.dck +att cdr1 -q -l deck_spit.dck d csw 7019519999 @@ -148,10 +148,9 @@ att cdr1 -q %2 set cdr1 wiring=it :run1 -if "%3" == "" goto run2 -att cdp1 -n -q %3 +if "%3" != "" att cdp1 -n -q %3 +if "%3" == "" att cdp1 -n -q deck_out.dck set cdp1 echo, print, wiring=it -:run2 ; Now execute the loaded deck diff --git a/I650/sw/soap_and_run.ini b/I650/sw/run_soap.ini similarity index 87% rename from I650/sw/soap_and_run.ini rename to I650/sw/run_soap.ini index fbdca49b..d0ae0fd1 100644 --- a/I650/sw/soap_and_run.ini +++ b/I650/sw/run_soap.ini @@ -7,13 +7,13 @@ ; params: %1 source card deck to assemble with soap ; %2 start address to run program (If empty, program not run) -; %3 input card deck (if empty, do not attach input card +; %3 input card deck (if empty, do not attach input card) set cpu 2k ; Load soap deck into drum (1 word per card format), but does not execute it -att cdr1 -q -l soapII.dck +att cdr1 -q -l soap/soapII.dck echo *** echo *** Load soap deck into drum @@ -25,7 +25,7 @@ go ; Now put source cards in reader and start soap assembler -att cdr1 %1 +att cdr1 -q %1 set cdr1 wiring=soap att cdp1 -n -q deck_out.dck @@ -47,7 +47,7 @@ if "%2" == "" goto end det cdp1 set cdr1 wiring=8WORD -att cdr1 -l deck_out.dck +att cdr1 -q -l deck_out.dck att cdp1 -n -q deck_out_run.dck set cdp1 echo, print, wiring=8WORD @@ -64,7 +64,7 @@ go ; attach input deck if "%3" == "" goto run -att cdr1 %3 +att cdr1 -q %3 ; Now execute the loaded deck :run diff --git a/I650/sw/soap/00_readme.txt b/I650/sw/soap/00_readme.txt new file mode 100644 index 00000000..8296a0fc --- /dev/null +++ b/I650/sw/soap/00_readme.txt @@ -0,0 +1,11 @@ + +Restoration comments May/2018 + +SOAP II +From Bitsavers Manual 24-4000-0_SOAPII.pdf + +It can assemble itself, but the generated code is not the same +as the one in the source code listing + +This is the result of a probable manual tuning/patch of +assembled code. \ No newline at end of file diff --git a/I650/sw/soap/soapII.dck b/I650/sw/soap/soapII.dck new file mode 100644 index 00000000..26acff42 --- /dev/null +++ b/I650/sw/soap/soapII.dck @@ -0,0 +1,1400 @@ +0?0000800? 0001 1 soap 2 +0?0000800? 0002 1 +0?0000800? 0003 1 symbolic optimal assembly prog +0?0000800? 0004 1 +0?0000800? 0005 1 for the +0?0000800? 0006 1 +0?0000800? 0007 1 ibm 650 +0?0000800? 0008 1 +0?0000800? 0009 1 data processing system +0?0000800? 0010 1 +0?0000800? 0011 regs0000 0399 symbol tab +0?0000800? 0012 rege0400 0599 equiv tabl +0?0000800? 0013 rega0600 0799 avail tabl +0?0000800? 0014 regn0800 0899 num op tab +0?0000800? 0015 blr 1000 1000 entry +0?0000800? 0016 blr 1001 1012 pseudo ent +0?0000800? 0017 blr 1021 1049 reg table +0?0000800? 0018 regc1050 1164 sym op tab +0?0000800? 0019 bla 1098 1099 +0?0000800? 0020 bla 1148 1149 +0?0000800? 0021 blr 1900 1900 manual pat +0?0000800? 0022 synreadc 1950 +0?0000800? 0023 blr 1951 1962 read area +0?0000800? 0024 regt1990 1992 type +0?0000800? 0025 regp1977 1986 punch area +0?0000800? 0026 blr 1998 1999 +0?0000800? 0027 equxxxx1 1961 +0?0000800? 0028 equxxxx2 1962 +0?0000800? 0029 blr 1563 1570 type2 +0?0000800? 0030 bla 1565 1565 +0?0000800? 0031 bla 1569 1569 +0?0000800? 0032 regb0900 0901 sub 2 +0?0000800? 0033 regh0902 0904 type 2 +0?0000800? 0034 regm0905 0907 +0?0000800? 0035 regq0908 0909 +0?0000800? 0036 regr1200 1207 sub 5 +0?0000800? 0037 regu1250 1259 sub 13 +0?0000800? 0038 regv0910 0912 equ syn +0?0000800? 0039 regx0913 0914 type 0 +0?0000800? 0040 regy0915 0916 equ syn +0?0000800? 0041 regz0917 0919 +0?0000800? 0042 regw0920 0922 +0?0000800? 0043 blr 0923 0968 multiple r +0?0000800? 0044 regi1300 1307 sub 13 +0?0000800? 0045 1 +0?0000800? 0046 1 control program +0?0000800? 0047 1 +6I1954195C 0048241000800?691950135C 1000lddreadc sub16 entry +0?0000800? 0049 1 +6I1954195C 0050241950800?701999199H readcrcd 1999 1998 read card +6I1954195C 0051241998800?691951135D 1998ldd 1951 transfer +6I1954195C 0052241354800?241977098? stdp0001 alphabetic +6I1954195C 0053240980800?691952135E ldd 1952 input +6I1954195C 0054241355800?241978098A stdp0002 to +6I1954195C 0055240981800?691953135F ldd 1953 output +6I1954195C 0056241356800?241979098B stdp0003 +6I1954195C 0057240982800?691954135G ldd 1954 +6I1954195C 0058241357800?241980098C stdp0004 +6I1954195C 0059240983800?691955120H ldd 1955 +6I1954195C 0060241208800?241981098D stdp0005 +6I1954195C 0061240984800?691956120I ldd 1956 +6I1954195C 0062241209800?241982098E stdp0006 +6I1954195C 0063240985800?651985098I ralp0009 step +6I1954195C 0064240989800?150992099G alo1ixxx card +6I1954195C 0065240997800?201985098H stlp0009 number +6I1954195C 0066240988800?601960101E rau 1960 store +6I1954195C 0067241015800?300002097A srt 0002 control +6I1954195C 0068240971800?211984098G stup0008 info +6I1954195C 0069240987800?100990099E auptorg +6I1954195C 0070240995800?201986800C stlp0010 8003 transfer +6I1954800? 0071248003800?000000999I 8003nop 0000 9999 to type +0?0000800? 0072 1 +6I1954195C 0073241350800?711977195? punchpchp0001 readc punch read +0?0000800? 0074 1 +6I1954195C 0075241400800?601950140E setccraureadc sub10 sudo exit +0?0000800? 0076 1 +6I1954195C 0077241900800?691950140C 1900lddreadc sub14 manual pat +6I1954195C 0078241990800?690993099F t0001lddx subr3 type 0 +0?0000800? 0079 1 +6I1954195C 0080240913800?691016096I x0001ldd procl 650 +6I1954195C 0081241016800?691019097B ldd procd command or +6I1954195C 0082241019800?691350145C lddpunch proci constants +0?0000800? 0083 1 +6I1954195C 0084240914800?000000800C x0002nop 0000 8003 pseudo op +0?0000800? 0085 1 +6I1954195C 0086241991800?601950140E t0002raureadc sub10 type 1 com +0?0000800? 0087 1 +6I1954195C 0088240993800?000000091C x 00 0000 x0001 +0?0000800? 0089 1 +0?0000800? 0090 1 relocate routine +0?0000800? 0091 1 +0?0000800? 0092 hedt +6I1954195C 0093241992800?691195099F t0003lddq subr3 process op +6I1954195C 0094240909800?000000101C q0002nop 0000 illop illegal op +6I1954195C 0095240908800?651951145E q0001ral 1951 is l fixed +6I1954195C 0096241455800?350002121A slt 0002 +6I1954195C 0097241211800?441165116F nzu rel +6I1954195C 0098241165800?601957126A rau 1957 fixed l +6I1954195C 0099241261800?111014116I sup2000i drum core +6I1954195C 0100241169800?461172097C bmi fc +6I1954195C 0101241172800?108001097I aup 8001 res fixed drum +6I1954195C 0102240973800?651957131A fc ral 1957 setl fixed core +6I1954195C 0103241450800?651961131A sr ralxxxx1 setl set l +6I1954195C 0104241311800?350004117A setl slt 0004 +6I1954195C 0105241171800?691984118G lddp0008 +6I1954195C 0106241187800?221984123G sdap0008 prod +6I1954195C 0107241166800?601957136A rel rau 1957 drum core +6I1954195C 0108241361800?111014121I sup2000i +6I1954195C 0109241219800?461222117C bmi rc +6I1954195C 0110241222800?100975117I aupddiff relocate +6I1954195C 0111241179800?461182118C bmi bl drum addr +6I1954195C 0112241182800?101014097I aup2000i res +6I1954195C 0113240979800?211961121D res stuxxxx1 +6I1954195C 0114241214800?691450150C lddsr sub2r reserve l +6I1954195C 0115241173800?651957141A rc ral 1957 relocate +6I1954195C 0116241411800?151264126I alocdiff core +6I1954195C 0117241269800?161272097G slo9060 +6I1954195C 0118240977800?461180118C bmi bl +6I1954195C 0119241180800?158001131A alo 8001 setl +6I1954195C 0120241183800?601237099A bl rauprod sub12 blank l +0?0000800? 0121 1 +0?0000800? 0122 regj0944 0944 d type 2 +0?0000800? 0123 regg0941 0941 +0?0000800? 0124 1 +6I1954195C 0125241237800?691190119C prod lddproi set d exit +6I1954195C 0126241193800?241196099I stdexitx +6I1954195C 0127240999800?601952140G rau 1952 what is d +6I1954195C 0128241407800?691210121C lddh subr4 +6I1954195C 0129240902800?651958126C h0001ral 1958 relocate +6I1954195C 0130241263800?161014131I slo2000i d or c +6I1954195C 0131241319800?461564156C bmi 1564 1563 +6I1954195C 0132240903800?300008122A h0002srt 0008 c d or f +6I1954195C 0133241221800?100974800C aup1500 8003 +6I1954195C 0134241563800?651264136I 1563ralcdiff cdd c +6I1954195C 0135241564800?650975136I 1564ralddiff cdd d +6I1954195C 0136241566800?651958094D 1566ral 1958 j0001 f +6I1954195C 0137241369800?151958094D cdd alo 1958 j0001 +6I1954195C 0138240904800?000000094C h0003nop 0000 g0003 symbolic +0?0000800? 0139 1 +0?0000800? 0140 regj0960 0960 i +0?0000800? 0141 regf0955 0955 +0?0000800? 0142 1 +6I1954195C 0143241190800?691350155C proi lddpunch set i exit +6I1954195C 0144241553800?241196109I stdexitx +6I1954195C 0145241099800?601953145G rau 1953 what is i +6I1954195C 0146241457800?691260121C lddm subr4 +6I1954195C 0147240905800?651959131C m0001ral 1959 relocate +6I1954195C 0148241313800?161014141I slo2000i d or c +6I1954195C 0149241419800?461568156G bmi 1568 1567 +6I1954195C 0150240906800?300008117E m0002srt 0008 c d or f +6I1954195C 0151241175800?100978800C aup1504 8003 +6I1954195C 0152241567800?651264146I 1567ralcdiff cdi c +6I1954195C 0153241568800?650975146I 1568ralddiff cdi d +6I1954195C 0154241570800?651959096? 1570ral 1959 j0001 f +6I1954195C 0155241469800?151959096? cdi alo 1959 j0001 +6I1954195C 0156240907800?000000095G m0003nop 0000 f0003 symbolic +0?0000800? 0157 1 +6I1954195C 0158241195800?000000090H q 00 0000 q0001 constants +6I1954195C 0159241272800?000000906? 9060 00 0000 9060 +6I1954195C 0160241210800?000000090B h 00 0000 h0001 +6I1954195C 0161240974800?000000150? 1500 00 0000 1500 +6I1954195C 0162241260800?000000090E m 00 0000 m0001 +6I1954195C 0163240978800?000000150D 1504 00 0000 1504 +6I1954195C 0164241961800?010000196A xxxx1 01 0000 xxxx1 eraseable +0?0000800? 0165 hed +0?0000800? 0166 1 +0?0000800? 0167 1 bop routine +0?0000800? 0168 1 +6I1954195C 0169241001800?691404135C 1001ldd sub16 initialize +6I1954195C 0170241404800?601950140E raureadc sub10 punch +0?0000800? 0171 1 +0?0000800? 0172 1 blr routine +0?0000800? 0173 1 +6I1954195C 0174241002800?651959136C 1002ral 1959 blr reserve +6I1954195C 0175241363800?161958141C blr slo 1958 fwa to +6I1954195C 0176241413800?108001127A aup 8001 lwa +6I1954195C 0177241271800?691400150C lddsetcc sub2r +0?0000800? 0178 1 +0?0000800? 0179 1 rbr routine +0?0000800? 0180 1 +6I1954195C 0181241012800?600975122I 1012rauddiff +6I1954195C 0182241229800?151959136C alo 1959 blr +0?0000800? 0183 1 +0?0000800? 0184 1 bla routine +0?0000800? 0185 1 +6I1954195C 0186241003800?691406130I 1003lddh8xxx set drum +6I1954195C 0187241309800?241212121E stddrumt tag to 8 +6I1954195C 0188241215800?651959146C ral 1959 unreserve +6I1954195C 0189241463800?161958151C slo 1958 fwa +6I1954195C 0190241513800?108001132A aup 8001 to +6I1954195C 0191241321800?691400160C lddsetcc sub2u lwa +0?0000800? 0192 1 +0?0000800? 0193 1 reg routine +0?0000800? 0194 1 +0?0000800? 0195 hedr +6I1954195C 0196241004800?651952150G 1004ral 1952 is +6I1954195C 0197241507800?300008122E srt 0008 region +6I1954195C 0198241225800?161178123C slo90xxx character +6I1954195C 0199241233800?460986100B bmi 1002 alphabetic +6I1954195C 0200240986800?151189124C alo29xxx +6I1954195C 0201241243800?461002119G bmi 1002 +6I1954195C 0202241197800?350004155G slt 0004 store +6I1954195C 0203241557800?151310126E alost region +6I1954195C 0204241265800?101958161C aup 1958 origin +6I1954195C 0205241613800?101216800B auph9xxx 8002 +6I1954800? 0206248002800?219999100B 8002stu 9999 1002 +0?0000800? 0207 1 +6I1954195C 0208241310800?211021100B st stu 1021 1002 constants +0?0000800? 0209 hed +0?0000800? 0210 1 +0?0000800? 0211 1 equ req and syn routine +0?0000800? 0212 1 +0?0000800? 0213 hedz +6I1954195C 0214241005800?691406135I 1005lddh8xxx both equ +6I1954195C 0215241006800?691216135I 1006lddh9xxx both syn +6I1954195C 0216241359800?241262131E both stdtag +6I1954195C 0217241315800?601953160G rau 1953 what is i +6I1954195C 0218241607800?691360121C lddz subr4 +6I1954195C 0219240917800?651959091E z0001ral 1959 y0001 absolute +6I1954195C 0220240918800?691371117D z0002lddy subr9 regional +6I1954195C 0221240915800?201519132B y0001stle td +6I1954195C 0222240916800?651986119A y0002ralp0010 bp reg error +6I1954195C 0223240919800?691372127E z0003lddw subr6 symbolic +6I1954195C 0224240920800?651223091E w0001ralequiv y0001 s defined +6I1954195C 0225240921800?651986119A w0002ralp0010 bp s undefind +6I1954195C 0226240922800?651986119A w0003ralp0010 bp s tab full +0?0000800? 0227 1 +6I1954195C 0228241322800?601952165G td rau 1952 head d +6I1954195C 0229241657800?691410166C ldd sub15 and equate +6I1954195C 0230241410800?691713127E lddv subr6 to e +6I1954195C 0231240912800?651986119A v0003ralp0010 bp s tab full +6I1954195C 0232240910800?151519127C v0001aloe sd +6I1954195C 0233240911800?151519127C v0002aloe sd +6I1954195C 0234241273800?690976127I sd lddtt subr7 +0?0000800? 0235 1 +6I1954195C 0236240976800?691262136E tt lddtag test tag +6I1954195C 0237241365800?901400097? bdosetcc +6I1954195C 0238240970800?601519132C raue reserve e +6I1954195C 0239241323800?691400150C lddsetcc sub2r +0?0000800? 0240 1 +6I1954195C 0241241011800?691406140I 1011lddh8xxx req +6I1954195C 0242241409800?241262141E stdtag routine +6I1954195C 0243241415800?651959176C ral 1959 is i +6I1954195C 0244241763800?161014156I slo2000i drum o cor +6I1954195C 0245241569800?461422137C bmid +6I1954195C 0246241373800?151264161I alocdiff cd +6I1954195C 0247241422800?150975161I d aloddiff cd +6I1954195C 0248241619800?151014091E cd alo2000i y0001 +0?0000800? 0249 1 +6I1954195C 0250241360800?000000091G z 00 0000 z0001 constants +6I1954195C 0251241371800?000089091E y 00 0089 y0001 +6I1954195C 0252241372800?000000092? w 00 0000 w0001 +6I1954195C 0253241713800?000000091? v 00 0000 v0001 +6I1954195C 0254241500800?008800000? 88 00 8800 0000 +0?0000800? 0255 1 +6I1954195C 0256241191800?151500150E bp alo88 by pass +6I1954195C 0257241505800?201986135? stlp0010 punch +0?0000800? 0258 1 +6I1954195C 0259241262800?010000126B tag 01 0000 tag eraseable +6I1954195C 0260241519800?010000151I e 01 0000 e +0?0000800? 0261 hed +0?0000800? 0262 1 +0?0000800? 0263 1 alf routine +0?0000800? 0264 1 +6I1954195C 0265241007800?691460096I 1007ldd procl proces loc +6I1954195C 0266241460800?691952155E ldd 1952 +6I1954195C 0267241555800?241983118F stdp0007 +6I1954195C 0268241186800?651953170G ral 1953 replace +6I1954195C 0269241707800?451350146A nzepunch blank i +6I1954195C 0270241461800?691314101G lddsoap2 by +6I1954195C 0271241017800?241979135? stdp0003 punch soap2 +6I1954195C 0272241314800?827661779B soap2alfsoap2 soap2 constant +0?0000800? 0273 1 +0?0000800? 0274 1 pat routine +0?0000800? 0275 1 +6I1954195C 0276241008800?601511140E 1008rau sub10 +6I1954195C 0277241511800?691950140C lddreadc sub14 +0?0000800? 0278 1 +0?0000800? 0279 1 hed routine +0?0000800? 0280 1 +6I1954195C 0281241009800?651952175G 1009ral 1952 store +6I1954195C 0282241757800?300008132E srt 0008 heading +6I1954195C 0283241325800?201329140? stl0000h setcc character +0?0000800? 0284 1 +0?0000800? 0285 1 rel routine +0?0000800? 0286 1 +0?0000800? 0287 hedm +6I1954195C 0288241010800?651952180G 1010ral 1952 set +6I1954195C 0289241807800?451510156A nze sdd drum +6I1954195C 0290241510800?651958156A ral 1958 sdd and +6I1954195C 0291241561800?200975122H sdd stlddiff core +6I1954195C 0292241228800?651953185G ral 1953 deltas +6I1954195C 0293241857800?451560161A nze scd +6I1954195C 0294241560800?651959161A ral 1959 scd +6I1954195C 0295241611800?201264140? scd stlcdiff setcc +0?0000800? 0296 1 +6I1954195C 0297240975800?010000097E ddiff 01 0000 ddiff eraseable +6I1954195C 0298241264800?010000126D cdiff 01 0000 cdiff +0?0000800? 0299 hed +0?0000800? 0300 1 +0?0000800? 0301 1 load availablity table +0?0000800? 0302 1 +0?0000800? 0303 hedl +6I1954195C 0304241999800?651951160E 1999ral 1951 calc +6I1954195C 0305241605800?300004146E srt 0004 loc +6I1954195C 0306241465800?350004137E slt 0004 w2 +6I1954195C 0307241375800?158002128C alo 8002 +6I1954195C 0308241283800?158002124A alo 8002 +6I1954195C 0309241241800?150994114I aloc1 +6I1954195C 0310241149800?101352800C aupc2 8003 +6I1954800? 0311248003800?699995800B 8003ldd 9995 8002 load +6I1954800? 0312248002800?249994124G 8002std 9994 tup table +6I1954195C 0313241247800?111550165E tup suptw +6I1954195C 0314241655800?441459195? nzu readc +6I1954195C 0315241459800?101312116G auptwp2 +6I1954195C 0316241167800?151020800C alo1dxxx 8003 +0?0000800? 0317 1 +6I1954195C 0318240994800?240600124G c1 stda0001 tup constants +6I1954195C 0319241352800?691952800B c2 ldd 1952 8002 +6I1954195C 0320241550800?691958800B tw ldd 1958 8002 +6I1954195C 0321241312800?691960800B twp2 ldd 1960 8002 +0?0000800? 0322 hed +0?0000800? 0323 1 optimizing table +0?0000800? 0324 1 +6I1954195C 0325240800800?000404099H n0001 00 0404 0998 nop +6I1954195C 0326240801800?000404099H n0002 00 0404 0998 hlt +6I1954195C 0327240802800?332322099I n0003 33 2322 0999 ufa +6I1954195C 0328240803800?000505099H n0004 00 0505 0998 rtc +6I1954195C 0329240804800?000505099H n0005 00 0505 0998 rtn +6I1954195C 0330240805800?000505099H n0006 00 0505 0998 rta +6I1954195C 0331240806800?000505099H n0007 00 0505 0998 wtn +6I1954195C 0332240807800?000505099H n0008 00 0505 0998 wta +6I1954195C 0333240808800?331212099I n0009 33 1212 0999 lib +6I1954195C 0334240809800?330202099I n0010 33 0202 0999 ldi +6I1954195C 0335240810800?330504099I n0011 33 0504 0999 aup +6I1954195C 0336240811800?330504099I n0012 33 0504 0999 sup +6I1954195C 0337240812800?999999999I n0013 99 9999 9999 not used +6I1954195C 0338240813800?999999999I n0014 99 9999 9999 not used +6I1954195C 0339240814800?331110099I n0015 33 1110 0999 div +6I1954195C 0340240815800?330504099I n0016 33 0504 0999 alo +6I1954195C 0341240816800?330504099I n0017 33 0504 0999 slo +6I1954195C 0342240817800?330504099I n0018 33 0504 0999 aml +6I1954195C 0343240818800?330504099I n0019 33 0504 0999 sml +6I1954195C 0344240819800?332120099I n0020 33 2120 0999 mpy +6I1954195C 0345240820800?540303099I n0021 54 0303 0999 stl +6I1954195C 0346240821800?450303099I n0022 45 0303 0999 stu +6I1954195C 0347240822800?340303099I n0023 34 0303 0999 sda +6I1954195C 0348240823800?340303099I n0024 34 0303 0999 sia +6I1954195C 0349240824800?330303099I n0025 33 0303 0999 std +6I1954195C 0350240825800?440505099H n0026 44 0505 0998 nts +6I1954195C 0351240826800?000505099H n0027 00 0505 0998 bin +6I1954195C 0352240827800?000505099H n0028 00 0505 0998 set +6I1954195C 0353240828800?331212099I n0029 33 1212 0999 sib +6I1954195C 0354240829800?330202099I n0030 33 0202 0999 sti +6I1954195C 0355240830800?000000098H n0031 00 0000 0988 srt +6I1954195C 0356240831800?000000088H n0032 00 0000 0888 srd +6I1954195C 0357240832800?332726099I n0033 33 2726 0999 fad +6I1954195C 0358240833800?332726099I n0034 33 2726 0999 fsb +6I1954195C 0359240834800?330000099I n0035 33 0000 0999 fdv +6I1954195C 0360240835800?000000098H n0036 00 0000 0988 slt +6I1954195C 0361240836800?000000098H n0037 00 0000 0988 sct +6I1954195C 0362240837800?332726099I n0038 33 2726 0999 fam +6I1954195C 0363240838800?332726099I n0039 33 2726 0999 fsm +6I1954195C 0364240839800?330000099I n0040 33 0000 0999 fmp +6I1954195C 0365240840800?330404099H n0041 33 0404 0998 nza +6I1954195C 0366240841800?330404099H n0042 33 0404 0998 bmz +6I1954195C 0367240842800?330404099H n0043 33 0404 0998 nzb +6I1954195C 0368240843800?330404099H n0044 33 0404 0998 bmb +6I1954195C 0369240844800?340405099H n0045 34 0405 0998 nzu +6I1954195C 0370240845800?430504099H n0046 43 0504 0998 nze +6I1954195C 0371240846800?330404099H n0047 33 0404 0998 bmi +6I1954195C 0372240847800?330505099H n0048 33 0505 0998 bov +6I1954195C 0373240848800?330404099H n0049 33 0404 0998 nzc +6I1954195C 0374240849800?330404099H n0050 33 0404 0998 bmc +6I1954195C 0375240850800?000000089H n0051 00 0000 0898 axa +6I1954195C 0376240851800?000000089H n0052 00 0000 0898 sxa +6I1954195C 0377240852800?000000089H n0053 00 0000 0898 axb +6I1954195C 0378240853800?000000089H n0054 00 0000 0898 sxb +6I1954195C 0379240854800?440505099H n0055 44 0505 0998 nef +6I1954195C 0380240855800?000505099H n0056 00 0505 0998 rwd +6I1954195C 0381240856800?000505099H n0057 00 0505 0998 wtm +6I1954195C 0382240857800?000505099H n0058 00 0505 0998 bst +6I1954195C 0383240858800?000000089H n0059 00 0000 0898 axc +6I1954195C 0384240859800?000000089H n0060 00 0000 0898 sxc +6I1954195C 0385240860800?330504099I n0061 33 0504 0999 rau +6I1954195C 0386240861800?330504099I n0062 33 0504 0999 rsu +6I1954195C 0387240862800?999999999I n0063 99 9999 9999 not used +6I1954195C 0388240863800?999999999I n0064 99 9999 9999 not used +6I1954195C 0389240864800?331110099I n0065 33 1110 0999 dvr +6I1954195C 0390240865800?330504099I n0066 33 0504 0999 ral +6I1954195C 0391240866800?330504099I n0067 33 0504 0999 rsl +6I1954195C 0392240867800?330504099I n0068 33 0504 0999 ram +6I1954195C 0393240868800?330504099I n0069 33 0504 0999 rsm +6I1954195C 0394240869800?330303099I n0070 33 0303 0999 ldd +6I1954195C 0395240870800?000000099I n0071 00 0000 0999 rd1 +6I1954195C 0396240871800?000000099I n0072 00 0000 0999 wr1 +6I1954195C 0397240872800?000000099I n0073 00 0000 0999 rc1 +6I1954195C 0398240873800?000000099I n0074 00 0000 0999 rd2 +6I1954195C 0399240874800?000000099I n0075 00 0000 0999 wr2 +6I1954195C 0400240875800?000000099I n0076 00 0000 0999 rc2 +6I1954195C 0401240876800?000000099I n0077 00 0000 0999 rd3 +6I1954195C 0402240877800?000000099I n0078 00 0000 0999 wr3 +6I1954195C 0403240878800?000000099I n0079 00 0000 0999 rc3 +6I1954195C 0404240879800?000505099I n0080 00 0505 0999 rpy +6I1954195C 0405240880800?000000089H n0081 00 0000 0898 raa +6I1954195C 0406240881800?000000089H n0082 00 0000 0898 rsa +6I1954195C 0407240882800?000000089H n0083 00 0000 0898 rab +6I1954195C 0408240883800?000000089H n0084 00 0000 0898 rsb +6I1954195C 0409240884800?330506099I n0085 33 0506 0999 tlu +6I1954195C 0410240885800?000606099H n0086 00 0606 0998 sds +6I1954195C 0411240886800?000606099H n0087 00 0606 0998 rds +6I1954195C 0412240887800?000606099H n0088 00 0606 0998 wds +6I1954195C 0413240888800?000000089H n0089 00 0000 0898 rac +6I1954195C 0414240889800?000000089H n0090 00 0000 0898 rsc +6I1954195C 0415240890800?440505099H n0091 44 0505 0998 bdo +6I1954195C 0416240891800?330505099H n0092 33 0505 0998 bd1 +6I1954195C 0417240892800?330505099H n0093 33 0505 0998 bd2 +6I1954195C 0418240893800?330505099H n0094 33 0505 0998 bd3 +6I1954195C 0419240894800?330505099H n0095 33 0505 0998 bd4 +6I1954195C 0420240895800?330505099H n0096 33 0505 0998 bd5 +6I1954195C 0421240896800?330505099H n0097 33 0505 0998 bd6 +6I1954195C 0422240897800?330505099H n0098 33 0505 0998 bd7 +6I1954195C 0423240898800?330505099H n0099 33 0505 0998 bd8 +6I1954195C 0424240899800?440505099H n0100 44 0505 0998 bd9 +0?0000800? 0425 1 +0?0000800? 0426 1 symbolic op table +0?0000800? 0427 1 +6I1954195C 0428241050800?617366100G c0001 61 7366 1007 alf +6I1954195C 0429241051800?617376001E c0002 61 7376 0015 alo +6I1954195C 0430241052800?617473001G c0003 61 7473 0017 aml +6I1954195C 0431241053800?618477001? c0004 61 8477 0010 aup +6I1954195C 0432241054800?618761005? c0005 61 8761 0050 axa +6I1954195C 0433241055800?618762005B c0006 61 8762 0052 axb +6I1954195C 0434241056800?618763005H c0007 61 8763 0058 axc +6I1954195C 0435241057800?626476009? c0008 62 6476 0090 bdo +6I1954195C 0436241058800?626491009A c0009 62 6491 0091 bd1 +6I1954195C 0437241059800?626492009B c0010 62 6492 0092 bd2 +6I1954195C 0438241060800?626493009C c0011 62 6493 0093 bd3 +6I1954195C 0439241061800?626494009D c0012 62 6494 0094 bd4 +6I1954195C 0440241062800?626495009E c0013 62 6495 0095 bd5 +6I1954195C 0441241063800?626496009F c0014 62 6496 0096 bd6 +6I1954195C 0442241064800?626497009G c0015 62 6497 0097 bd7 +6I1954195C 0443241065800?626498009H c0016 62 6498 0098 bd8 +6I1954195C 0444241066800?626499009I c0017 62 6499 0099 bd9 +6I1954195C 0445241067800?626975002F c0018 62 6975 0026 bin +6I1954195C 0446241068800?627361100C c0019 62 7361 1003 bla +6I1954195C 0447241069800?627379100B c0020 62 7379 1002 blr +6I1954195C 0448241070800?627461004A c0021 62 7461 0041 bma +6I1954195C 0449241071800?627462004C c0022 62 7462 0043 bmb +6I1954195C 0450241072800?627463004I c0023 62 7463 0049 bmc +6I1954195C 0451241073800?627469004F c0024 62 7469 0046 bmi +6I1954195C 0452241074800?627677100A c0025 62 7677 1001 bop +6I1954195C 0453241075800?627685004G c0026 62 7685 0047 bov +6I1954195C 0454241076800?628283005G c0027 62 8283 0057 bst +6I1954195C 0455241077800?646985001D c0028 64 6985 0014 div +6I1954195C 0456241078800?648579006D c0029 64 8579 0064 dvr +6I1954195C 0457241079800?657884100E c0030 65 7884 1005 equ +6I1954195C 0458241080800?666164003B c0031 66 6164 0032 fad +6I1954195C 0459241081800?666174003G c0032 66 6174 0037 fam +6I1954195C 0460241082800?666485003D c0033 66 6485 0034 fdv +6I1954195C 0461241083800?667477003I c0034 66 7477 0039 fmp +6I1954195C 0462241084800?668262003C c0035 66 8262 0033 fsb +6I1954195C 0463241085800?668274003H c0036 66 8274 0038 fsm +6I1954195C 0464241086800?686564100I c0037 68 6564 1009 hed +6I1954195C 0465241087800?687383000A c0038 68 7383 0001 hlt +6I1954195C 0466241088800?736464006I c0039 73 6464 0069 ldd +6I1954195C 0467241089800?736469000I c0040 73 6469 0009 ldi +6I1954195C 0468241090800?736962000H c0041 73 6962 0008 lib +6I1954195C 0469241091800?747788001I c0042 74 7788 0019 mpy +6I1954195C 0470241092800?756566005D c0043 75 6566 0054 nef +6I1954195C 0471241093800?757677000? c0044 75 7677 0000 nop +6I1954195C 0472241094800?758382002E c0045 75 8382 0025 nts +6I1954195C 0473241095800?758961004? c0046 75 8961 0040 nza +6I1954195C 0474241096800?758962004B c0047 75 8962 0042 nzb +6I1954195C 0475241097800?758963004H c0048 75 8963 0048 nzc +6I1954195C 0476241100800?758965004E c0051 75 8965 0045 nze +6I1954195C 0477241101800?758984004D c0052 75 8984 0044 nzu +6I1954195C 0478241102800?776183100H c0053 77 6183 1008 pat +6I1954195C 0479241103800?776368007A c0054 77 6368 0071 pch +6I1954195C 0480241104800?796161008? c0055 79 6161 0080 raa +6I1954195C 0481241105800?796162008B c0056 79 6162 0082 rab +6I1954195C 0482241106800?796163008H c0057 79 6163 0088 rac +6I1954195C 0483241107800?796173006E c0058 79 6173 0065 ral +6I1954195C 0484241108800?796174006G c0059 79 6174 0067 ram +6I1954195C 0485241109800?796184006? c0060 79 6184 0060 rau +6I1954195C 0486241110800?796279101B c0061 79 6279 1012 rbr +6I1954195C 0487241111800?796364007? c0062 79 6364 0070 rcd +6I1954195C 0488241112800?796391007B c0063 79 6391 0072 rc1 +6I1954195C 0489241113800?796392007E c0064 79 6392 0075 rc2 +6I1954195C 0490241114800?796393007H c0065 79 6393 0078 rc3 +6I1954195C 0491241115800?796482008F c0066 79 6482 0086 rds +6I1954195C 0492241116800?796491007? c0067 79 6491 0070 rd1 +6I1954195C 0493241117800?796492007C c0068 79 6492 0073 rd2 +6I1954195C 0494241118800?796493007F c0069 79 6493 0076 rd3 +6I1954195C 0495241119800?796567100D c0070 79 6567 1004 reg +6I1954195C 0496241120800?796573101? c0071 79 6573 1010 rel +6I1954195C 0497241121800?796578101A c0072 79 6578 1011 req +6I1954195C 0498241122800?797788007I c0073 79 7788 0079 rpy +6I1954195C 0499241123800?798261008A c0074 79 8261 0081 rsa +6I1954195C 0500241124800?798262008C c0075 79 8262 0083 rsb +6I1954195C 0501241125800?798263008I c0076 79 8263 0089 rsc +6I1954195C 0502241126800?798273006F c0077 79 8273 0066 rsl +6I1954195C 0503241127800?798274006H c0078 79 8274 0068 rsm +6I1954195C 0504241128800?798284006A c0079 79 8284 0061 rsu +6I1954195C 0505241129800?798361000E c0080 79 8361 0005 rta +6I1954195C 0506241130800?798363000C c0081 79 8363 0003 rtc +6I1954195C 0507241131800?798375000D c0082 79 8375 0004 rtn +6I1954195C 0508241132800?798664005E c0083 79 8664 0055 rwd +6I1954195C 0509241133800?826383003F c0084 82 6383 0036 sct +6I1954195C 0510241134800?826461002B c0085 82 6461 0022 sda +6I1954195C 0511241135800?826482008E c0086 82 6482 0085 sds +6I1954195C 0512241136800?826583002G c0087 82 6583 0027 set +6I1954195C 0513241137800?826961002C c0088 82 6961 0023 sia +6I1954195C 0514241138800?826962002H c0089 82 6962 0028 sib +6I1954195C 0515241139800?827376001F c0090 82 7376 0016 slo +6I1954195C 0516241140800?827383003E c0091 82 7383 0035 slt +6I1954195C 0517241141800?827473001H c0092 82 7473 0018 sml +6I1954195C 0518241142800?827964003A c0093 82 7964 0031 srd +6I1954195C 0519241143800?827983003? c0094 82 7983 0030 srt +6I1954195C 0520241144800?828364002D c0095 82 8364 0024 std +6I1954195C 0521241145800?828369002I c0096 82 8369 0029 sti +6I1954195C 0522241146800?828373002? c0097 82 8373 0020 stl +6I1954195C 0523241147800?828384002A c0098 82 8384 0021 stu +6I1954195C 0524241150800?828477001A c0101 82 8477 0011 sup +6I1954195C 0525241151800?828761005A c0102 82 8761 0051 sxa +6I1954195C 0526241152800?828762005C c0103 82 8762 0053 sxb +6I1954195C 0527241153800?828763005I c0104 82 8763 0059 sxc +6I1954195C 0528241154800?828875100F c0105 82 8875 1006 syn +6I1954195C 0529241155800?837384008D c0106 83 7384 0084 tlu +6I1954195C 0530241156800?846661000B c0107 84 6661 0002 ufa +6I1954195C 0531241157800?866482008G c0108 86 6482 0087 wds +6I1954195C 0532241158800?867991007A c0109 86 7991 0071 wr1 +6I1954195C 0533241159800?867992007D c0110 86 7992 0074 wr2 +6I1954195C 0534241160800?867993007G c0111 86 7993 0077 wr3 +6I1954195C 0535241161800?868361000G c0112 86 8361 0007 wta +6I1954195C 0536241162800?868374005F c0113 86 8374 0056 wtm +6I1954195C 0537241163800?868375000F c0114 86 8375 0006 wtn +6I1954195C 0538241164800?999999000A c0115 99 9999 0001 table end +0?0000800? 0539 1 +0?0000800? 0540 1 sub 1 store k in fwa to lwa +0?0000800? 0541 1 +0?0000800? 0542 hed1 +6I1954195C 0543241600800?241196119I subr1stdexitx store exit +6I1954195C 0544241199800?211961136D stuxxxx1 store k +6I1954195C 0545241364800?691217117? lddfwa set +6I1954195C 0546241170800?221217122? sdafwa fwa +6I1954195C 0547241220800?350004118A slt 0004 lwa +6I1954195C 0548241181800?221962151E sdaxxxx2 addresses +6I1954195C 0549241515800?601217142A raufwa +6I1954195C 0550241421800?151961800C aloxxxx1 8003 +6I1954800? 0551248003800?209999140B 8003stl 9999 next store k +6I1954195C 0552241402800?111962126G next supxxxx2 end of +6I1954195C 0553241267800?441471119F nzu exitx loop test +6I1954195C 0554241471800?108001137I aup 8001 +6I1954195C 0555241379800?101020800C aup1dxxx 8003 step +0?0000800? 0556 1 +6I1954195C 0557241217800?209998140B fwa stl 9998 next constants +6I1954195C 0558241962800?010000196B xxxx2 01 0000 xxxx2 eraseable +0?0000800? 0559 hed +0?0000800? 0560 1 +0?0000800? 0561 1 sub 2 reserve unreserve +0?0000800? 0562 1 +0?0000800? 0563 hed2 +6I1954195C 0564241503800?241813131F sub2rstdexity reserve +6I1954195C 0565241316800?691769147B lddz ru entry +6I1954195C 0566241603800?241813136F sub2ustdexity unreserve +6I1954195C 0567241366800?691565147B ldd1i ru entry +6I1954195C 0568241472800?241246129I ru stdw set w +6I1954195C 0569241299800?201653155F stln store n +6I1954195C 0570241556800?168001191C slo 8001 calc ao +6I1954195C 0571241913800?108003157A aup 8003 and po +6I1954195C 0572241571800?300003147I srt 0003 +6I1954195C 0573241479800?211284128G stux +6I1954195C 0574241287800?118001124E sup 8001 +6I1954195C 0575241245800?350001145A slt 0001 +6I1954195C 0576241451800?211606160I stup +6I1954195C 0577241609800?118001136G sup 8001 +6I1954195C 0578241367800?350002147C slt 0002 +6I1954195C 0579241473800?108003128A aup 8003 +6I1954195C 0580241281800?101284123I aupx +6I1954195C 0581241239800?151606171A alop +6I1954195C 0582241711800?350004162A slt 0004 +6I1954195C 0583241621800?151506176A aloc1 +6I1954195C 0584241761800?200901155D stlb0002 +6I1954195C 0585241554800?691188129A lddc2 +6I1954195C 0586241291800?221231133D sdaspr +6I1954195C 0587241334800?101337142C aupc3 su +6I1954195C 0588241423800?211401160D su stusa +6I1954195C 0589241604800?101558800C aupc4 8003 +6I1954800? 0590248003800?659992090A 8003ral 9992 b0002 +6I1954195C 0591240901800?350009152A b0002slt 0009 xx +6I1954195C 0592241521800?211176142I xx stuuh +6I1954195C 0593241429800?350001118E slt 0001 +6I1954195C 0594241185800?658002129C ral 8002 +6I1954195C 0595241293800?101246135A aupw +6I1954195C 0596241351800?300001190G srt 0001 +6I1954195C 0597241907800?101176123A aupuh spr +6I1954195C 0598241231800?300009140A spr srt 0009 sa +6I1954195C 0599241401800?209983090? sa stl 9983 b0001 +6I1954195C 0600240900800?651653130H b0001raln is n zero +6I1954195C 0601241308800?451362181C nze exity +6I1954195C 0602241362800?161565166I slo1i reduce n +6I1954195C 0603241669800?201653145F stln by 1 +6I1954195C 0604241456800?601401170E rausa is ai +6I1954195C 0605241705800?111358186C supa197 in last +6I1954195C 0606241863800?461266131G bmi tp block of +6I1954195C 0607241266800?101719142C aupa201 su 4 +0?0000800? 0608 1 +6I1954195C 0609241317800?651231123E tp ralspr is p 9 +6I1954195C 0610241235800?161188134C sloc2 +6I1954195C 0611241343800?451296129G nze zp +6I1954195C 0612241296800?151249170C aloc5 step p +6I1954195C 0613241703800?691506150I lddc1 +6I1954195C 0614241509800?220901145D sdab0002 +6I1954195C 0615241454800?201231118D stlspr +6I1954195C 0616241184800?601401175E rausa reduce ai +6I1954195C 0617241755800?111408142C supc6 su by 196 +0?0000800? 0618 1 +6I1954195C 0619241297800?691506155I zp lddc1 set p +6I1954195C 0620241559800?240901150D stdb0002 to zero +6I1954195C 0621241504800?691458166A lddc7 +6I1954195C 0622241661800?241231123D stdspr +6I1954195C 0623241234800?601401180E rausa reduce ai +6I1954195C 0624241805800?111508142C supc8 su by 195 +0?0000800? 0625 1 +6I1954195C 0626241506800?350000152A c1 slt 0000 xx constants +6I1954195C 0627241188800?300009140A c2 srt 0009 sa +6I1954195C 0628241337800?200600090? c3 stla0001 b0001 +6I1954195C 0629241558800?450000000A c4 45 0000 0001 +6I1954195C 0630241565800?000000000A 1i 00 0000 0001 +6I1954195C 0631241358800?200796090? a197 stla0197 b0001 +6I1954195C 0632241719800?200800090? a201 stla0201 b0001 +6I1954195C 0633241249800?300010140A c5 srt 0010 sa +6I1954195C 0634241408800?000196000? c6 00 0196 0000 +6I1954195C 0635241458800?300000140A c7 srt 0000 sa +6I1954195C 0636241508800?000195000? c8 00 0195 0000 +6I1954195C 0637241769800?000000000? z 00 0000 0000 +6I1954195C 0638241246800?010000124F w 01 0000 w eraseable +6I1954195C 0639241653800?010000165C n 01 0000 n +6I1954195C 0640240901800?010000090A b0002 01 0000 b0002 +6I1954195C 0641241231800?010000123A spr 01 0000 spr +6I1954195C 0642241401800?010000140A sa 01 0000 sa +6I1954195C 0643241176800?010000117F uh 01 0000 uh +6I1954195C 0644241284800?010000128D x 01 0000 x +0?0000800? 0645 hed +0?0000800? 0646 1 +0?0000800? 0647 1 sub 3 process op code +0?0000800? 0648 1 +0?0000800? 0649 hed3 +6I1954195C 0650240996800?241196134I subr3stdexitx store exit +6I1954195C 0651241349800?651954165I ral 1954 +6I1954195C 0652241659800?300004181I srt 0004 is op +6I1954195C 0653241819800?451522101C nze illop blank +6I1954195C 0654241522800?350006138G slt 0006 is op +6I1954195C 0655241387800?441341119B nzu num numeric +6I1954195C 0656241341800?300002134G srt 0002 +6I1954195C 0657241347800?201961141D stlxxxx1 search +6I1954195C 0658241414800?168001167A slo 8001 symbolic +6I1954195C 0659241671800?841050185E tluc0001 op table +6I1954195C 0660241855800?151608800B alo1 8002 +6I1954800? 0661248002800?659997150A 8002ral 9997 next is +6I1954195C 0662241501800?161961161E next sloxxxx1 sym op +6I1954195C 0663241615800?350006152I slt 0006 legal +6I1954195C 0664241529800?441013138D nzuillop +6I1954195C 0665241384800?350001139A slt 0001 test for +6I1954195C 0666241391800?441295134F nzupseu pseudo op +6I1954195C 0667241346800?350001175C slt 0001 sno store num +6I1954195C 0668241753800?201983123F sno stlp0007 650 op +6I1954195C 0669241236800?300004139G srt 0004 get optim +6I1954195C 0670241397800?151650800B alo3 8002 constants +6I1954800? 0671248002800?699996139I 8002ldd 9996 nex +6I1954195C 0672241399800?241452119F nex stdoptim exitx +0?0000800? 0673 1 +6I1954195C 0674241192800?161345144I num slo4 form +6I1954195C 0675241449800?350002190E slt 0002 numeric +6I1954195C 0676241905800?168002196C slo 8002 op +6I1954195C 0677241963800?300001186I srt 0001 code +6I1954195C 0678241869800?158001175C alo 8001 sno +0?0000800? 0679 1 +6I1954195C 0680241013800?651986144A illopralp0010 illegal op +6I1954195C 0681241441800?151194149I alo5 set 8 +6I1954195C 0682241499800?201986128I stlp0010 for blank +6I1954195C 0683241289800?691242139I ldd6 nex op +0?0000800? 0684 1 +6I1954195C 0685241295800?350003180C pseu slt 0003 pseudo +6I1954195C 0686241803800?151196155A aloexitx op +6I1954195C 0687241551800?150992800B alo1ixxx 8002 +0?0000800? 0688 1 +6I1954195C 0689241608800?650000150A 1 ral 0000 next constants +6I1954195C 0690241700800?100000000? 2 10 0000 0000 +6I1954195C 0691241650800?690800139I 3 lddn0001 nex +6I1954195C 0692241345800?909000000? 4 90 9000 0000 +6I1954195C 0693241194800?000000000H 5 00 0000 0008 +6I1954195C 0694241242800?550505099I 6 55 0505 0999 +0?0000800? 0695 hed +0?0000800? 0696 1 +0?0000800? 0697 1 sub 4 what is address +0?0000800? 0698 1 +0?0000800? 0699 hed4 +6I1954195C 0700241213800?241416191I subr4stdexitz store exit +6I1954195C 0701241919800?211961146D stuxxxx1 store addr +6I1954195C 0702241464800?300008133C srt 0008 is c5 +6I1954195C 0703241333800?441437141F nzu exitz blank +6I1954195C 0704241437800?211962166E stuxxxx2 save c5 +6I1954195C 0705241665800?608002152C rau 8002 are low 4 +6I1954195C 0706241523800?101178138C aup90xxx characters +6I1954195C 0707241383800?471286128F bovloop loop numeric +6I1954195C 0708241286800?101339139C loop auph1 +6I1954195C 0709241393800?471396099H bov sym +6I1954195C 0710241396800?350002185C slt 0002 +6I1954195C 0711241853800?441286165H nzuloop +6I1954195C 0712241658800?651962141G ralxxxx2 low 4 num +6I1954195C 0713241417800?161178143C slo90xxx is c5 +6I1954195C 0714241433800?461336099H bmi sym alphabetic +6I1954195C 0715241336800?151189144C alo29xxx +6I1954195C 0716241443800?460998144G bmisym +6I1954195C 0717241447800?650992149G ral1ixxx regional +6I1954195C 0718241497800?101961171E aupxxxx1 aex +6I1954195C 0719241715800?151416172A aex aloexitz +6I1954195C 0720241721800?168002800A slo 8002 8001 +6I1954195C 0721240998800?601961176E sym rauxxxx1 hed symbol +6I1954195C 0722241765800?691018166C ldd sub15 +6I1954195C 0723241018800?151771142E alo2ixxx step exit +6I1954195C 0724241425800?211230171E stuhsymb aex +6I1954195C 0725241339800?100000000? h1 10 0000 0000 +6I1954195C 0726241230800?010000123? hsymb 01 0000 hsymb eraseable +0?0000800? 0727 hed +0?0000800? 0728 1 +0?0000800? 0729 1 sub 5 test absolute address +0?0000800? 0730 1 +0?0000800? 0731 hed5 +6I1954195C 0732241750800?241416196I subr5stdexitz store exit +6I1954195C 0733241969800?201961151D stlxxxx1 store a +6I1954195C 0734241514800?350004147E slt 0004 +6I1954195C 0735241475800?168002148C slo 8002 +6I1954195C 0736241483800?841200165F tlur0001 tlu +6I1954195C 0737241656800?151709800B aloget 8002 range +6I1954800? 0738248002800?609972117G 8002rau 9972 x table +6I1954195C 0739241177800?350006149A x slt 0006 +6I1954195C 0740241491800?300006170F srt 0006 +6I1954195C 0741241706800?101416182A aupexitz +6I1954195C 0742241821800?151961181E aloxxxx1 +6I1954195C 0743241815800?118003800A sup 8003 8001 +6I1954195C 0744241709800?600000117G get rau 0000 x +6I1954195C 0745241200800?001999000? r0001 00 1999 0000 range +6I1954195C 0746241201800?007999000C r0002 00 7999 0003 table +6I1954195C 0747241202800?008003000A r0003 00 8003 0001 +6I1954195C 0748241203800?008004000C r0004 00 8004 0003 +6I1954195C 0749241204800?008007000A r0005 00 8007 0001 +6I1954195C 0750241205800?008999000C r0006 00 8999 0003 +6I1954195C 0751241206800?009059000B r0007 00 9059 0002 +6I1954195C 0752241207800?999999000C r0008 99 9999 0003 +0?0000800? 0753 hed +0?0000800? 0754 1 +0?0000800? 0755 1 sub 6 symbol test routine +0?0000800? 0756 1 +0?0000800? 0757 hed6 +6I1954195C 0758241275800?241416132? subr6stdexitz store exit +6I1954195C 0759241320800?211601165D stus store symb +6I1954195C 0760241654800?691758186A lddswof set switch +6I1954195C 0761241861800?241610176D stdsw off +6I1954195C 0762241764800?191517123H mpysc scramble +6I1954195C 0763241238800?658002154G ral 8002 symbol +6I1954195C 0764241547800?350003180F slt 0003 giving +6I1954195C 0765241806800?191759133? mpycf lo +6I1954195C 0766241330800?300001158G srt 0001 +6I1954195C 0767241587800?350004159G slt 0004 set +6I1954195C 0768241597800?151850185F alol1p1 test +6I1954195C 0769241856800?201865116H stllop1 word +6I1954195C 0770241168800?161020152E slo1dxxx +6I1954195C 0771241525800?201903148G stllo sli save lo +6I1954195C 0772241487800?201614800A sli stlli 8001 init li +6I1954800? 0773248001800?659990139E 8001ral 9990 a is cont of +6I1954195C 0774241395800?451098154I a nze und li zero +6I1954195C 0775241098800?161601175F slos is cont of +6I1954195C 0776241756800?451610181A nzesw def li symb +6I1954195C 0777241610800?651614127? sw ralli off is li +6I1954195C 0778241270800?161573122G off slolmax maximum +6I1954195C 0779241227800?451280133A nze max +6I1954195C 0780241280800?151533148G alolmp1 sli step li +6I1954195C 0781241800800?161903170H on slolo is li equa +6I1954195C 0782241708800?451412166D nze swsym to lo +6I1954195C 0783241412800?151865148G alolop1 sli step li +6I1954195C 0784241331800?691434153G max lddswon set +6I1954195C 0785241537800?241610171D stdsw switch on +6I1954195C 0786241714800?651467148G rall1 sli zero li +0?0000800? 0787 1 +6I1954195C 0788241549800?651416187A und ralexitz undefined +6I1954195C 0789241871800?150992164G alo1ixxx step +6I1954195C 0790241647800?201416137? stlexitz exit +6I1954195C 0791241370800?651614142? ralli +6I1954195C 0792241420800?161467192A slol1 +6I1954195C 0793241921800?201575127H stllsymb asu +0?0000800? 0794 1 +6I1954195C 0795241811800?651614147? def ralli defined +6I1954195C 0796241470800?691278138A lddasu subr8 get +6I1954195C 0797241278800?101601141F asu aups exitz equivalent +0?0000800? 0798 1 +6I1954195C 0799241664800?010111121H swsymhlt 0111 symof s tab full +6I1954195C 0800241218800?691971122D symoflddsymon set sw sym +6I1954195C 0801241224800?241664197A stdswsym symon on +6I1954195C 0802241971800?651416157B symonralexitz +6I1954195C 0803241572800?151771800B alo2ixxx 8002 +0?0000800? 0804 1 +6I1954195C 0805241758800?651614127? swof ralli off constants +6I1954195C 0806241434800?651614180? swon ralli on +6I1954195C 0807241517800?100100100A sc 10 0100 1001 +6I1954195C 0808241759800?000000000D cf 00 0000 0004 +6I1954195C 0809241467800?650000139E l1 ral 0000 a +6I1954195C 0810241850800?650001139E l1p1 ral 0001 a +6I1954195C 0811241573800?650399139E lmax rale0000 a +6I1954195C 0812241533800?650400139E lmp1 rale0001 a +6I1954195C 0813241601800?010000160A s 01 0000 s erasable +6I1954195C 0814241610800?010000161? sw 01 0000 sw +6I1954195C 0815241903800?010000190C lo 01 0000 lo +6I1954195C 0816241614800?010000161D li 01 0000 li +6I1954195C 0817241575800?010000157E lsymb 01 0000 lsymb +0?0000800? 0818 hed +0?0000800? 0819 1 +0?0000800? 0820 1 sub 7 store symbol and equiv +0?0000800? 0821 1 +0?0000800? 0822 hed7 +6I1954195C 0823241279800?241416152? subr7stdexitz store exit +6I1954195C 0824241520800?691623122F lddss +6I1954195C 0825241226800?221962800A sdaxxxx2 8001 store +6I1954800? 0826248001800?219988154A 8001stu 9988 a symbol +6I1954195C 0827241541800?118001159I a sup 8001 +6I1954195C 0828241599800?201961181D stlxxxx1 save e +6I1954195C 0829241814800?300004162E srt 0004 +6I1954195C 0830241625800?141771123B div2ixxx calculate +6I1954195C 0831241232800?350004149C slt 0004 location +6I1954195C 0832241493800?151446165A aloc1 of +6I1954195C 0833241651800?691704180H lddc2 e +6I1954195C 0834241808800?221911186D sdasel and +6I1954195C 0835241864800?691617162? lddc3 store +6I1954195C 0836241620800?221673127F sdaser +6I1954195C 0837241276800?201431148D stlobee +6I1954195C 0838241484800?168001159A slo 8001 +6I1954195C 0839241591800?151961143A aloxxxx1 obee +6I1954195C 0840241431800?699986138I obee ldd 9986 b +6I1954195C 0841241389800?441673124D b nzuser +6I1954195C 0842241244800?350004191A slt 0004 sel +6I1954195C 0843241623800?219987154A ss stu 9987 a constants +6I1954195C 0844241446800?690400138I c1 ldde0001 b +6I1954195C 0845241704800?229985141F c2 sda 9985 exitz +6I1954195C 0846241617800?239984141F c3 sia 9984 exitz +6I1954195C 0847241431800?010000143A obee 01 0000 obee erasable +6I1954195C 0848241911800?010000191A sel 01 0000 sel +6I1954195C 0849241673800?010000167C ser 01 0000 ser +0?0000800? 0850 hed +0?0000800? 0851 1 +0?0000800? 0852 1 sub 8 given sym loc get equiv +0?0000800? 0853 1 +0?0000800? 0854 hed8 +6I1954195C 0855241381800?241534163G subr8stdexit store exit +6I1954195C 0856241637800?698003129D ldd 8003 +6I1954195C 0857241294800?221575132H sdalsymb store l +6I1954195C 0858241328800?658001128E ral 8001 +6I1954195C 0859241285800?141288114H div2dxxx +6I1954195C 0860241148800?350004180I slt 0004 +6I1954195C 0861241809800?151462800B aloe1 8002 +6I1954800? 0862248002800?699975137H 8002ldd 9975 tr +6I1954195C 0863241378800?441481128B tr nzu lh +6I1954195C 0864241481800?678001143I ram 8001 lr get e rh +6I1954195C 0865241282800?678001148I lh ram 8001 get e lh +6I1954195C 0866241489800?300004143I srt 0004 lr +6I1954195C 0867241439800?698003149F lr ldd 8003 +6I1954195C 0868241496800?231223132F siaequiv +6I1954195C 0869241326800?651575153D rallsymb exit +6I1954195C 0870241462800?690400137H e1 ldde0001 tr constant +6I1954195C 0871241534800?010000153D exit 01 0000 exit eraseable +6I1954195C 0872241223800?010000122C equiv 01 0000 equiv +0?0000800? 0873 hed +0?0000800? 0874 1 +0?0000800? 0875 1 sub 9 calculate reg address +0?0000800? 0876 hed9 +6I1954195C 0877241174800?241416167? subr9stdexitz store exit +6I1954195C 0878241670800?300008153I srt 0008 +6I1954195C 0879241539800?658003169G ral 8003 +6I1954195C 0880241697800?350004185H slt 0004 +6I1954195C 0881241858800?151512800B aloc 8002 is +6I1954800? 0882248002800?659991144E 8002ral 9991 nex region +6I1954195C 0883241445800?901649170A nex bdoill defined +6I1954195C 0884241701800?350001190H slt 0001 +6I1954195C 0885241908800?658002166G ral 8002 +6I1954195C 0886241667800?300001172C srt 0001 +6I1954195C 0887241723800?691416172? lddexitz +6I1954195C 0888241720800?961773167E bd6 l +6I1954195C 0889241773800?951376142H bd5d i +6I1954195C 0890241675800?151957156B l alo 1957 all +6I1954195C 0891241376800?151958156B d alo 1958 all +6I1954195C 0892241428800?151959156B i alo 1959 all +6I1954195C 0893241562800?160992174G all slo1ixxx +6I1954195C 0894241747800?461649141F bmiill exitz +6I1954195C 0895241649800?651416162B ill ralexitz undefined +6I1954195C 0896241622800?150992800B alo1ixxx 8002 or illeg +0?0000800? 0897 1 +6I1954195C 0898241512800?650960144E c ral 0960 nex constant +0?0000800? 0899 hed +0?0000800? 0900 1 sub 10 set cc 8 and punch +0?0000800? 0901 1 +6I1954195C 0902241405800?151986164A sub10alop0010 +6I1954195C 0903241641800?151344169I alo84th +6I1954195C 0904241699800?201986158I stlp0010 +6I1954195C 0905241589800?711977800C pchp0001 8003 +0?0000800? 0906 1 +6I1954195C 0907241344800?000800000? 84th 00 0800 0000 constant +0?0000800? 0908 1 +0?0000800? 0909 1 sub 11 find and reserve best +0?0000800? 0910 1 +0?0000800? 0911 hed0 +6I1954195C 0912241801800?691212196E sub11ldddrumt test +6I1954195C 0913241965800?901770182? bdo sex drum tag +6I1954195C 0914241770800?201725147H stlexit is adr l +6I1954195C 0915241478800?961531163C bd6di +6I1954195C 0916241633800?658003174A ral 8003 ssw l +6I1954195C 0917241531800?691634178G di lddf d or i +6I1954195C 0918241787800?221961196D sdaxxxx1 sub13 find optim +6I1954195C 0919241851800?350004176B gda slt 0004 dynam adr +6I1954195C 0920241762800?158002167B alo 8002 +6I1954195C 0921241672800?158002174A alo 8002 ssw +6I1954195C 0922241741800?691444179G ssw lddoff set sw off +6I1954195C 0923241797800?241584183G stdsw +6I1954195C 0924241837800?151290149E aloa1p1 get table +6I1954195C 0925241495800?201915126H stlbp1 start addr +6I1954195C 0926241268800?161020177E slo1dxxx +6I1954195C 0927241775800?201804161B stlao sai save ao +6I1954195C 0928241612800?201687800A sai stlai 8001 +6I1954800? 0929248001800?609975157I 8001rau 9975 ta is locat +6I1954195C 0930241579800?441583158D ta nzuyes sw available +6I1954195C 0931241584800?601687169A sw rauai swof +6I1954195C 0932241691800?161394174I swof sloamax is ai max +6I1954195C 0933241749800?451502175D nze max +6I1954195C 0934241502800?151906161B aloamp1 sai step ai +6I1954195C 0935241751800?161804185I swon sloao is ai equa +6I1954195C 0936241859800?451662191D nze full to ao +6I1954195C 0937241662800?151915161B alobp1 sai step ai +6I1954195C 0938241754800?691909171B max lddon set sw on +6I1954195C 0939241712800?241584173G stdsw +6I1954195C 0940241737800?651240161B rala1 sai set ai to +0?0000800? 0941 1 +6I1954195C 0942241914800?010222131H full hlt 0222 drum paked +6I1954195C 0943241318800?691216187? lddh9xxx set drum +6I1954195C 0944241870800?241212146F stddrumt tag to 9 +6I1954195C 0945241466800?651725182? ralexit sex step exit +6I1954195C 0946241820800?150992800B sex alo1ixxx 8002 +0?0000800? 0947 1 +6I1954195C 0948241583800?360000166? yes sct 0000 reserve +6I1954195C 0949241660800?350001171G slt 0001 location +6I1954195C 0950241717800?300001182C srt 0001 found +6I1954195C 0951241823800?201962151F stlxxxx2 save p +6I1954195C 0952241516800?118003187C sup 8003 +6I1954195C 0953241873800?350004168C slt 0004 +6I1954195C 0954241683800?108001179A aup 8001 +6I1954195C 0955241791800?151494800B alosrp 8002 +6I1954800? 0956248002800?300009172B 8002srt 0009 sca nulify sct +6I1954195C 0957241722800?608003162I sca rau 8003 +6I1954195C 0958241629800?151687184A aloai +6I1954195C 0959241841800?691544184G lddst +6I1954195C 0960241847800?221901800A sdaeras 8001 +6I1954800? 0961248001800?219972182E 8001stu 9972 ca +6I1954195C 0962241825800?118001173C ca sup 8001 calculate +6I1954195C 0963241733800?161240154E sloa1 location +6I1954195C 0964241545800?300004171? srt 0004 found +6I1954195C 0965241710800?141616142F div4i +6I1954195C 0966241426800?191679155B mpy500 +6I1954195C 0967241552800?158003176? alo 8003 +6I1954195C 0968241760800?118001176G sup 8001 +6I1954195C 0969241767800?101962181G aupxxxx2 +6I1954195C 0970241817800?191920134? mpy50 +6I1954195C 0971241340800?158003189G alo 8003 +6I1954195C 0972241897800?118001172E sup 8001 exit +6I1954195C 0973241634800?000000185A f 00 0000 gda constants +6I1954195C 0974241444800?651687169A off ralai swof +6I1954195C 0975241290800?600601157I a1p1 raua0002 ta +6I1954195C 0976241394800?600799157I amax raua0200 ta +6I1954195C 0977241906800?600800157I amp1 raua0201 ta +6I1954195C 0978241909800?651687175A on ralai swon +6I1954195C 0979241240800?600600157I a1 raua0001 ta +6I1954195C 0980241494800?300000172B srp srt 0000 sca +6I1954195C 0981241544800?219999182E st stu 9999 ca +6I1954195C 0982241616800?000000000D 4i 00 0000 0004 +6I1954195C 0983241679800?000000050? 500 00 0000 0500 +6I1954195C 0984241920800?000000005? 50 00 0000 0050 +6I1954195C 0985241602800?658001181? fon ral 8001 stepx +6I1954195C 0986241804800?010000180D ao 01 0000 ao erasable +6I1954195C 0987241687800?010000168G ai 01 0000 ai +6I1954195C 0988241915800?010000191E bp1 01 0000 bp1 +6I1954195C 0989241725800?010000172E exit 01 0000 exit +0?0000800? 0990 hed +0?0000800? 0991 1 +0?0000800? 0992 1 sub 12 set blank l 8 +0?0000800? 0993 1 +6I1954195C 0994240991800?151986189A sub12alop0010 +6I1954195C 0995241891800?151594179I alo87th +6I1954195C 0996241799800?201986800C stlp0010 8003 +0?0000800? 0997 1 +6I1954195C 0998241594800?000000800? 87th 00 0000 8000 constant +0?0000800? 0999 1 +0?0000800? 1000 1 sub 13 cal optimum dynamic adr +0?0000800? 1001 1 +0?0000800? 1002 hedy +6I1954195C 1003241964800?241416197? sub13stdexitz store exit +6I1954195C 1004241970800?951923187E bd5 i d or i +6I1954195C 1005241923800?651452186? raloptim d +6I1954195C 1006241860800?350001186G slt 0001 +6I1954195C 1007241867800?168002192E slo 8002 +6I1954195C 1008241925800?350001158A slt 0001 +6I1954195C 1009241581800?158001163I alo 8001 +6I1954195C 1010241639800?300003194G srt 0003 seo +6I1954195C 1011241875800?651452191? i raloptim i +6I1954195C 1012241910800?921666171F bd2shop shift test +6I1954195C 1013241716800?931772182B bd3xas xas test +6I1954195C 1014241822800?350002194G slt 0002 seo +6I1954195C 1015241947800?201961176F seo stlxxxx1 save ev od +6I1954195C 1016241766800?651872127G ralopreg is base +6I1954195C 1017241277800?141771133B div2ixxx even or od +6I1954195C 1018241332800?608003168I rau 8003 +6I1954195C 1019241689800?151961181F aloxxxx1 +6I1954195C 1020241816800?441922197B nzu rb +6I1954195C 1021241922800?350002172I slt 0002 +6I1954195C 1022241729800?658002197B ral 8002 rb +6I1954195C 1023241972800?300008194A rb srt 0008 get base +6I1954195C 1024241941800?151872132G aloopreg plus delta +6I1954195C 1025241327800?141380139? div50 mod 50 +6I1954195C 1026241390800?658003141F ral 8003 exitz +0?0000800? 1027 1 +6I1954195C 1028241666800?651983188G shop ralp0007 tlu units +6I1954195C 1029241887800?300004199G srt 0004 digit of +6I1954195C 1030241997800?350009191G slt 0009 d address +6I1954195C 1031241917800?168002197E slo 8002 +6I1954195C 1032241975800?841250181B tluu0001 +6I1954195C 1033241812800?151866800B alogu 8002 +6I1954800? 1034248002800?659969197C 8002ral 9969 top +6I1954195C 1035241973800?350002177I top slt 0002 +6I1954195C 1036241779800?691452186B lddoptim is op srd +6I1954195C 1037241862800?931916194G bd3 seo +6I1954195C 1038241916800?350004194G slt 0004 seo srd +0?0000800? 1039 1 +6I1954195C 1040241772800?651983193G xas ralp0007 tlu +6I1954195C 1041241937800?300004119H srt 0004 d address +6I1954195C 1042241198800?350006196F slt 0006 +6I1954195C 1043241966800?168002147F slo 8002 +6I1954195C 1044241476800?841300191B tlui0001 +6I1954195C 1045241912800?151967800B alogxd 8002 +6I1954800? 1046248002800?659968127D 8002ral 9968 nxt +6I1954195C 1047241274800?350004194G nxt slt 0004 seo +0?0000800? 1048 1 +6I1954195C 1049241250800?002322252D u0001 00 2322 2524 shift +6I1954195C 1050241251800?100706070F u0002 10 0706 0706 optimizing +6I1954195C 1051241252800?200706090H u0003 20 0706 0908 table +6I1954195C 1052241253800?300908111? u0004 30 0908 1110 +6I1954195C 1053241254800?401110131B u0005 40 1110 1312 +6I1954195C 1054241255800?501312151D u0006 50 1312 1514 +6I1954195C 1055241256800?601514171F u0007 60 1514 1716 +6I1954195C 1056241257800?701716191H u0008 70 1716 1918 +6I1954195C 1057241258800?801918212? u0009 80 1918 2120 +6I1954195C 1058241259800?902120232B u0010 90 2120 2322 +0?0000800? 1059 1 +6I1954195C 1060241300800?199906060? i0001 19 9906 0600 x accum +6I1954195C 1061241301800?799907070? i0002 79 9907 0700 add sub +6I1954195C 1062241302800?800008080? i0003 80 0008 0800 table +6I1954195C 1063241303800?800106060? i0004 80 0106 0600 +6I1954195C 1064241304800?800209080? i0005 80 0209 0800 +6I1954195C 1065241305800?800308090? i0006 80 0308 0900 +6I1954195C 1066241306800?905908080? i0007 90 5908 0800 +6I1954195C 1067241307800?999909090? i0008 99 9909 0900 +0?0000800? 1068 1 +6I1954195C 1069241866800?650000197C gu ral 0000 top constants +6I1954195C 1070241967800?650000127D gxd ral 0000 nxt +6I1954195C 1071241380800?000000005? 50 00 0000 0050 +0?0000800? 1072 hed +0?0000800? 1073 1 +0?0000800? 1074 1 sub 14 punch avail table +0?0000800? 1075 1 +0?0000800? 1076 hedp +6I1954195C 1077241403800?241196184I sub14stdexitx store exit +6I1954195C 1078241849800?691652136H ldd85th set punch +6I1954195C 1079241368800?241986173I stdp0010 8 +6I1954195C 1080241739800?691292159E ldda1 init a1 +6I1954195C 1081241595800?241961141H stdxxxx1 +6I1954195C 1082241418800?651324182I ralrs1 loop init rs +6I1954195C 1083241829800?101382800A loop aupc1 8001 +6I1954800? 1084248001800?209999170B 8001stl 9999 next set locat +6I1954195C 1085241702800?111468137D next suptw1 +6I1954195C 1086241374800?441377152H nzu srs +6I1954195C 1087241377800?101430133E aupc2 +6I1954195C 1088241335800?151338800C aloc3 8003 +6I1954195C 1089241528800?201962151H srs stlxxxx2 save rs +6I1954195C 1090241518800?601424187I rauc4 +6I1954195C 1091241879800?151961800B aloxxxx1 8002 +6I1954800? 1092248002800?699998800C 8002ldd 9998 8003 store +6I1954800? 1093248003800?249997175B 8003std 9997 tp av table +6I1954195C 1094241752800?111618147D tp suptw2 +6I1954195C 1095241474800?441427157H nzu pun +6I1954195C 1096241427800?101480138E aupc5 +6I1954195C 1097241385800?151388800B aloc6 8002 +6I1954195C 1098241578800?711977147G pun pchp0001 +6I1954195C 1099241477800?161530143E sloaim is ai max +6I1954195C 1100241435800?451438119F nze exitx +6I1954195C 1101241438800?151342124H aloamp1 step ai +6I1954195C 1102241248800?201961166H stlxxxx1 +6I1954195C 1103241668800?651962171H ralxxxx2 +6I1954195C 1104241718800?161524182I sloc7 loop +0?0000800? 1105 1 +6I1954195C 1106241382800?201977170B c1 stlp0001 next constants +6I1954195C 1107241430800?201985170B c2 stlp0009 next +6I1954195C 1108241338800?000500050? c3 00 0500 0500 +6I1954195C 1109241424800?241978175B c4 stdp0002 tp +6I1954195C 1110241480800?241986175B c5 stdp0010 tp +6I1954195C 1111241388800?000001000? c6 00 0001 0000 +6I1954195C 1112241524800?001499149I c7 00 1499 1499 +6I1954195C 1113241468800?201983170B tw1 stlp0007 next +6I1954195C 1114241618800?241984175B tw2 stdp0008 tp +6I1954195C 1115241652800?000080000? 85th 00 0080 0000 +6I1954195C 1116241292800?690600800C a1 ldda0001 8003 +6I1954195C 1117241324800?000000045? rs1 00 0000 0450 +6I1954195C 1118241530800?690799800C aim ldda0200 8003 +6I1954195C 1119241342800?690800800C amp1 ldda0201 8003 +0?0000800? 1120 hed +0?0000800? 1121 1 +0?0000800? 1122 1 sub 15 heading routine +0?0000800? 1123 1 +0?0000800? 1124 hedh +6I1954195C 1125241663800?241813176H sub15stdexity save exit +6I1954195C 1126241768800?698003157D ldd 8003 is c1 +6I1954195C 1127241574800?350008154C slt 0008 blank +6I1954195C 1128241543800?441298134H nzudh +6I1954195C 1129241348800?608001181H rau 8001 head +6I1954195C 1130241818800?101329181C aup0000h exity +6I1954195C 1131241298800?608001181C dh rau 8001 exity dont head +0?0000800? 1132 hed +0?0000800? 1133 1 +0?0000800? 1134 1 sub 16 initialization +0?0000800? 1135 1 +6I1954195C 1136241353800?241813186H sub16stdexity store exit +6I1954195C 1137241868800?651624192I rali1 +6I1954195C 1138241929800?211985148H stup0009 zero card +6I1954195C 1139241488800?241329143B std0000h zero head +6I1954195C 1140241432800?691485160? ldd subr1 zero sym t +6I1954195C 1141241485800?651538159C rali2 make drum +6I1954195C 1142241593800?101546180B aupi3 available +6I1954195C 1143241802800?691918160? ldd subr1 +6I1954195C 1144241918800?691406196H lddh8xxx set drum +6I1954195C 1145241968800?241212167D stddrumt tag to 8 +6I1954195C 1146241674800?691527158? lddi4 set swsym +6I1954195C 1147241580800?241664172D stdswsym off +6I1954195C 1148241724800?651577163A rali5 undefine +6I1954195C 1149241631800?101406177D auph8xxx regions +6I1954195C 1150241774800?691813160? lddexity subr1 +0?0000800? 1151 1 +6I1954195C 1152241624800?000000059I i1 00s0001 e0200 constants +6I1954195C 1153241538800?000600079I i2 00a0001 a0200 +6I1954195C 1154241546800?111111111A i3 11 1111 1111 +6I1954195C 1155241527800?010111121H i4 01 0111 symof +6I1954195C 1156241577800?001021104I i5 00 1021 1049 +6I1954195C 1157241852800?961824187D pacofbd6findi findl +0?0000800? 1158 1 +0?0000800? 1159 1 sub 17 calc 800x equivalent +0?0000800? 1160 1 +0?0000800? 1161 hedx +6I1954195C 1162241902800?691924162G sb17dldddeq di d equiv +6I1954195C 1163241854800?691974162G sb17ilddieq di i equiv +6I1954195C 1164241627800?241961152F di stdxxxx1 save tag +6I1954195C 1165241526800?211813157F stuexity store exit +6I1954195C 1166241576800?201962162F stlxxxx2 store 800x +6I1954195C 1167241626800?691961196D lddxxxx1 sub13 get optim +6I1954195C 1168241904800?201961167F sda stlxxxx1 dynam addr +6I1954195C 1169241676800?141771148B div2ixxx is dy addr +6I1954195C 1170241482800?441535138F nzuod ev even or od +6I1954195C 1171241535800?651588164C od ral8002 eo +6I1954195C 1172241386800?651789164C ev ral8003 eo +6I1954195C 1173241643800?161962172F eo sloxxxx2 +6I1954195C 1174241726800?451630168A nze add1 +6I1954195C 1175241630800?651961181C ralxxxx1 exity +6I1954195C 1176241681800?651961177F add1 ralxxxx1 +6I1954195C 1177241776800?150992181C alo1ixxx exity +0?0000800? 1178 1 +6I1954195C 1179241924800?000008190D deq 00 0008 sda constants +6I1954195C 1180241974800?000009190D ieq 00 0009 sda +6I1954195C 1181241588800?000000800B 8002 00 0000 8002 +6I1954195C 1182241789800?000000800C 8003 00 0000 8003 +0?0000800? 1183 hed +0?0000800? 1184 1 +0?0000800? 1185 1 sub 18 index address +0?0000800? 1186 1 +0?0000800? 1187 hedw +6I1954195C 1188241826800?241813187F indexstdexity store exit +6I1954195C 1189241876800?201961192F stlxxxx1 store addr +6I1954195C 1190241926800?601954197F rau 1954 +6I1954195C 1191241976800?350007169C slt 0007 +6I1954195C 1192241693800?691813167G lddexity +6I1954195C 1193241677800?951680153B bd5d d or i +6I1954195C 1194241532800?350002168? slt 0002 d +6I1954195C 1195241680800?300009172G d srt 0009 +6I1954195C 1196241727800?191014168D mpy2000i +6I1954195C 1197241684800?691813177G lddexity +6I1954195C 1198241777800?961730158B bd6ds drum 0 cor +6I1954195C 1199241582800?300001173? srt 0001 ds core +6I1954195C 1200241730800?151961181C ds aloxxxx1 exity +0?0000800? 1201 1 +6I1954195C 1202241813800?010000181C exity 01 0000 exity erasabele +0?0000800? 1203 hed +0?0000800? 1204 1 +0?0000800? 1205 1 sub 19 process location +0?0000800? 1206 1 +0?0000800? 1207 regd0923 0923 proc l +0?0000800? 1208 regg0925 0925 +0?0000800? 1209 regj0928 0928 +0?0000800? 1210 regk0931 0931 +0?0000800? 1211 regl0933 0933 +0?0000800? 1212 1 +0?0000800? 1213 heda +6I1954195C 1214240969800?241196189I proclstdexitx store exit +6I1954195C 1215241899800?601951182G rau 1951 is l blank +6I1954195C 1216241827800?441731163B nzunb +6I1954195C 1217241632800?691212187G ldddrumt blank test +6I1954195C 1218241877800?901781092D bdob d0002 drum tag +6I1954195C 1219241781800?651872192G b ralopreg setl blank +6I1954195C 1220241927800?350004198G setl slt 0004 set l +6I1954195C 1221241987800?691984163H lddp0008 to dr +6I1954195C 1222241638800?221984119F sdap0008 exitx +6I1954195C 1223241731800?691734121C nb lddg subr4 what is l +6I1954195C 1224240925800?651957093A g0001ral 1957 k0001 absolute +6I1954195C 1225240926800?691780117D g0002lddk subr9 regional +6I1954195C 1226240927800?691830127E g0003lddj subr6 symbolic +6I1954195C 1227240931800?691784175? k0001lddl subr5 test range +6I1954195C 1228240932800?601585183I k0002rau87th x reg error +6I1954195C 1229241839800?101986139B x aupp0010 set blank +6I1954195C 1230241392800?211986192G stup0010 setl l8 +6I1954195C 1231240933800?201872192G l0001stlopreg setl drum addr +6I1954195C 1232240934800?101688174C l0002aup86th 800x 800x +6I1954195C 1233240935800?691738144B l0003lddorceq 89x core addr +6I1954195C 1234240936800?601585183I l0004rau87th x other +6I1954195C 1235241743800?691596144B 800x lddorxeq 89x +6I1954195C 1236241442800?241872183I 89x stdopreg x +6I1954195C 1237240928800?651223093A j0001ralequiv k0001 sym defind +6I1954195C 1238240929800?651682180A j0002rald sub11 sym undef +6I1954195C 1239240930800?601585183I j0003rau87th x s tab full +6I1954195C 1240240923800?201872162H d0001stlopreg ss s eq found +6I1954195C 1241240924800?601585183I d0002rau87th x drum paked +6I1954195C 1242241628800?101230163E ss auphsymb store +6I1954195C 1243241635800?151575188? alolsymb symbol +6I1954195C 1244241880800?691781127I lddb subr7 +0?0000800? 1245 1 +6I1954195C 1246241734800?000000092E g 00 0000 g0001 constants +6I1954195C 1247241780800?000090093A k 00 0090 k0001 +6I1954195C 1248241830800?000000092H j 00 0000 j0001 +6I1954195C 1249241784800?000000093C l 00 0000 l0001 +6I1954195C 1250241682800?000090092C d 00 0090 d0001 +6I1954195C 1251241688800?000008000? 86th 00 0008 0000 +6I1954195C 1252241585800?000000800? 87th 00 0000 8000 +6I1954195C 1253241196800?010000119F exitx 01 0000 exitx eraseable +0?0000800? 1254 hed +0?0000800? 1255 1 +0?0000800? 1256 1 sub 20 process data address +0?0000800? 1257 1 +0?0000800? 1258 regd0937 0937 proc d +0?0000800? 1259 regf0939 0939 +0?0000800? 1260 regg0941 0941 +0?0000800? 1261 regj0944 0944 +0?0000800? 1262 regk0946 0946 +0?0000800? 1263 regl0949 0949 +0?0000800? 1264 1 +0?0000800? 1265 hedb +6I1954195C 1266240972800?241196194I procdstdexitx store exit +6I1954195C 1267241949800?601952167H rau 1952 is d blank +6I1954195C 1268241678800?441831173B nzunb +6I1954195C 1269241732800?651685180A rald sub11 find +6I1954195C 1270240937800?201492095B d0001stlorbal l0004 optimum +6I1954195C 1271240938800?601542139H d0002rau88th x drum paked +6I1954195C 1272241728800?691452177H bt lddoptim is op +6I1954195C 1273241778800?911196178C bd1exitx a branch +6I1954195C 1274241783800?201872119F stlopreg exitx d to or +6I1954195C 1275241398800?101986159B x aupp0010 set blank +6I1954195C 1276241592800?211986119F stup0010 exitx +6I1954195C 1277241831800?691834121C nb lddg subr4 what is d +6I1954195C 1278240941800?651958094D g0001ral 1958 j0001 absolute +6I1954195C 1279240942800?691645117D g0002lddj subr9 regional +6I1954195C 1280240943800?691646127E g0003lddk subr6 symbolic +6I1954195C 1281240944800?691448175? j0001lddl subr5 test range +6I1954195C 1282240945800?601542139H j0002rau88th x reg error +6I1954195C 1283240949800?691828182F l0001lddaxd index drum addr +6I1954195C 1284240950800?350004187H l0002slt 0004 800x 800x +6I1954195C 1285240951800?691928182F l0003lddaxc index core addr +6I1954195C 1286240952800?350004193? l0004slt 0004 sd other +6I1954195C 1287241878800?691983143F 800x lddp0007 set 800x d +6I1954195C 1288241436800?221983148F sdap0007 +6I1954195C 1289241486800?300004149H srt 0004 +6I1954195C 1290241498800?101881190B aupxeq sb17d get 800x e +6I1954195C 1291241931800?350004164B scd slt 0004 set core d +6I1954195C 1292241642800?691983153F lddp0007 +6I1954195C 1293241536800?221983158F sdap0007 +6I1954195C 1294241586800?300004154H srt 0004 +6I1954195C 1295241548800?691782196D lddceq sub13 get core e +6I1954195C 1296241832800?201738172H sceq stlorceq bt save core +6I1954195C 1297240946800?651223094D k0001ralequiv j0001 sym defind +6I1954195C 1298240947800?651882180A k0002ralf sub11 sym undef +6I1954195C 1299240948800?601542139H k0003rau88th x s tab full +6I1954195C 1300240939800?201793169F f0001stleq ss save eq +6I1954195C 1301240940800?601542139H f0002rau88th x drum paked +6I1954195C 1302241696800?101230173E ss auphsymb store +6I1954195C 1303241735800?151575193B alolsymb symbol +6I1954195C 1304241932800?691785127I ldd subr7 +6I1954195C 1305241785800?651793095B raleq l0004 +6I1954195C 1306241930800?691983163F sd lddp0007 set d addr +6I1954195C 1307241636800?221983168F sdap0007 +6I1954195C 1308241686800?300004172H srt 0004 bt +6I1954195C 1309241685800?000088093G d 00 0088 d0001 constants +6I1954195C 1310241834800?000000094A g 00 0000 g0001 +6I1954195C 1311241645800?000088094D j 00 0088 j0001 +6I1954195C 1312241448800?000000094I l 00 0000 l0001 +6I1954195C 1313241882800?000088093I f 00 0088 f0001 +6I1954195C 1314241646800?000000094F k 00 0000 k0001 +6I1954195C 1315241828800?000088093G axd 00 0088 d0001 +6I1954195C 1316241928800?000098193A axc 00 0098 scd +6I1954195C 1317241881800?201596172H xeq stlorxeq bt +6I1954195C 1318241782800?000008183B ceq 00 0008 sceq +6I1954195C 1319241542800?000000080? 88th 00 0000 0800 +6I1954195C 1320241793800?010000179C eq 01 0000 eq erasable +0?0000800? 1321 hed +0?0000800? 1322 1 +0?0000800? 1323 1 sub 21 process instr address +0?0000800? 1324 1 +0?0000800? 1325 regd0953 0953 proc i +0?0000800? 1326 regf0955 0955 +0?0000800? 1327 regg0958 0958 +0?0000800? 1328 regj0960 0960 +0?0000800? 1329 regk0962 0962 +0?0000800? 1330 regl0965 0965 +0?0000800? 1331 1 +0?0000800? 1332 hedc +6I1954195C 1333241453800?241196183C procistdexitx store exit +6I1954195C 1334241833800?601953188C rau 1953 is i blank +6I1954195C 1335241883800?441788183H nzunb +6I1954195C 1336241838800?601952193C rau 1952 is d blank +6I1954195C 1337241933800?441888193H nzudnb +6I1954195C 1338241938800?691212188D ldddrumt d i blank +6I1954195C 1339241884800?901988095I bdo g0002 test drum +6I1954195C 1340241988800?651492096H ralorbal l0004 tag +6I1954195C 1341241888800?651692180A dnb rald sub11 find best +6I1954195C 1342240953800?201492096H d0001stlorbal l0004 found +6I1954195C 1343240954800?651986174B d0002ralp0010 x drum paked +6I1954195C 1344241742800?151695193D x alo89th +6I1954195C 1345241934800?201986119F stlp0010 exitx +6I1954195C 1346241788800?691792121C nb lddf subr4 what is i +6I1954195C 1347240955800?651959096? f0001ral 1959 j0001 absolute +6I1954195C 1348240956800?691835117D f0002lddj subr9 regional +6I1954195C 1349240957800?691885127E f0003lddk subr6 symbolic +6I1954195C 1350240960800?691935175? j0001lddl subr5 test range +6I1954195C 1351240961800?651986174B j0002ralp0010 x reg error +6I1954195C 1352240965800?691736182F l0001lddaxd index drum addr +6I1954195C 1353240966800?691983178F l0002lddp0007 800x 800x +6I1954195C 1354240967800?691836182F l0003lddaxc index core addr +6I1954195C 1355240968800?691983188F l0004lddp0007 other +6I1954195C 1356241886800?231983193F siap0007 mor +6I1954195C 1357241786800?231983188I 800x siap0007 +6I1954195C 1358241889800?101842185D aupxeq sb17i get 800x e +6I1954195C 1359241939800?691983198I 90xx lddp0007 set core +6I1954195C 1360241989800?231983144? siap0007 address +6I1954195C 1361241440800?691843196D lddceq sub13 get core e +6I1954195C 1362240962800?651223096? k0001ralequiv j0001 sym defind +6I1954195C 1363240963800?651490180A k0002ralg sub11 sym undef +6I1954195C 1364240964800?651986174B k0003ralp0010 x s tab full +6I1954195C 1365240958800?691983154? g0001lddp0007 si found best +6I1954195C 1366240959800?651986174B g0002ralp0010 x drum paked +6I1954195C 1367241540800?231983159? si siap0007 +6I1954195C 1368241590800?101230164? auphsymb store +6I1954195C 1369241640800?151575169? alolsymb symbol +6I1954195C 1370241690800?691936127I lddmor subr7 +6I1954195C 1371241936800?691492174E mor lddorbal set or +6I1954195C 1372241745800?241872119F stdopreg exitx to orb +6I1954195C 1373241740800?201738193F sceq stlorceq mor save core +0?0000800? 1374 1 +6I1954195C 1375241692800?000089095C d 00 0089 d0001 constants +6I1954195C 1376241792800?000000095E f 00 0000 f0001 +6I1954195C 1377241835800?000089096? j 00 0089 j0001 +6I1954195C 1378241885800?000000096B k 00 0000 k0001 +6I1954195C 1379241935800?000000096E l 00 0000 l0001 +6I1954195C 1380241490800?000089095H g 00 0089 g0001 +6I1954195C 1381241695800?000000008? 89th 00 0000 0080 +6I1954195C 1382241736800?000089096H axd 00 0089 l0004 +6I1954195C 1383241836800?000099193I axc 00 0099 90xx +6I1954195C 1384241842800?201596193F xeq stlorxeq mor +6I1954195C 1385241843800?000009174? ceq 00 0009 sceq +0?0000800? 1386 hed +0?0000800? 1387 1 +6I1954195C 1388240992800?000000000A 1ixxx 00 0000 0001 constants +6I1954195C 1389241020800?000001000? 1dxxx 00 0001 0000 +6I1954195C 1390241771800?000000000B 2ixxx 00 0000 0002 +6I1954195C 1391241288800?000002000? 2dxxx 00 0002 0000 +6I1954195C 1392241406800?800000000? h8xxx 80 0000 0000 +6I1954195C 1393241216800?900000000? h9xxx 90 0000 0000 +6I1954195C 1394241178800?000000009? 90xxx 00 0000 0090 +6I1954195C 1395241189800?000000002I 29xxx 00 0000 0029 +6I1954195C 1396241014800?000000200? 2000i 00 0000 2000 constant +6I1954195C 1397240990800?000000199? torg 00 0000 t0001 +0?0000800? 1398 1 +0?0000800? 1399 pat +0A0000100? 1400 diff --git a/I650/sw/soapII_condensed_card.dck b/I650/sw/soap/soapII_condensed_card.dck similarity index 100% rename from I650/sw/soapII_condensed_card.dck rename to I650/sw/soap/soapII_condensed_card.dck diff --git a/I650/sw/soap_example_1_src.txt b/I650/sw/soap/soap_example_1_src.txt similarity index 100% rename from I650/sw/soap_example_1_src.txt rename to I650/sw/soap/soap_example_1_src.txt diff --git a/I650/sw/soap_listing.txt b/I650/sw/soap/soap_listing.txt similarity index 100% rename from I650/sw/soap_listing.txt rename to I650/sw/soap/soap_listing.txt diff --git a/I650/sw/soap_src.txt b/I650/sw/soap/soap_src.txt similarity index 100% rename from I650/sw/soap_src.txt rename to I650/sw/soap/soap_src.txt diff --git a/doc/i650_doc.doc b/doc/i650_doc.doc index f5ce12ad49a1bf9eb04fce9bbd267228b30daeaf..1df56bee87d08041a5f7ec0c9db68f87b3286dd9 100644 GIT binary patch delta 70996 zcmc${2YeMp_wau=frJ2|CqO7(P&$MVNN55^dhZApAS5>h(nz6*a6u4hN?C9L1wrWu zC=scl2`VT>#h?fXD2kK>6ltRVzi0OD%}s#k`TczV@8`|>-JRW?nVmW3%$c%#apJka ziSvWz)PK^~X0tuz%})MG*=$b})(HOn&p-djrRJQsfR^wiw1U>q2DUa@S9qZ|&#Q9t z_Mh8qC2Yfn4;x-@TD@tKF8^QA;(@j%cf4$!FVq?)r0qBFSJeA^Eq6BKB(%28mhNS< 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