From 176540f639f0e240d10f6c4c3c8058a97825d560 Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Tue, 8 Sep 2015 11:17:52 -0700 Subject: [PATCH] PDP11, VAX: Correct MSCP & TMSCP register access debug output to mention correct register names and data being written on register writes --- PDP11/pdp11_rq.c | 4 ++-- PDP11/pdp11_tq.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/PDP11/pdp11_rq.c b/PDP11/pdp11_rq.c index 252b8853..fbf77d9b 100644 --- a/PDP11/pdp11_rq.c +++ b/PDP11/pdp11_rq.c @@ -1323,7 +1323,7 @@ int32 cidx = rq_map_pa ((uint32) PA); MSC *cp = rq_ctxmap[cidx]; DEVICE *dptr = rq_devmap[cidx]; -sim_debug(DBG_REG, dptr, "rq_rd(PA=0x%08X [%s], access=%d)\n", PA, ((PA >> 1) & 01) ? "IP" : "SA", access); +sim_debug(DBG_REG, dptr, "rq_rd(PA=0x%08X [%s], access=%d)=0x%04X\n", PA, ((PA >> 1) & 01) ? "SA" : "IP", access, ((PA >> 1) & 01) ? cp->sa : 0); if (cidx < 0) return SCPE_IERR; @@ -1356,7 +1356,7 @@ DEVICE *dptr = rq_devmap[cidx]; if (cidx < 0) return SCPE_IERR; -sim_debug(DBG_REG, dptr, "rq_wr(PA=0x%08X [%s], access=%d)\n", PA, ((PA >> 1) & 01) ? "IP" : "SA", access); +sim_debug(DBG_REG, dptr, "rq_wr(PA=0x%08X [%s], access=%d, data=0x%04X)\n", PA, ((PA >> 1) & 01) ? "SA" : "IP", access, data); switch ((PA >> 1) & 01) { /* decode PA<1> */ diff --git a/PDP11/pdp11_tq.c b/PDP11/pdp11_tq.c index 5724ef0e..d4b6e391 100644 --- a/PDP11/pdp11_tq.c +++ b/PDP11/pdp11_tq.c @@ -570,7 +570,7 @@ struct tq_req_results { /* intermediate State during tape motion comma t_stat tq_rd (int32 *data, int32 PA, int32 access) { -sim_debug(DBG_REG, &tq_dev, "tq_rd(PA=0x%08X [%s], access=%d)\n", PA, ((PA >> 1) & 01) ? "IP" : "SA", access); +sim_debug(DBG_REG, &tq_dev, "tq_rd(PA=0x%08X [%s], access=%d)=0x%04X\n", PA, ((PA >> 1) & 01) ? "SA" : "IP", access, ((PA >> 1) & 01) ? tq_sa : 0); switch ((PA >> 1) & 01) { /* decode PA<1> */ case 0: /* IP */ @@ -593,7 +593,7 @@ return SCPE_OK; t_stat tq_wr (int32 data, int32 PA, int32 access) { -sim_debug(DBG_REG, &tq_dev, "tq_wr(PA=0x%08X [%s], access=%d)\n", PA, ((PA >> 1) & 01) ? "IP" : "SA", access); +sim_debug(DBG_REG, &tq_dev, "tq_wr(PA=0x%08X [%s], access=%d, data=0x%04X)\n", PA, ((PA >> 1) & 01) ? "SA" : "IP", access, data); switch ((PA >> 1) & 01) { /* decode PA<1> */