mirror of
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Notes For V3.1-0
RESTRICTION: The FP15 and XVM features of the PDP-15 are only partially debugged. Do NOT enable these features for normal operations. 1. New Features in 3.1-0 1.1 SCP and libraries - Added simulated Ethernet support for VMS, FreeBSD, Mac OS/X. - Added status return to tmxr_putc_ln. - Added sim_putchar_s to handle possible output stalls. 1.2 All DECtapes - Added "DECtape off reel" error stop. 1.3 All Asynchronous Consoles - Added support for output congestion stall if using a Telnet connection. 1.4 PDP-1 - Added Type 23 parallel drum support. 1.5 PDP-8 - Added instruction history. - Added TSC8-75 option support for ETOS. - Added TD8E DECtape support. 1.6 PDP-18b - Added instruction history. - Changed PDP-9, PDP-15 API default to enabled. 1.7 PDP-11 - Added support for 18b only Qbus devices. - Formalized bus and addressing definitions. - Added control to enable/disable autoconfiguration. - Added stub support for second Unibus Ethernet controller. 1.7 Interdata 32b - Added instruction history. 1.8 Eclipse - Added floating point support. - Added programmable interval timer support. 1.9 H316 - Added DMA/DMC support. - Added fixed head disk support. - Added moving head disk support. - Added magtape support. 1.10 IBM 1130 (Brian Knittel) - Added support for physical card reader, using the Cardread interface (www.ibm1130.org/sim/downloads). - Added support for physical printer (flushes output buffer after each line). 2. Bugs Fixed in 3.1-0 2.1 SCP and libraries - Fixed numerous bugs in Ethernet library. 2.2 All DECtapes - Fixed reverse checksum value in 'read all' mode. - Simplified (and sped up) timing. 2.3 PDP-8 - Fixed bug in RX28 read status (found by Charles Dickman). - Fixed RX28 double density write. 2.4 PDP-18b - Fixed autoincrement bug in PDP-4, PDP-7, PDP-9. 2.5 PDP-11/VAX - Revised RQ MB->LBN conversion for greater accuracy. - Fixed bug in IO configuration (found by David Hittner). - Fixed bug with multiple RQ RAUSER drives. - Fixed bug in second Qbus Ethernet controller interrupts. 2.6 Nova/Eclipse - Fixed bugs in DKP flag clear, map setup, map usage (Charles Owen). - Fixed bug in MT, reset completes despite I/O reset (Charles Owen). - Fixed bug in MT, space operations return word count (Charles Owen). 2.7 IBM 1130 (Brian Knittel) - Fixed bug in setting carry bit in subtract and subtract double. - Fixed timing problem in console printer simulation. 2.8 1620 - Fixed bug in branch digit (found by Dave Babcock). 3. New Features in 3.0 vs prior releases 3.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support. 3.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 3.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 3.4 PDP-1 - Added block loader format support to LOAD. - Changed BOOT PTR to allow loading of all of the first bank of memory. - The LOAD command takes an optional argument specifying the memory field to be loaded. - The PTR BOOT command takes its starting memory field from the TA (address switch) register. 3.5 PDP-18b Family - Added PDP-4 EAE support. - Added PDP-15 FP15 support. - Added PDP-15 XVM support. - Added PDP-15 "re-entrancy ECO". - Added PDP-7, PDP-9, PDP-15 hardware RIM loader support in BOOT PTR. 4. Bugs Fixed in 3.0 vs prior releases 4.1 SCP and Libraries - Fixed end of file problem in dep, idep. - Fixed handling of trailing spaces in dep, idep. 4.2 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). - Fixed bug in user disk size (found by Chaskiel M Grundman). 4.3 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. - Revised fetch to model hardware more closely. - Fixed tape read end-of-record handling based on real 1401. - Added diagnostic read (space forward). 4.4 Nova - Fixed DSK variable size interaction with restore. - Fixed bug in DSK set size routine. 4.5 PDP-1 - Fixed DT variable size interaction with restore. - Updated CPU, line printer, standard devices to detect indefinite I/O wait. - Fixed incorrect logical, missing activate, break in drum simulator. - Fixed bugs in instruction decoding, overprinting for line printer. - Fixed system hang if continue after PTR error. - Fixed PTR to start/stop on successive rpa instructions. 4.6 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. - Fixed bug in user disk size (found by Chaskiel M Grundman). 4.7 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. - Fixed bug in PDP-4 line printer overprinting. - Fixed bug in PDP-15 memory protect/skip interaction. - Fixed bug in RF set size routine. - Increased PTP TIME for PDP-15 operating systems. - Fixed priorities in PDP-15 API (differs from PDP-9). - Fixed sign handling in PDP-15 EAE unsigned mul/div (differs from PDP-9). - Fixed bug in CAF, clears API subsystem. 4.8 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. - Fixed bug in DF, RF set size routine. 4.9 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. - Fixed DR drum sizes. - Fixed DR variable capacity interaction with SAVE/RESTORE. 4.10 GRI - Fixed bug in SC queue pointer management. 4.11 PDP-10 - Fixed bug in RP read header. 4.12 Ibm1130 - Fixed bugs found by APL 1130. 4.13 Altairz80 - Fixed bug in real-time clock on Windows host. 4.14 1620 - Fixed bug in immediate index add (found by Michael Short).
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
b2101ecdd4
commit
1da2d9452d
@@ -23,6 +23,9 @@
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu Interdata 16b CPU
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22-Sep-03 RMS Added additional instruction decode types
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07-Feb-03 RMS Fixed bug in SETM, SETMR (found by Mark Pizzolato)
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The register state for the Interdata 16b CPU is:
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@@ -266,7 +269,7 @@ const uint16 decrom[256] = {
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OP_NO | OP_816, /* FXR */
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OP_NO | OP_816, /* FLR */
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0, 0, 0, /* 30:32 */
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OP_RR | OP_816E | OP_PRV, /* LPSR */
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OP_NO | OP_816E | OP_PRV, /* LPSR */
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0, 0, 0, 0, /* 34:37 */
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OP_NO | OP_816 | OP_DPF, /* LDR */
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OP_NO | OP_816 | OP_DPF, /* CDR */
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@@ -328,8 +331,8 @@ const uint16 decrom[256] = {
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OP_NO | OP_716, /* SRLS */
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OP_NO | OP_716, /* SLLS */
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OP_NO, /* STBR */
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OP_NO, /* LDBR */
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OP_NO | OP_716, /* EXBR */
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OP_RR, /* LDBR */
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OP_RR | OP_716, /* EXBR */
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OP_NO | OP_716 | OP_PRV, /* EPSR */
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OP_RR | OP_PRV, /* WBR */
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OP_RR | OP_PRV, /* RBR */
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@@ -364,8 +367,8 @@ const uint16 decrom[256] = {
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OP_RX | OP_ID4, /* STM */
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OP_RX | OP_ID4, /* LM */
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OP_RX, /* STB */
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OP_RX, /* LDB */
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OP_RX | OP_716, /* CLB */
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OP_RXB, /* LDB */
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OP_RXB | OP_716, /* CLB */
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OP_RX | OP_ID4 | OP_PRV, /* AL */
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OP_RXH | OP_PRV, /* WB */
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OP_RXH | OP_PRV, /* RB */
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@@ -552,6 +555,7 @@ while (reason == 0) { /* loop until halted */
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uint32 dev, drom, inc, lim, opnd;
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uint32 op, r1, r1p1, r2, ea, oPC;
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uint32 rslt, t, map;
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uint32 ir1, ir2, ityp;
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int32 sr, st;
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if (sim_interval <= 0) { /* check clock queue */
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@@ -606,11 +610,13 @@ if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
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sim_interval = sim_interval - 1;
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t = ReadH (oPC = PC); /* fetch instr */
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op = (t >> 8) & 0xFF; /* isolate op, R1, R2 */
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r1 = (t >> 4) & 0xF;
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r2 = t & 0xF;
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ir1 = ReadH (oPC = PC); /* fetch instr */
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op = (ir1 >> 8) & 0xFF; /* isolate op, R1, R2 */
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r1 = (ir1 >> 4) & 0xF;
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r2 = ir1 & 0xF;
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drom = decrom[op];
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ityp = drom & OP_MASK;
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if ((drom == 0) || (drom & dec_flgs)) { /* not in model? */
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if (stop_inst) reason = STOP_RSRV; /* stop or */
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else cc = swap_psw (ILOPSW, cc); /* swap PSW */
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@@ -618,26 +624,41 @@ if ((drom == 0) || (drom & dec_flgs)) { /* not in model? */
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if ((drom & OP_PRV) && (PSW & PSW_PRO)) { /* priv & protected? */
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cc = swap_psw (ILOPSW, cc); /* swap PSW */
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continue; }
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switch (drom & OP_MASK) { /* decode instruction */
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switch (ityp) { /* decode instruction */
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case OP_NO: /* no operand */
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opnd = r2; /* assume short */
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break;
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case OP_RR: /* reg-reg */
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opnd = R[r2]; /* operand is R2 */
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break;
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case OP_RS: /* reg-storage */
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case OP_RX: /* reg-mem */
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PC = (PC + 2) & VAMASK; /* increment PC */
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ea = ReadH (PC); /* fetch address */
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if (r2) ea = (ea + R[r2]) & VAMASK; /* index calculation */
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ir2 = ea = ReadH (PC); /* fetch address */
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if (r2) ea = (ir2 + R[r2]) & VAMASK; /* index calculation */
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opnd = ea; /* operand is ea */
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break;
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case OP_RXH: /* reg-mem read */
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case OP_RXB: /* reg-mem byte */
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PC = (PC + 2) & VAMASK; /* increment PC */
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ea = ReadH (PC); /* fetch address */
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ir2 = ea = ReadH (PC); /* fetch address */
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if (r2) ea = (ea + R[r2]) & VAMASK; /* index calculation */
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opnd = ReadB (ea); /* fetch operand */
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break;
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case OP_RXH: /* reg-mem halfword */
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PC = (PC + 2) & VAMASK; /* increment PC */
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ir2 = ea = ReadH (PC); /* fetch address */
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if (r2) ea = (ea + R[r2]) & VAMASK; /* index calculation */
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opnd = ReadH (ea); /* fetch operand */
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break; }
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break;
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default:
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return SCPE_IERR; }
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PC = (PC + 2) & VAMASK; /* increment PC */
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switch (op) { /* case on opcode */
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@@ -672,11 +693,9 @@ case 0xD0: /* STM - RX */
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ea = (ea + 2) & VAMASK; } /* incr mem addr */
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break;
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case 0x93: /* LDBR - NO */
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R[r1] = R[r2] & DMASK8; /* load byte */
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break;
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case 0xD3: /* LDB - RX */
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R[r1] = ReadB (ea); /* load byte */
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case 0x93: /* LDBR - RR */
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case 0xD3: /* LDB - RXB */
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R[r1] = opnd & DMASK8; /* load byte */
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break;
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case 0x92: /* STBR - NO */
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@@ -686,8 +705,8 @@ case 0xD2: /* STB - RX */
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WriteB (ea, R[r1] & DMASK8); /* store byte */
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break;
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case 0x94: /* EXBR - NO */
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R[r1] = (R[r2] >> 8) | ((R[r2] & DMASK8) << 8);
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case 0x94: /* EXBR - RR */
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R[r1] = (opnd >> 8) | ((opnd & DMASK8) << 8);
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break;
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/* Control instructions */
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@@ -792,8 +811,7 @@ case 0xC5: /* CLHI - RS */
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if (((R[r1] ^ opnd) & (~opnd ^ rslt)) & SIGN16) cc = cc | CC_V;
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break;
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case 0xD4: /* CLB - RX */
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opnd = ReadB (ea); /* get operand */
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case 0xD4: /* CLB - RXB */
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t = R[r1] & DMASK8;
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rslt = (t - opnd) & DMASK16; /* result */
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CC_GL_16 (rslt); /* set G,L */
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@@ -1118,7 +1136,7 @@ case 0xC2: /* LPSW - RX */
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if (PSW & PSW_SQI) cc = testsysq (cc); /* test for q */
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break;
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case 0x95: /* EPSR - RR */
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case 0x95: /* EPSR - NO */
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R[r1] = BUILD_PSW (cc); /* save PSW */
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case 0x33: /* LPSR - NO */
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cc = newPSW (R[r2]); /* load new PSW */
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@@ -1,6 +1,6 @@
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/* id32_cpu.c: Interdata 32b CPU simulator
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Copyright (c) 2000-2003, Robert M. Supnik
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Copyright (c) 2000-2004, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -23,6 +23,12 @@
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu Interdata 32b CPU
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31-Dec-03 RMS Fixed bug in cpu_set_hist
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22-Sep-03 RMS Added additional instruction decode types
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Added instruction history
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The register state for an Interdata 32b CPU is:
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REG[0:F][2]<0:31> general register sets
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@@ -156,6 +162,18 @@
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#define UNIT_832 (1 << UNIT_V_832)
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#define UNIT_TYPE (UNIT_DPFP | UNIT_832)
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#define HIST_PC 0x40000000
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#define HIST_MIN 64
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#define HIST_MAX 65536
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struct InstHistory {
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uint32 pc;
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uint32 ir1;
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uint32 ir2;
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uint32 ir3;
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uint32 r1;
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uint32 ea;
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uint32 opnd; };
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#define SEXT32(x) (((x) & SIGN32)? ((int32) ((x) | ~0x7FFFFFFF)): \
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((int32) ((x) & 0x7FFFFFFF)))
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#define SEXT16(x) (((x) & SIGN16)? ((int32) ((x) | ~0x7FFF)): \
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@@ -202,6 +220,9 @@ uint32 dec_flgs = 0; /* decode flags */
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uint32 fp_in_hwre = 0; /* ucode vs hwre fp */
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uint32 pawidth = PAWIDTH32; /* addr mask */
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uint32 cpu_log = 0; /* debug logging */
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uint32 hst_p = 0; /* history pointer */
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uint32 hst_lnt = 0; /* history length */
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struct InstHistory *hst = NULL; /* instruction history */
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jmp_buf save_env; /* abort handler */
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struct BlockIO blk_io; /* block I/O status */
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uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
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@@ -229,6 +250,8 @@ t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_consint (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
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void set_r_display (uint32 *rbase);
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extern t_bool devtab_init (void);
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@@ -329,8 +352,8 @@ const uint16 decrom[256] = {
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OP_RXF, /* S */
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OP_RXF, /* M */
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OP_RXF, /* D */
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OP_RX, /* CRC12 */
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OP_RX, /* CRC16 */
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OP_RXH, /* CRC12 */
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OP_RXH, /* CRC16 */
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OP_RX, /* STE */
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OP_RXH, /* AHM */
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0, /* PB - 8/32C */
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@@ -349,7 +372,7 @@ const uint16 decrom[256] = {
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OP_RX | OP_DPF, /* STD */
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OP_RX, /* SME */
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OP_RX, /* LME */
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OP_RX, /* LHL */
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OP_RXH, /* LHL */
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OP_RX, /* TBT */
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OP_RX, /* SBT */
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OP_RX, /* RBT */
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@@ -367,8 +390,8 @@ const uint16 decrom[256] = {
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OP_NO, /* SRHLS */
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OP_NO, /* SLHLS */
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OP_NO, /* STBR */
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OP_NO, /* LDBR */
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OP_NO, /* EXBR */
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OP_RR, /* LDBR */
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OP_RR, /* EXBR */
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OP_NO | OP_PRV, /* EPSR */
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OP_RR | OP_PRV, /* WBR */
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OP_RR | OP_PRV, /* RBR */
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@@ -403,8 +426,8 @@ const uint16 decrom[256] = {
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OP_RX, /* STM */
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OP_RX, /* LM */
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OP_RX, /* STB */
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OP_RX, /* LDB */
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OP_RX, /* CLB */
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OP_RXB, /* LDB */
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OP_RXB, /* CLB */
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OP_RX | OP_PRV, /* AL */
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OP_RXF | OP_PRV, /* WB */
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OP_RXF | OP_PRV, /* RB */
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@@ -419,7 +442,7 @@ const uint16 decrom[256] = {
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OP_RXH, /* TS */
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OP_RX, /* SVC */
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OP_RI1 | OP_PRV, /* SINT */
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OP_RX | OP_PRV, /* SCP */
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OP_RXH | OP_PRV, /* SCP */
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0, 0, /* E4:E5 */
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OP_RX, /* LA */
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OP_RXF, /* TLATE */
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@@ -534,6 +557,8 @@ MTAB cpu_mod[] = {
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{ UNIT_TYPE, UNIT_DPFP | UNIT_832, "8/32", "832", NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
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&cpu_set_consint, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "HISTORY", "HISTORY",
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&cpu_set_hist, &cpu_show_hist },
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{ 0 } };
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DEVICE cpu_dev = {
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@@ -586,6 +611,7 @@ uint32 dev, drom, opnd, inc, lim, bufa;
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uint32 op, r1, r1p1, r2, rx2, ea;
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uint32 mpy, mpc, dvr;
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uint32 i, rslt, rlo, t;
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uint32 ir1, ir2, ir3, ityp;
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int32 sr, st;
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if (sim_interval <= 0) { /* check clock queue */
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@@ -644,11 +670,13 @@ if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
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sim_interval = sim_interval - 1;
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t = ReadH (oPC = PC, VE); /* fetch instr */
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op = (t >> 8) & 0xFF; /* extract op,R1,R2 */
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r1 = (t >> 4) & 0xF;
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r2 = t & 0xF;
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ir1 = ReadH (oPC = PC, VE); /* fetch instr */
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op = (ir1 >> 8) & 0xFF; /* extract op,R1,R2 */
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r1 = (ir1 >> 4) & 0xF;
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r2 = ir1 & 0xF;
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drom = decrom[op]; /* get decode flags */
|
||||
ityp = drom & OP_MASK; /* instruction type */
|
||||
|
||||
if ((drom == 0) || (drom & dec_flgs)) { /* not in model? */
|
||||
if (stop_inst) reason = STOP_RSRV; /* stop or */
|
||||
else cc = exception (ILOPSW, cc, 0); /* exception */
|
||||
@@ -657,55 +685,70 @@ if ((drom & OP_PRV) && (PSW & PSW_PRO)) { /* priv & protected? */
|
||||
cc = exception (ILOPSW, cc, 0); /* exception */
|
||||
continue; }
|
||||
|
||||
switch (drom & OP_MASK) { /* decode instruction */
|
||||
switch (ityp) { /* decode instruction */
|
||||
case OP_NO: /* no operand */
|
||||
opnd = r2; /* assume short */
|
||||
PC = (PC + 2) & VAMASK; /* increment PC */
|
||||
break;
|
||||
|
||||
case OP_RR: /* reg-reg */
|
||||
ea = opnd = R[r2]; /* operand is R2 */
|
||||
opnd = R[r2]; /* ea/operand is R2 */
|
||||
PC = (PC + 2) & VAMASK; /* increment PC */
|
||||
break;
|
||||
|
||||
case OP_RI1: /* reg-imm 1 */
|
||||
t = ReadH ((PC + 2) & VAMASK, VE); /* fetch immed */
|
||||
opnd = SEXT16 (t); /* sign extend */
|
||||
ir2 = ReadH ((PC + 2) & VAMASK, VE); /* fetch immed */
|
||||
opnd = SEXT16 (ir2); /* sign extend */
|
||||
if (r2) opnd = (opnd + R[r2]) & DMASK32; /* index calculation */
|
||||
PC = (PC + 4) & VAMASK; /* increment PC */
|
||||
break;
|
||||
|
||||
case OP_RI2: /* reg-imm 2 */
|
||||
t = ReadH ((PC + 2) & VAMASK, VE); /* fetch imm hi */
|
||||
opnd = t << 16; /* shift to place */
|
||||
t = ReadH ((PC + 4) & VAMASK, VE); /* fetch imm lo */
|
||||
opnd = opnd | t; /* complete imm */
|
||||
ir2 = ReadH ((PC + 2) & VAMASK, VE); /* fetch imm hi */
|
||||
ir3 = ReadH ((PC + 4) & VAMASK, VE); /* fetch imm lo */
|
||||
opnd = (ir2 << 16) | ir3; /* 32b immediate */
|
||||
if (r2) opnd = (opnd + R[r2]) & DMASK32; /* index calculation */
|
||||
PC = (PC + 6) & VAMASK; /* increment PC */
|
||||
break;
|
||||
case OP_RX: case OP_RXH: case OP_RXF: /* reg-mem */
|
||||
t = ReadH ((PC + 2) & VAMASK, VE); /* fetch addr */
|
||||
if ((t & 0xC000) == 0) { /* displacement? */
|
||||
|
||||
case OP_RX: case OP_RXB: case OP_RXH: case OP_RXF: /* reg-mem */
|
||||
ir2 = ReadH ((PC + 2) & VAMASK, VE); /* fetch addr */
|
||||
if ((ir2 & 0xC000) == 0) { /* displacement? */
|
||||
PC = (PC + 4) & VAMASK; /* increment PC */
|
||||
ea = t; } /* abs 14b displ */
|
||||
else if (t & 0x8000) { /* relative? */
|
||||
ea = ir2; } /* abs 14b displ */
|
||||
else if (ir2 & 0x8000) { /* relative? */
|
||||
PC = (PC + 4) & VAMASK; /* increment PC */
|
||||
ea = PC + SEXT15 (t); } /* add to incr PC */
|
||||
ea = PC + SEXT15 (ir2); } /* add to incr PC */
|
||||
else { /* absolute */
|
||||
rx2 = (t >> 8) & 0xF; /* get second index */
|
||||
ea = (t & 0xFF) << 16; /* shift to place */
|
||||
t = ReadH ((PC + 4) & VAMASK, VE); /* fetch addr lo */
|
||||
ea = ea | t; /* finish addr */
|
||||
rx2 = (ir2 >> 8) & 0xF; /* get second index */
|
||||
ea = (ir2 & 0xFF) << 16; /* shift to place */
|
||||
ir3 = ReadH ((PC + 4) & VAMASK, VE); /* fetch addr lo */
|
||||
ea = ea | ir3; /* finish addr */
|
||||
if (rx2) ea = ea + R[rx2]; /* index calc 2 */
|
||||
PC = (PC + 6) & VAMASK; } /* increment PC */
|
||||
if (r2) ea = ea + R[r2]; /* index calculation */
|
||||
ea = ea & VAMASK;
|
||||
if ((drom & OP_MASK) == OP_RXF) /* get fw operand? */
|
||||
opnd = ReadF (ea, VR); /* read fullword */
|
||||
else if ((drom & OP_MASK) == OP_RXH) { /* get hw operand? */
|
||||
if (ityp == OP_RXF) opnd = ReadF (ea, VR); /* get fw operand? */
|
||||
else if (ityp == OP_RXH) { /* get hw operand? */
|
||||
t = ReadH (ea, VR); /* read halfword */
|
||||
opnd = SEXT16 (t); } /* sign extend */
|
||||
else opnd = ea; /* for sloppy code */
|
||||
else if (ityp == OP_RXB) opnd = ReadB (ea, VR); /* get byte opnd? */
|
||||
else opnd = ea; /* just address */
|
||||
break;
|
||||
case OP_UNDEF:
|
||||
|
||||
default:
|
||||
return SCPE_IERR; }
|
||||
|
||||
if (hst_lnt) { /* instruction history? */
|
||||
hst[hst_p].pc = oPC | HIST_PC; /* save decode state */
|
||||
hst[hst_p].ir1 = ir1;
|
||||
hst[hst_p].ir2 = ir2;
|
||||
hst[hst_p].ir3 = ir3;
|
||||
hst[hst_p].r1 = R[r1];
|
||||
hst[hst_p].ea = ea;
|
||||
hst[hst_p].opnd = opnd;
|
||||
hst_p = hst_p + 1;
|
||||
if (hst_p >= hst_lnt) hst_p = 0; }
|
||||
if (qevent & EV_MAC) continue; /* MAC abort on fetch? */
|
||||
switch (op) { /* case on opcode */
|
||||
|
||||
@@ -721,8 +764,8 @@ case 0xF8: /* LI - RI2 */
|
||||
CC_GL_32 (R[r1]); /* set G,L */
|
||||
break;
|
||||
|
||||
case 0x73: /* LHL - RX */
|
||||
R[r1] = ReadH (ea, VR); /* get op, zero ext */
|
||||
case 0x73: /* LHL - RXH */
|
||||
R[r1] = opnd & DMASK16; /* get op, zero ext */
|
||||
CC_GL_32 (R[r1]); /* set G, L */
|
||||
break;
|
||||
|
||||
@@ -764,11 +807,9 @@ case 0xE0: /* TS - RXH */
|
||||
WriteH (ea, opnd | SIGN16, VW); /* set MSB */
|
||||
break;
|
||||
|
||||
case 0x93: /* LDBR - NO */
|
||||
R[r1] = R[r2] & DMASK8; /* load byte */
|
||||
break;
|
||||
case 0xD3: /* LDB - RX */
|
||||
R[r1] = ReadB (ea, VR); /* load byte */
|
||||
case 0x93: /* LDBR - RR */
|
||||
case 0xD3: /* LDB - RXB */
|
||||
R[r1] = opnd & DMASK8; /* load byte */
|
||||
break;
|
||||
|
||||
case 0x92: /* STBR - NO */
|
||||
@@ -778,13 +819,13 @@ case 0xD2: /* STB - RX */
|
||||
WriteB (ea, R[r1], VW); /* store byte */
|
||||
break;
|
||||
|
||||
case 0x34: /* EXHR - NO */
|
||||
R[r1] = ((R[r2] >> 16) & DMASK16) | ((R[r2] & DMASK16) << 16);
|
||||
case 0x34: /* EXHR - RR */
|
||||
R[r1] = ((opnd >> 16) & DMASK16) | ((opnd & DMASK16) << 16);
|
||||
break;
|
||||
|
||||
case 0x94: /* EXBR - NO */
|
||||
case 0x94: /* EXBR - RR */
|
||||
R[r1] = (R[r1] & ~DMASK16) |
|
||||
((R[r2] >> 8) & DMASK8) | ((R[r2] & DMASK8) << 8);
|
||||
((opnd >> 8) & DMASK8) | ((opnd & DMASK8) << 8);
|
||||
break;
|
||||
|
||||
/* Control instructions */
|
||||
@@ -793,14 +834,14 @@ case 0x01: /* BALR - RR */
|
||||
case 0x41: /* BAL - RX */
|
||||
PCQ_ENTRY; /* save old PC */
|
||||
R[r1] = PC; /* save cur PC */
|
||||
PC = ea; /* branch */
|
||||
PC = opnd; /* branch */
|
||||
break;
|
||||
|
||||
case 0x02: /* BTCR - RR */
|
||||
case 0x42: /* BTC - RX */
|
||||
if (cc & r1) { /* test CC's */
|
||||
PCQ_ENTRY; /* branch if true */
|
||||
PC = ea; }
|
||||
PC = opnd; }
|
||||
break;
|
||||
|
||||
case 0x20: /* BTBS - NO */
|
||||
@@ -819,7 +860,7 @@ case 0x03: /* BFCR - RR */
|
||||
case 0x43: /* BFC - RX */
|
||||
if ((cc & r1) == 0) { /* test CC's */
|
||||
PCQ_ENTRY; /* branch if false */
|
||||
PC = ea; }
|
||||
PC = opnd; }
|
||||
break;
|
||||
|
||||
case 0x22: /* BFBS - NO */
|
||||
@@ -840,16 +881,16 @@ case 0xC0: /* BXH - RX */
|
||||
R[r1] = (R[r1] + inc) & DMASK32; /* R1 = R1 + inc */
|
||||
if (R[r1] > lim) { /* if R1 > lim */
|
||||
PCQ_ENTRY; /* branch */
|
||||
PC = ea; }
|
||||
PC = opnd; }
|
||||
break;
|
||||
|
||||
case 0xC1: /* BXLE - RS */
|
||||
case 0xC1: /* BXLE - RX */
|
||||
inc = R[(r1 + 1) & 0xF]; /* inc = R1 + 1 */
|
||||
lim = R[(r1 + 2) & 0xF]; /* lim = R1 + 2 */
|
||||
R[r1] = (R[r1] + inc) & DMASK32; /* R1 = R1 + inc */
|
||||
if (R[r1] <= lim) { /* if R1 <= lim */
|
||||
PCQ_ENTRY; /* branch */
|
||||
PC = ea; }
|
||||
PC = opnd; }
|
||||
break;
|
||||
|
||||
/* Logical instructions */
|
||||
@@ -898,8 +939,7 @@ case 0xF5: /* CI - RI2 */
|
||||
if (((R[r1] ^ opnd) & (~opnd ^ rslt)) & SIGN32) cc = cc | CC_V;
|
||||
break;
|
||||
|
||||
case 0xD4: /* CLB - RX */
|
||||
opnd = ReadB (ea, VR); /* get operand */
|
||||
case 0xD4: /* CLB - RXB */
|
||||
t = R[r1] & DMASK8;
|
||||
rslt = (t - opnd) & DMASK16; /* result */
|
||||
CC_GL_16 (rslt); /* set G,L 16b */
|
||||
@@ -1278,8 +1318,8 @@ case 0xE2: /* SINT - RI1 */
|
||||
int_eval ();
|
||||
break;
|
||||
|
||||
case 0xE3: /* SCP - RX */
|
||||
opnd = ReadH (ea, VR); /* zero ext operand */
|
||||
case 0xE3: /* SCP - RXH */
|
||||
opnd = opnd & DMASK16; /* zero ext operand */
|
||||
if (opnd & CCW32_B1) t = ea + CCB32_B1C; /* point to buf */
|
||||
else t = ea + CCB32_B0C;
|
||||
sr = ReadH (t & VAMASK, VR); /* get count */
|
||||
@@ -1335,7 +1375,7 @@ case 0x67: /* RBL - RX */
|
||||
break;
|
||||
|
||||
case 0x5E: /* CRC12 - RXH */
|
||||
opnd = ReadH (ea, VR); /* zero ext opnd */
|
||||
opnd = opnd & DMASK16; /* zero ext opnd */
|
||||
t = (R[r1] & 0x3F) ^ opnd;
|
||||
for (i = 0; i < 6; i++) {
|
||||
if (t & 1) t = (t >> 1) ^ 0x0F01;
|
||||
@@ -1344,7 +1384,7 @@ case 0x5E: /* CRC12 - RXH */
|
||||
break;
|
||||
|
||||
case 0x5F: /* CRC16 - RXH */
|
||||
opnd = ReadH (ea, VR); /* zero ext opnd */
|
||||
opnd = opnd & DMASK16; /* zero ext opnd */
|
||||
t = (R[r1] & 0xFF) ^ opnd;
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (t & 1) t = (t >> 1) ^ 0xA001;
|
||||
@@ -1417,7 +1457,7 @@ case 0xDB: /* RD - RX */
|
||||
break;
|
||||
|
||||
case 0x99: /* RHR - RR */
|
||||
case 0xD9: /* RH - RS */
|
||||
case 0xD9: /* RH - RX */
|
||||
dev = R[r1] & DEV_MAX;
|
||||
if (DEV_ACC (dev)) { /* dev exist? */
|
||||
if (dev_tab[dev] (dev, IO_ADR, 0)) /* select, hw ok? */
|
||||
@@ -1436,7 +1476,7 @@ case 0xD9: /* RH - RS */
|
||||
break;
|
||||
|
||||
case 0x9D: /* SSR - RR */
|
||||
case 0xDD: /* SS - RS */
|
||||
case 0xDD: /* SS - RX */
|
||||
dev = R[r1] & DEV_MAX;
|
||||
if (DEV_ACC (dev)) { /* dev exist? */
|
||||
dev_tab[dev] (dev, IO_ADR, 0); /* select */
|
||||
@@ -2026,3 +2066,61 @@ t_stat cpu_set_consint (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
if (PSW & PSW_EXI) SET_INT (v_DS);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Set history */
|
||||
|
||||
t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
uint32 i, lnt;
|
||||
t_stat r;
|
||||
|
||||
if (cptr == NULL) {
|
||||
for (i = 0; i < hst_lnt; i++) hst[i].pc = 0;
|
||||
hst_p = 0;
|
||||
return SCPE_OK; }
|
||||
lnt = (uint32) get_uint (cptr, 10, HIST_MAX, &r);
|
||||
if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) return SCPE_ARG;
|
||||
hst_p = 0;
|
||||
if (hst_lnt) {
|
||||
free (hst);
|
||||
hst_lnt = 0;
|
||||
hst = NULL; }
|
||||
if (lnt) {
|
||||
hst = calloc (sizeof (struct InstHistory), lnt);
|
||||
if (hst == NULL) return SCPE_MEM;
|
||||
hst_lnt = lnt; }
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show history */
|
||||
|
||||
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
uint32 op, k, di;
|
||||
t_value sim_eval[6];
|
||||
struct InstHistory *h;
|
||||
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
|
||||
UNIT *uptr, int32 sw);
|
||||
|
||||
if (hst_lnt == 0) return SCPE_NOFNC; /* enabled? */
|
||||
fprintf (st, "PC r1 operand ea IR\n\n");
|
||||
di = hst_p; /* work forward */
|
||||
for (k = 0; k < hst_lnt; k++) { /* print specified */
|
||||
h = &hst[(di++) % hst_lnt]; /* entry pointer */
|
||||
if (h->pc & HIST_PC) { /* instruction? */
|
||||
fprintf (st, "%06X %08X %08X ", h->pc & VAMASK32, h->r1, h->opnd);
|
||||
sim_eval[0] = op = (h->ir1 >> 8) & 0xFF;
|
||||
sim_eval[1] = h->ir1 & 0xFF;
|
||||
sim_eval[2] = (h->ir2 >> 8) & 0xFF;
|
||||
sim_eval[3] = h->ir2 & 0xFF;
|
||||
sim_eval[4] = (h->ir3 >> 8) & 0xFF;
|
||||
sim_eval[5] = h->ir3 & 0xFF;
|
||||
if (OP_TYPE (op) >= OP_RX) fprintf (st, "%06X ", h->ea);
|
||||
else fprintf (st, " ");
|
||||
if ((fprint_sym (st, h->pc & VAMASK32, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
|
||||
fprintf (st, "(undefined) %04X", h->ir1);
|
||||
fputc ('\n', st); /* end line */
|
||||
} /* end if instruction */
|
||||
} /* end for */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -26,6 +26,7 @@
|
||||
The author gratefully acknowledges the help of Carl Friend and Al Kossow,
|
||||
who provided key documents about the Interdata product line.
|
||||
|
||||
22-Sep-03 RMS Added additional instruction decode types
|
||||
21-Jun-03 RMS Changed subroutine argument for ARM compiler conflict
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
28-Feb-03 RMS Changed magtape device default to 0x85
|
||||
@@ -188,9 +189,10 @@ struct BlockIO {
|
||||
#define OP_RS 0x0003 /* 16b: reg-storage */
|
||||
#define OP_RI1 0x0003 /* 32b: reg-imm 16b */
|
||||
#define OP_RX 0x0004 /* all: reg-mem */
|
||||
#define OP_RXH 0x0005 /* all: reg-mem, rd HW */
|
||||
#define OP_RXF 0x0006 /* 32b: reg-mem, rd FW */
|
||||
#define OP_RI2 0x0007 /* 32b: reg-imm 32b */
|
||||
#define OP_RXB 0x0005 /* all: reg-mem, rd BY */
|
||||
#define OP_RXH 0x0006 /* all: reg-mem, rd HW */
|
||||
#define OP_RXF 0x0007 /* 32b: reg-mem, rd FW */
|
||||
#define OP_RI2 0x0008 /* 32b: reg-imm 32b */
|
||||
#define OP_MASK 0x000F
|
||||
|
||||
#define OP_ID4 0x0010 /* 16b: ID4 */
|
||||
|
||||
@@ -69,7 +69,7 @@ sim> boot pt0
|
||||
|
||||
Breakpoint: PC: 00C2 (EXBR R8,R6)
|
||||
|
||||
sim> run 100
|
||||
sim> run 2d0
|
||||
|
||||
MODEL 8/16E PROCESSOR TEST PART 2 06-212R00
|
||||
CPU
|
||||
@@ -96,7 +96,7 @@ Breakpoint, PC: 00C0 (8800)
|
||||
|
||||
sim> d 234a 0202 ; patch to use
|
||||
sim> d 234c a4a8 ; TTY as console
|
||||
sim> d 17a b1e4
|
||||
sim> d 17a b 1e4
|
||||
sim> run 100
|
||||
|
||||
SERIES SIXTEEN PROCESSOR TEST PART 1 06-242F01R00
|
||||
|
||||
@@ -259,6 +259,16 @@ control registers for the interrupt system.
|
||||
most recent PC change first
|
||||
WRU 8 interrupt character
|
||||
|
||||
The CPU can maintain a history of the most recently executed instructions.
|
||||
This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:
|
||||
|
||||
SET CPU HISTORY clear history buffer
|
||||
SET CPU HISTORY=0 disable history
|
||||
SET CPU HISTORY=n enable history, display length = n
|
||||
SHOW CPU HISTORY print CPU history
|
||||
|
||||
The maximum length for the history is 65536 entries.
|
||||
|
||||
2.3 Selector Channel (SELCH)
|
||||
|
||||
An Interdata system can have 1 to 4 selector channels (SELCH0, SELCH1,
|
||||
|
||||
@@ -276,6 +276,7 @@ return 0;
|
||||
t_stat fd_svc (UNIT *uptr)
|
||||
{
|
||||
uint32 i, u, tk, sc, crc, fnc, da;
|
||||
uint8 *fbuf = uptr->filebuf;
|
||||
|
||||
u = uptr - fd_dev.units; /* get unit number */
|
||||
fnc = GET_FNC (uptr->FNC); /* get function */
|
||||
@@ -296,9 +297,9 @@ case FNC_RD: /* read, buf empty */
|
||||
if (fd_dte (uptr, FALSE)) return SCPE_OK; /* xfr error? */
|
||||
da = GET_DA (uptr->LRN); /* get disk addr */
|
||||
for (i = 0; i < FD_NUMBY; i++) /* read sector */
|
||||
fdxb[i] = *(((uint8 *) uptr->filebuf) + da + i);
|
||||
if (*(((uint8 *) uptr->filebuf) + FD_SIZE + uptr->LRN - 1)) {
|
||||
fd_sta = fd_sta | STA_DEL; /* deleted? set err */
|
||||
fdxb[i] = fbuf[da + i];
|
||||
if (fbuf[FD_SIZE + uptr->LRN - 1]) { /* deleted? set err */
|
||||
fd_sta = fd_sta | STA_DEL;
|
||||
fd_es[u][0] = fd_es[u][0] | ES0_DEL; }
|
||||
fd_es[u][2] = GET_SEC (uptr->LRN); /* set ext sec/trk */
|
||||
fd_es[u][3] = GET_TRK (uptr->LRN);
|
||||
@@ -313,9 +314,8 @@ case FNC_WR: case FNC_DEL: /* write block */
|
||||
for (i = fd_bptr; i < FD_NUMBY; i++) /* pad sector */
|
||||
fdxb[i] = fd_db;
|
||||
for (i = 0; i < FD_NUMBY; i++) /* write sector */
|
||||
*(((uint8 *) uptr->filebuf) + da + i) = fdxb[i];
|
||||
*(((uint8 *) uptr->filebuf) + FD_SIZE + uptr->LRN - 1) =
|
||||
(fnc == FNC_DEL)? 1: 0; /* write dir */
|
||||
fbuf[da + i] = fdxb[i]; /* then dir */
|
||||
fbuf[FD_SIZE + uptr->LRN - 1] = ((fnc == FNC_DEL)? 1: 0);
|
||||
uptr->hwmark = uptr->capac; /* rewrite all */
|
||||
fd_es[u][2] = GET_SEC (uptr->LRN); /* set ext sec/trk */
|
||||
fd_es[u][3] = GET_TRK (uptr->LRN);
|
||||
|
||||
@@ -546,9 +546,9 @@ for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru devices */
|
||||
if (tplte == NULL) tplte = dflt_tplte; /* none? use default */
|
||||
for ( ; *tplte != TPL_END; tplte++) { /* loop thru template */
|
||||
t = (dno + *tplte) & DEV_MAX; /* loop thru template */
|
||||
dmsk = 1u << (t & 0x1F); /* bit to test */
|
||||
dmsk = 1u << (t & 0x1F); /* bit to test */
|
||||
doff = t / 32; /* word to test */
|
||||
if (dmap[doff] & dmsk) { /* in use? */
|
||||
if (dmap[doff] & dmsk) { /* in use? */
|
||||
printf ("Device number conflict, devno = %02X\n", t);
|
||||
if (sim_log) fprintf (sim_log,
|
||||
"Device number conflict, devno = %02X\n", t);
|
||||
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
tt console
|
||||
|
||||
29-Dec-03 RMS Added support for console backpressure
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
11-Jan-03 RMS Added TTP support
|
||||
22-Dec-02 RMS Added break support
|
||||
@@ -192,16 +193,18 @@ t_stat tto_svc (UNIT *uptr)
|
||||
int32 ch;
|
||||
t_stat r;
|
||||
|
||||
if (!tt_rd) { /* write mode? */
|
||||
tt_sta = tt_sta & ~STA_BSY; /* clear busy */
|
||||
if (tt_arm) SET_INT (v_TT); } /* if armed, intr */
|
||||
if (uptr->flags & UNIT_KSR) { /* KSR mode? */
|
||||
ch = uptr->buf & 0x7F; /* mask to 7b */
|
||||
if (islower (ch)) ch = toupper (ch); } /* cvt to UC */
|
||||
else ch = uptr->buf & ((tt_unit[TTO].flags & UNIT_8B)? 0xFF: 0x7F);
|
||||
if (!(uptr->flags & UNIT_8B) && /* KSR or 7b? */
|
||||
((ch == 0) || (ch == 0x7F))) return SCPE_OK; /* supr NULL, DEL */
|
||||
if ((r = sim_putchar (ch)) != SCPE_OK) return r; /* output */
|
||||
if ((uptr->flags & UNIT_8B) || /* KSR or 7b? */
|
||||
((ch != 0) && (ch != 0x7F))) { /* supr NULL, DEL */
|
||||
if ((r = sim_putchar_s (ch)) != SCPE_OK) { /* output; error? */
|
||||
sim_activate (uptr, uptr->wait); /* try again */
|
||||
return ((r == SCPE_STALL)? SCPE_OK: r); } }
|
||||
if (!tt_rd) { /* write mode? */
|
||||
tt_sta = tt_sta & ~STA_BSY; /* clear busy */
|
||||
if (tt_arm) SET_INT (v_TT); } /* if armed, intr */
|
||||
uptr->pos = uptr->pos + 1; /* incr count */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* id_ttp.c: Interdata PASLA console interface
|
||||
|
||||
Copyright (c) 2000-2003, Robert M. Supnik
|
||||
Copyright (c) 2000-2004, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
ttp console (on PAS)
|
||||
|
||||
29-Dec-03 RMS Added support for console backpressure
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
*/
|
||||
|
||||
@@ -195,16 +196,18 @@ t_stat ttpo_svc (UNIT *uptr)
|
||||
int32 c;
|
||||
t_stat r;
|
||||
|
||||
ttp_sta = ttp_sta & ~STA_BSY; /* not busy */
|
||||
if (ttp_tarm) SET_INT (v_TTP + 1); /* set intr */
|
||||
if (uptr->flags & UNIT_8B) /* 8b? */
|
||||
c = pas_par (ttp_cmd, uptr->buf); /* apply parity */
|
||||
else { c = uptr->buf & 0x7F; /* mask char */
|
||||
if ((uptr->flags & UNIT_UC) && islower (c))
|
||||
c = toupper (c); } /* cvt to UC */
|
||||
if (!(uptr->flags & UNIT_8B) && /* UC or 7b? */
|
||||
((c == 0) || (c == 0x7F))) return SCPE_OK; /* supr NULL, DEL */
|
||||
if ((r = sim_putchar (c)) != SCPE_OK) return r; /* output */
|
||||
if ((uptr->flags & UNIT_8B) || /* UC or 7b? */
|
||||
((c != 0) && (c != 0x7F))){ /* supr NULL, DEL */
|
||||
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
|
||||
sim_activate (uptr, uptr->wait); /* try again */
|
||||
return ((r == SCPE_STALL)? SCPE_OK: r); } }
|
||||
ttp_sta = ttp_sta & ~STA_BSY; /* not busy */
|
||||
if (ttp_tarm) SET_INT (v_TTP + 1); /* set intr */
|
||||
uptr->pos = uptr->pos + 1; /* incr count */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user