mirror of
https://github.com/simh/simh.git
synced 2026-04-05 05:13:38 +00:00
Merge branch 'DMC11' into SerialMux
Conflicts: scp.c sim_ether.c sim_ether.h sim_tmxr.c
This commit is contained in:
@@ -1134,7 +1134,7 @@ switch (op) { /* case on opcode */
|
||||
result = (A2ADR << 16) | A2LNT; /* op in VAX format */
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CVTLx:
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dst = Dstr0; /* clear result */
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if (dst.sign = GET_SIGN_L (result))
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if ((dst.sign = GET_SIGN_L (result)))
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result = (~result + 1) & 0xFFFFFFFF;
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for (i = 1; (i < (DSTRLNT * 8)) && result; i++) {
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digit = result % 10;
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@@ -1267,7 +1267,7 @@ for (i = 0; i < DSTRLNT; i++) { /* loop thru value */
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mask = 0xFFFFFFFF;
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if (dst->val[i] & mask) /* test for ovflo */
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V = 1;
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if (dst->val[i] = dst->val[i] & ~mask) /* test nz */
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if ((dst->val[i] = dst->val[i] & ~mask)) /* test nz */
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Z = 0;
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}
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dst->sign = dst->sign & ~unsignedtab[type] & ~(Z & ~V);
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@@ -1523,7 +1523,7 @@ uint32 NibbleRshift (DSTR *dsrc, int32 sc, uint32 cin)
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{
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int32 i, s, nc;
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if (s = sc * 4) {
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if ((s = sc * 4)) {
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for (i = DSTRMAX; i >= 0; i--) {
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nc = (dsrc->val[i] << (32 - s)) & 0xFFFFFFFF;
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dsrc->val[i] = ((dsrc->val[i] >> s) |
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@@ -1548,7 +1548,7 @@ int32 i, s;
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uint32 nc, cin;
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cin = 0;
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if (s = sc * 4) {
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if ((s = sc * 4)) {
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for (i = 0; i < DSTRLNT; i++) {
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nc = dsrc->val[i] >> (32 - s);
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dsrc->val[i] = ((dsrc->val[i] << s) | cin) & 0xFFFFFFFF;
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@@ -25,6 +25,7 @@
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cpu PDP-11 CPU
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29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
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19-Mar-12 RMS Fixed declaration of sim_switches (Mark Pizzolato)
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29-Dec-08 RMS Fixed failure to clear cpu_bme on RESET (Walter Mueller)
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22-Apr-08 RMS Fixed MMR0 treatment in RESET (Walter Mueller)
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@@ -731,7 +732,7 @@ while (reason == 0) {
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if (trap_req) { /* check traps, ints */
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trapea = 0; /* assume srch fails */
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if (t = trap_req & TRAP_ALL) { /* if a trap */
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if ((t = trap_req & TRAP_ALL)) { /* if a trap */
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for (trapnum = 0; trapnum < TRAP_V_MAX; trapnum++) {
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if ((t >> trapnum) & 1) { /* trap set? */
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trapea = trap_vec[trapnum]; /* get vec, clr */
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@@ -1292,7 +1293,7 @@ while (reason == 0) {
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break;
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case 070: /* CSM */
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if (CPUT (HAS_CSM) && (MMR3 & MMR3_CSM) || (cm != MD_KER)) {
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if ((CPUT (HAS_CSM) && (MMR3 & MMR3_CSM)) || (cm != MD_KER)) {
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dst = dstreg? R[dstspec]: ReadW (GeteaW (dstspec));
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PSW = get_PSW () & ~PSW_CC; /* PSW, cc = 0 */
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STACKFILE[cm] = SP;
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@@ -1075,7 +1075,7 @@ t_stat r;
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for (i = 0; cnf_tab[i].dib != NULL; i++) { /* loop thru config tab */
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if (((cnf_tab[i].cpum == 0) || (cpu_type & cnf_tab[i].cpum)) &&
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((cnf_tab[i].optm == 0) || (cpu_opt & cnf_tab[i].optm))) {
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if (r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)) /* add to dispatch tab */
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if ((r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)))/* add to dispatch tab */
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return r;
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}
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}
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@@ -346,7 +346,7 @@ if (ln >= 0) { /* got one? rcv enb */
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tmxr_poll_rx (&dlx_desc); /* poll for input */
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for (ln = 0; ln < DLX_LINES; ln++) { /* loop thru lines */
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if (dlx_ldsc[ln].conn) { /* connected? */
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if (temp = tmxr_getc_ln (&dlx_ldsc[ln])) { /* get char */
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if ((temp = tmxr_getc_ln (&dlx_ldsc[ln]))) { /* get char */
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if (temp & SCPE_BREAK) /* break? */
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c = DLIBUF_ERR|DLIBUF_RBRK;
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else c = sim_tt_inpcvt (temp, TT_GET_MODE (dlo_unit[ln].flags));
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2273
PDP11/pdp11_dmc.c
Normal file
2273
PDP11/pdp11_dmc.c
Normal file
File diff suppressed because it is too large
Load Diff
132
PDP11/pdp11_dmc.h
Normal file
132
PDP11/pdp11_dmc.h
Normal file
@@ -0,0 +1,132 @@
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/* pdp11_dmc.h: DMC11 Emulation
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------------------------------------------------------------------------------
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Copyright (c) 2011, Robert M. A. Jarratt
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Permission is hereby granted, free of charge, to any person obtaining a
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||||
copy of this software and associated documentation files (the "Software"),
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||||
to deal in the Software without restriction, including without limitation
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||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
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||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
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||||
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||||
The above copyright notice and this permission notice shall be included in
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||||
all copies or substantial portions of the Software.
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||||
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||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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||||
THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of the author shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from the author.
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------------------------------------------------------------------------------*/
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// Notes
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// Base address needs to be 760060 according to DMC11 manual, but SYSGEN seems to think CSR is 0760100. However if I use
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// 0760100 I get a conflict with the DZ because the first 13 bits are still 00100. If I use 760060 VMS sees the XM device, but
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// if I remove the DZ to prevent the conflict VMS does not see an XM device, but I do get lots of reads and writes, possibly
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// because it thinks it is a different device. What worries me more though is that there seems to be overlap in the 13-bit base
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// addresses of the DZ and DMC.
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#ifndef _PDP11_DMC_H
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#define _PDP11_DMC_H
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#if defined (VM_VAX) /* VAX version */
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#include "vax_defs.h"
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extern int32 int_req[IPL_HLVL];
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#else /* PDP-11 version */
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#include "pdp11_defs.h"
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extern int32 int_req[IPL_HLVL];
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#endif
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#include "sim_sock.h"
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#define DMC_NUMDEVICE 4 /* # DMC-11 devices */
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#define DMC_UNITSPERDEVICE 1 /* # units per DMC-11 */
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#define DMP_NUMDEVICE 1 /* # DMP-11 devices */
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#define DMP_UNITSPERDEVICE 1 /* # units per DMP-11 */
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#define DMC_RDX 8
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/* debugging bitmaps */
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#define DBG_TRC 0x0001 /* trace routine calls */
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#define DBG_REG 0x0002 /* trace read/write registers */
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#define DBG_WRN 0x0004 /* display warnings */
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#define DBG_INF 0x0008 /* display informational messages (high level trace) */
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#define DBG_DAT 0x0010 /* display data buffer contents */
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#define DBG_DTS 0x0020 /* display data summary */
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#define DBG_SOK 0x0040 /* display socket open/close */
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#define DBG_CON 0x0080 /* display socket connection establishment */
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#define TYPE_BACCI 0
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#define TYPE_CNTLI 1
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#define TYPE_BASEI 03
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#define TYPE_BACCO 0
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#define TYPE_CNTLO 1
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#define TYPE_DMP_MODE 2
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#define TYPE_DMP_CONTROL 1
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#define TYPE_DMP_RECEIVE 0
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#define TYPE_DMP_TRANSMIT 4
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/* SEL0 */
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#define DMC_TYPE_INPUT_MASK 0x0003
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#define DMC_IN_IO_MASK 0x0004
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#define DMP_IEO_MASK 0x0010
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#define DMC_RQI_MASK 0x0020
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#define DMP_RQI_MASK 0x0080
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#define DMC_RDYI_MASK 0x0080
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#define DMC_IEI_MASK 0x0040
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#define DMP_IEI_MASK 0x0001
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#define LU_LOOP_MASK 0x0800
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#define MASTER_CLEAR_MASK 0x4000
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#define RUN_MASK 0x8000
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/* SEL2 */
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#define DMP_IN_IO_MASK 0x0004
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#define DMP_TYPE_INPUT_MASK 0x0007
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#define TYPE_OUTPUT_MASK 0x0003
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#define OUT_IO_MASK 0x0004
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#define DMC_RDYO_MASK 0x0080
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#define DMC_IEO_MASK 0x0040
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#define DMP_RDYI_MASK 0x0010
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/* BSEL6 */
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#define LOST_DATA_MASK 0x0010
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#define DISCONNECT_MASK 0x0040
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#define SEL0_RUN_BIT 15
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#define SEL0_MCLR_BIT 14
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#define SEL0_LU_LOOP_BIT 11
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#define SEL0_RDI_BIT 7
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#define SEL0_DMC_IEI_BIT 6
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#define SEL0_DMP_IEI_BIT 0
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#define SEL0_DMP_IEO_BIT 4
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#define SEL0_DMC_RQI_BIT 5
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#define SEL0_DMP_RQI_BIT 7
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#define SEL0_IN_IO_BIT 2
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#define SEL0_TYPEI_BIT 0
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#define SEL2_TYPEO_BIT 0
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#define SEL2_RDO_BIT 7
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#define SEL2_IEO_BIT 6
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#define SEL2_OUT_IO_BIT 2
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#define SEL2_LINE_BIT 8
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#define SEL2_LINE_BIT_LENGTH 6
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#define SEL2_PRIO_BIT 14
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#define SEL2_PRIO_BIT_LENGTH 2
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#define SEL6_LOST_DATA_BIT 4
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#define SEL6_DISCONNECT_BIT 6
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#define BUFFER_QUEUE_SIZE 7
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#endif /* _VAX_DMC_H */
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@@ -438,7 +438,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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else fac.l = ReadI (GeteaFP (dstspec, leni), dstspec, leni);
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fac.h = 0;
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if (fac.l) {
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if (sign = GET_SIGN_L (fac.l))
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if ((sign = GET_SIGN_L (fac.l)))
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fac.l = (fac.l ^ 0xFFFFFFFF) + 1;
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for (i = 0; GET_SIGN_L (fac.l) == 0; i++)
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fac.l = fac.l << 1;
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@@ -887,7 +887,7 @@ switch (fnc) { /* case on function */
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err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);
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if (uptr->FNC == FNC_WRITE) { /* write? */
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if (hkcs2 & CS2_UAI) { /* no addr inc? */
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if (t = Map_ReadW (ba, 2, &comp)) { /* get 1st wd */
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if ((t = Map_ReadW (ba, 2, &comp))) { /* get 1st wd */
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wc = 0; /* NXM, no xfr */
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hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
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}
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@@ -895,7 +895,7 @@ switch (fnc) { /* case on function */
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hkxb[i] = comp;
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}
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else { /* normal */
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if (t = Map_ReadW (ba, wc << 1, hkxb)) { /* get buf */
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if ((t = Map_ReadW (ba, wc << 1, hkxb))) {/* get buf */
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wc = wc - (t >> 1); /* NXM, adj wc */
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hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
|
||||
}
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@@ -915,13 +915,13 @@ switch (fnc) { /* case on function */
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for ( ; i < wc; i++) /* fill buf */
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hkxb[i] = 0;
|
||||
if (hkcs2 & CS2_UAI) { /* no addr inc? */
|
||||
if (t = Map_WriteW (ba, 2, &hkxb[wc - 1])) {
|
||||
if ((t = Map_WriteW (ba, 2, &hkxb[wc - 1]))) {
|
||||
wc = 0; /* NXM, no xfr */
|
||||
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
|
||||
}
|
||||
}
|
||||
else { /* normal */
|
||||
if (t = Map_WriteW (ba, wc << 1, hkxb)) { /* put buf */
|
||||
if ((t = Map_WriteW (ba, wc << 1, hkxb))) {/* put buf */
|
||||
wc = wc - (t >> 1); /* NXM, adj wc */
|
||||
hkcs2 = hkcs2 | CS2_NEM; /* set nxm err */
|
||||
}
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
27-Mar-12 RMS Fixed order of int_internal (Jordi Guillaumes i Pons)
|
||||
19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato)
|
||||
12-Dec-11 RMS Fixed Qbus interrupts to treat all IO devices as BR4
|
||||
19-Nov-08 RMS Moved I/O support routines to I/O library
|
||||
@@ -83,8 +84,8 @@ static const int32 pirq_bit[7] = {
|
||||
};
|
||||
|
||||
static const int32 int_internal[IPL_HLVL] = {
|
||||
INT_INTERNAL7, INT_INTERNAL6, INT_INTERNAL5, INT_INTERNAL4,
|
||||
INT_INTERNAL3, INT_INTERNAL2, INT_INTERNAL1, 0
|
||||
0, INT_INTERNAL1, INT_INTERNAL2, INT_INTERNAL3,
|
||||
INT_INTERNAL4, INT_INTERNAL5, INT_INTERNAL6, INT_INTERNAL7
|
||||
};
|
||||
|
||||
/* I/O page lookup and linkage routines
|
||||
@@ -372,17 +373,17 @@ init_ubus_tab (); /* init Unibus tables */
|
||||
init_mbus_tab (); /* init Massbus tables */
|
||||
for (i = 0; i < 7; i++) /* seed PIRQ intr */
|
||||
int_vec[i + 1][pirq_bit[i]] = VEC_PIRQ;
|
||||
if (r = cpu_build_dib ()) /* build CPU entries */
|
||||
if ((r = cpu_build_dib ())) /* build CPU entries */
|
||||
return r;
|
||||
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
|
||||
dibp = (DIB *) dptr->ctxt; /* get DIB */
|
||||
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
|
||||
if (dptr->flags & DEV_MBUS) { /* Massbus? */
|
||||
if (r = build_mbus_tab (dptr, dibp)) /* add to Mbus tab */
|
||||
if ((r = build_mbus_tab (dptr, dibp))) /* add to Mbus tab */
|
||||
return r;
|
||||
}
|
||||
else { /* no, Unibus */
|
||||
if (r = build_ubus_tab (dptr, dibp)) /* add to Unibus tab */
|
||||
if ((r = build_ubus_tab (dptr, dibp))) /* add to Unibus tab */
|
||||
return r;
|
||||
}
|
||||
} /* end if enabled */
|
||||
|
||||
@@ -252,7 +252,7 @@ switch (PA & 017) { /* decode PA<3:0> */
|
||||
data = data & 077; /* 6b shift count */
|
||||
if (data != 0) {
|
||||
t32 = (ke_AC << 16) | ke_MQ; /* 32b operand */
|
||||
if (sign = GET_SIGN_W (ke_AC)) /* sext operand */
|
||||
if ((sign = GET_SIGN_W (ke_AC))) /* sext operand */
|
||||
t32 = t32 | ~017777777777;
|
||||
if (data < 32) { /* [1,31] - left */
|
||||
sout = (t32 >> (32 - data)) | (-sign << data);
|
||||
@@ -282,7 +282,7 @@ switch (PA & 017) { /* decode PA<3:0> */
|
||||
data = data & 077; /* 6b shift count */
|
||||
if (data != 0) {
|
||||
t32 = (ke_AC << 16) | ke_MQ; /* 32b operand */
|
||||
if (sign = GET_SIGN_W (ke_AC)) /* sext operand */
|
||||
if ((sign = GET_SIGN_W (ke_AC))) /* sext operand */
|
||||
t32 = t32 | ~017777777777;
|
||||
if (data < 32) { /* [1,31] - left */
|
||||
sout = (t32 >> (31 - data)) | (-sign << data);
|
||||
|
||||
@@ -211,7 +211,7 @@
|
||||
#define CMD_REFL 2 /* ref # */
|
||||
#define CMD_REFH 3
|
||||
#define CMD_UN 4 /* unit # */
|
||||
/* 5 /* reserved */
|
||||
/* 5 *//* reserved */
|
||||
#define CMD_OPC 6 /* opcode */
|
||||
#define CMD_MOD 7 /* modifier */
|
||||
|
||||
@@ -256,14 +256,14 @@
|
||||
/* Flush - 10 W status (8 undefined) */
|
||||
|
||||
#define FLU_LNT 32
|
||||
/* 8 - 15 /* reserved */
|
||||
/* 8 - 15 *//* reserved */
|
||||
#define FLU_POSL 16 /* position */
|
||||
#define FLU_POSH 17
|
||||
|
||||
/* Write tape mark - 10W status (8 undefined) */
|
||||
|
||||
#define WTM_LNT 32
|
||||
/* 8 - 15 /* reserved */
|
||||
/* 8 - 15 *//* reserved */
|
||||
#define WTM_POSL 16 /* position */
|
||||
#define WTM_POSH 17
|
||||
|
||||
@@ -399,8 +399,8 @@
|
||||
#define RW_BAH 11
|
||||
#define RW_MAPL 12 /* map table */
|
||||
#define RW_MAPH 13
|
||||
/* 14 /* reserved */
|
||||
/* 15 /* reserved */
|
||||
/* 14 *//* reserved */
|
||||
/* 15 *//* reserved */
|
||||
|
||||
/* Disk specific parameters */
|
||||
|
||||
|
||||
@@ -545,13 +545,13 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
rkxb[i] = 0;
|
||||
}
|
||||
if (rkcs & RKCS_INH) { /* incr inhibit? */
|
||||
if (t = Map_WriteW (ma, 2, &rkxb[wc - 1])) { /* store last */
|
||||
if ((t = Map_WriteW (ma, 2, &rkxb[wc - 1]))) {/* store last */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = 0; /* no transfer */
|
||||
}
|
||||
}
|
||||
else { /* normal store */
|
||||
if (t = Map_WriteW (ma, wc << 1, rkxb)) { /* store buf */
|
||||
if ((t = Map_WriteW (ma, wc << 1, rkxb))) { /* store buf */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = wc - t; /* adj wd cnt */
|
||||
}
|
||||
@@ -560,7 +560,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
|
||||
case RKCS_WRITE: /* write */
|
||||
if (rkcs & RKCS_INH) { /* incr inhibit? */
|
||||
if (t = Map_ReadW (ma, 2, &comp)) { /* get 1st word */
|
||||
if ((t = Map_ReadW (ma, 2, &comp))) { /* get 1st word */
|
||||
rker = rker | RKER_NXM; /* NXM? set flag */
|
||||
wc = 0; /* no transfer */
|
||||
}
|
||||
@@ -568,7 +568,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
rkxb[i] = comp;
|
||||
}
|
||||
else { /* normal fetch */
|
||||
if (t = Map_ReadW (ma, wc << 1, rkxb)) { /* get buf */
|
||||
if ((t = Map_ReadW (ma, wc << 1, rkxb))) { /* get buf */
|
||||
rker = rker | RKER_NXM; /* NXM? set flg */
|
||||
wc = wc - t; /* adj wd cnt */
|
||||
}
|
||||
@@ -584,7 +584,7 @@ if (wc && (err == 0)) { /* seek ok? */
|
||||
|
||||
case RKCS_WCHK: /* write check */
|
||||
i = fxread (rkxb, sizeof (int16), wc, uptr->fileref);
|
||||
if (err = ferror (uptr->fileref)) { /* read error? */
|
||||
if ((err = ferror (uptr->fileref))) { /* read error? */
|
||||
wc = 0; /* no transfer */
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -894,7 +894,7 @@ UNIT rqb_unit[] = {
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
|
||||
};
|
||||
|
||||
@@ -966,7 +966,7 @@ UNIT rqc_unit[] = {
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
|
||||
};
|
||||
|
||||
@@ -1038,7 +1038,7 @@ UNIT rqd_unit[] = {
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+
|
||||
(RD54_DTYPE << UNIT_V_DTYPE), RQ_SIZE (RD54)) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_tmrsvc, UNIT_IDLE|UNIT_DIS, 0) },
|
||||
{ UDATA (&rq_quesvc, UNIT_DIS, 0) }
|
||||
};
|
||||
|
||||
@@ -1442,7 +1442,7 @@ DEVICE *dptr = rq_devmap[cp->cnum];
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_abo\n");
|
||||
|
||||
tpkt = 0; /* set no mtch */
|
||||
if (uptr = rq_getucb (cp, lu)) { /* get unit */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* get unit */
|
||||
if (uptr->cpkt && /* curr pkt? */
|
||||
(GETP32 (uptr->cpkt, CMD_REFL) == ref)) { /* match ref? */
|
||||
tpkt = uptr->cpkt; /* save match */
|
||||
@@ -1455,8 +1455,8 @@ if (uptr = rq_getucb (cp, lu)) { /* get unit */
|
||||
tpkt = uptr->pktq; /* save match */
|
||||
uptr->pktq = cp->pak[tpkt].link; /* unlink */
|
||||
}
|
||||
else if (prv = uptr->pktq) { /* srch pkt q */
|
||||
while (tpkt = cp->pak[prv].link) { /* walk list */
|
||||
else if ((prv = uptr->pktq)) { /* srch pkt q */
|
||||
while ((tpkt = cp->pak[prv].link)) { /* walk list */
|
||||
if (GETP32 (tpkt, RSP_REFL) == ref) { /* match? unlink */
|
||||
cp->pak[prv].link = cp->pak[tpkt].link;
|
||||
break;
|
||||
@@ -1486,7 +1486,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_avl\n");
|
||||
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if (q && uptr->cpkt) { /* need to queue? */
|
||||
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
|
||||
return OK;
|
||||
@@ -1546,7 +1546,7 @@ if (cp->pak[pkt].d[CMD_MOD] & MD_NXU) { /* next unit? */
|
||||
cp->pak[pkt].d[RSP_UN] = lu;
|
||||
}
|
||||
}
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
|
||||
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
|
||||
else if (uptr->flags & UNIT_ONL) /* online */
|
||||
@@ -1583,7 +1583,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_onl\n");
|
||||
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if (q && uptr->cpkt) { /* need to queue? */
|
||||
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
|
||||
return OK;
|
||||
@@ -1626,7 +1626,7 @@ else {
|
||||
cmd = GETP (pkt, CMD_OPC, OPC); /* get opcode */
|
||||
cp->cflgs = (cp->cflgs & CF_RPL) | /* hack ctrl flgs */
|
||||
cp->pak[pkt].d[SCC_CFL];
|
||||
if (cp->htmo = cp->pak[pkt].d[SCC_TMO]) /* set timeout */
|
||||
if ((cp->htmo = cp->pak[pkt].d[SCC_TMO])) /* set timeout */
|
||||
cp->htmo = cp->htmo + 2; /* if nz, round up */
|
||||
cp->pak[pkt].d[SCC_CFL] = cp->cflgs; /* return flags */
|
||||
cp->pak[pkt].d[SCC_TMO] = RQ_DCTMO; /* ctrl timeout */
|
||||
@@ -1655,7 +1655,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_suc\n");
|
||||
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if (q && uptr->cpkt) { /* need to queue? */
|
||||
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
|
||||
return OK;
|
||||
@@ -1686,7 +1686,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_fmt\n");
|
||||
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if (q && uptr->cpkt) { /* need to queue? */
|
||||
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
|
||||
return OK;
|
||||
@@ -1722,7 +1722,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_rw(lu=%d, pkt=%d, queue=%s)\n", lu, pkt, q?"yes" : "no");
|
||||
|
||||
if (uptr = rq_getucb (cp, lu)) { /* unit exist? */
|
||||
if ((uptr = rq_getucb (cp, lu))) { /* unit exist? */
|
||||
if (q && uptr->cpkt) { /* need to queue? */
|
||||
sim_debug (DBG_TRC, rq_devmap[cp->cnum], "rq_rw - queued\n");
|
||||
rq_enqt (cp, &uptr->pktq, pkt); /* do later */
|
||||
@@ -1769,7 +1769,7 @@ if (bc & 1) /* odd byte cnt? */
|
||||
return (ST_HST | SB_HST_OC);
|
||||
if (bc & 0xF0000000) /* 'reasonable' bc? */
|
||||
return (ST_CMD | I_BCNT);
|
||||
/* if (lbn & 0xF0000000) return (ST_CMD | I_LBN); /* 'reasonable' lbn? */
|
||||
/* if (lbn & 0xF0000000) return (ST_CMD | I_LBN); *//* 'reasonable' lbn? */
|
||||
if (lbn >= maxlbn) { /* accessing RCT? */
|
||||
if (lbn >= (maxlbn + drv_tab[dtyp].rcts)) /* beyond copy 1? */
|
||||
return (ST_CMD | I_LBN); /* lbn err */
|
||||
@@ -1854,7 +1854,7 @@ if (!uptr->io_complete) { /* Top End (I/O Initiation) Processing */
|
||||
|
||||
else if (cmd == OP_WR) { /* write? */
|
||||
t = Map_ReadW (ba, tbc, uptr->rqxb); /* fetch buffer */
|
||||
if (abc = tbc - t) { /* any xfer? */
|
||||
if ((abc = tbc - t)) { /* any xfer? */
|
||||
wwc = ((abc + (RQ_NUMBY - 1)) & ~(RQ_NUMBY - 1)) >> 1;
|
||||
for (i = (abc >> 1); i < wwc; i++)
|
||||
((uint16 *)(uptr->rqxb))[i] = 0;
|
||||
@@ -1889,7 +1889,7 @@ else { /* Bottom End (After I/O processing) */
|
||||
else {
|
||||
sim_disk_data_trace(uptr, uptr->rqxb, bl, tbc, "sim_disk_rdsect", DBG_DAT & rq_devmap[cp->cnum]->dctrl, DBG_REQ);
|
||||
if ((cmd == OP_RD) && !err) { /* read? */
|
||||
if (t = Map_WriteW (ba, tbc, uptr->rqxb)) { /* store, nxm? */
|
||||
if ((t = Map_WriteW (ba, tbc, uptr->rqxb))) {/* store, nxm? */
|
||||
PUTP32 (pkt, RW_WBCL, bc - (tbc - t)); /* adj bc */
|
||||
PUTP32 (pkt, RW_WBAL, ba + (tbc - t)); /* adj ba */
|
||||
if (rq_hbe (cp, uptr)) /* post err log */
|
||||
@@ -2746,11 +2746,11 @@ if ((uptr->flags & UNIT_ONL) == 0) {
|
||||
if (uptr->cpkt) {
|
||||
fprintf (st, "Unit %d current ", u);
|
||||
rq_show_pkt (st, cp, uptr->cpkt);
|
||||
if (pkt = uptr->pktq) {
|
||||
if ((pkt = uptr->pktq)) {
|
||||
do {
|
||||
fprintf (st, "Unit %d queued ", u);
|
||||
rq_show_pkt (st, cp, pkt);
|
||||
} while (pkt = cp->pak[pkt].link);
|
||||
} while ((pkt = cp->pak[pkt].link));
|
||||
}
|
||||
}
|
||||
else fprintf (st, "Unit %d queues are empty\n", u);
|
||||
@@ -2777,7 +2777,7 @@ if (val & RQ_SH_RI) {
|
||||
rq_show_ring (st, &cp->rq);
|
||||
}
|
||||
if (val & RQ_SH_FR) {
|
||||
if (pkt = cp->freq) {
|
||||
if ((pkt = cp->freq)) {
|
||||
for (i = 0; pkt != 0; i++, pkt = cp->pak[pkt].link) {
|
||||
if (i == 0)
|
||||
fprintf (st, "Free queue = %d", pkt);
|
||||
@@ -2790,11 +2790,11 @@ if (val & RQ_SH_FR) {
|
||||
else fprintf (st, "Free queue is empty\n");
|
||||
}
|
||||
if (val & RQ_SH_RS) {
|
||||
if (pkt = cp->rspq) {
|
||||
if ((pkt = cp->rspq)) {
|
||||
do {
|
||||
fprintf (st, "Response ");
|
||||
rq_show_pkt (st, cp, pkt);
|
||||
} while (pkt = cp->pak[pkt].link);
|
||||
} while ((pkt = cp->pak[pkt].link));
|
||||
}
|
||||
else fprintf (st, "Response queue is empty\n");
|
||||
}
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* pdp11_sys.c: PDP-11 simulator interface
|
||||
|
||||
Copyright (c) 1993-2008, Robert M Supnik
|
||||
Copyright (c) 1993-2012, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
29-Apr-12 RMS Fixed compiler warning (Mark Pizzolato)
|
||||
19-Nov-08 RMS Moved I/O support routines to I/O library
|
||||
15-May-08 RMS Added KE11-A, DC11 support
|
||||
Renamed DL11
|
||||
@@ -992,7 +993,7 @@ switch (j) { /* case on class */
|
||||
disp = (disp - addr) & 0177777;
|
||||
else return SCPE_ARG;
|
||||
}
|
||||
if ((disp & 1) || (disp > 0400) && (disp < 0177402))
|
||||
if ((disp & 1) || ((disp > 0400) && (disp < 0177402)))
|
||||
return SCPE_ARG;
|
||||
val[0] = val[0] | (((disp - 2) >> 1) & 0377);
|
||||
break;
|
||||
|
||||
@@ -397,13 +397,13 @@ switch (uptr->FNC) { /* case on function */
|
||||
|
||||
case TACS_WRITE|TACS_3RD: /* write CRC */
|
||||
if (ta_bptr) { /* anything to write? */
|
||||
if (st = sim_tape_wrrecf (uptr, ta_xb, ta_bptr)) /* write, err? */
|
||||
if ((st = sim_tape_wrrecf (uptr, ta_xb, ta_bptr)))/* write, err? */
|
||||
r = ta_map_err (uptr, st); /* map error */
|
||||
}
|
||||
break; /* op done */
|
||||
|
||||
case TACS_WFG: /* write file gap */
|
||||
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
|
||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
||||
r = ta_map_err (uptr, st); /* map error */
|
||||
break;
|
||||
|
||||
@@ -413,7 +413,7 @@ switch (uptr->FNC) { /* case on function */
|
||||
break;
|
||||
|
||||
case TACS_SRB: /* space rev blk */
|
||||
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rev, err? */
|
||||
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rev, err? */
|
||||
r = ta_map_err (uptr, st); /* map error */
|
||||
break;
|
||||
|
||||
@@ -425,7 +425,7 @@ switch (uptr->FNC) { /* case on function */
|
||||
break;
|
||||
|
||||
case TACS_SFB: /* space fwd blk */
|
||||
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rev, err? */
|
||||
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rev, err? */
|
||||
r = ta_map_err (uptr, st); /* map error */
|
||||
ta_cs |= TACS_CRC; /* CRC sets, no err */
|
||||
break;
|
||||
|
||||
@@ -992,7 +992,7 @@ switch (fnc) { /* at speed, check fnc *
|
||||
if (ba >= uptr->hwmark)
|
||||
uptr->hwmark = ba + 1;
|
||||
}
|
||||
/* else /* ignore hdr */
|
||||
/* else *//* ignore hdr */
|
||||
sim_activate (uptr, DT_WSIZE * dt_ltime);
|
||||
DT_SETDONE; /* set done */
|
||||
break;
|
||||
|
||||
@@ -377,7 +377,7 @@ if (f == MTC_UNLOAD) { /* unload? */
|
||||
}
|
||||
else if (f == MTC_REWIND) /* rewind */
|
||||
uptr->USTAT = uptr->USTAT | STA_REW; /* rewinding */
|
||||
/* else /* uncomment this else if rewind/unload don't set done */
|
||||
/* else *//* uncomment this else if rewind/unload don't set done */
|
||||
tm_cmd = tm_cmd & ~MTC_DONE; /* clear done */
|
||||
CLR_INT (TM); /* clear int */
|
||||
sim_activate (uptr, tm_time); /* start io */
|
||||
@@ -439,7 +439,7 @@ switch (f) { /* case on function */
|
||||
tm_sta = tm_sta | STA_RLE;
|
||||
if (tbc < cbc) /* use smaller */
|
||||
cbc = tbc;
|
||||
if (t = Map_WriteB (xma, cbc, tmxb)) { /* copy buf to mem */
|
||||
if ((t = Map_WriteB (xma, cbc, tmxb))) { /* copy buf to mem */
|
||||
tm_sta = tm_sta | STA_NXM; /* NXM, set err */
|
||||
cbc = cbc - t; /* adj byte cnt */
|
||||
}
|
||||
@@ -449,13 +449,13 @@ switch (f) { /* case on function */
|
||||
|
||||
case MTC_WRITE: /* write */
|
||||
case MTC_WREXT: /* write ext gap */
|
||||
if (t = Map_ReadB (xma, cbc, tmxb)) { /* copy mem to buf */
|
||||
if ((t = Map_ReadB (xma, cbc, tmxb))) { /* copy mem to buf */
|
||||
tm_sta = tm_sta | STA_NXM; /* NXM, set err */
|
||||
cbc = cbc - t; /* adj byte cnt */
|
||||
if (cbc == 0) /* no xfr? done */
|
||||
break;
|
||||
}
|
||||
if (st = sim_tape_wrrecf (uptr, tmxb, cbc)) /* write rec, err? */
|
||||
if ((st = sim_tape_wrrecf (uptr, tmxb, cbc))) /* write rec, err? */
|
||||
r = tm_map_err (uptr, st); /* map error */
|
||||
else {
|
||||
xma = (xma + cbc) & 0777777; /* inc bus addr */
|
||||
@@ -464,14 +464,14 @@ switch (f) { /* case on function */
|
||||
break;
|
||||
|
||||
case MTC_WREOF: /* write eof */
|
||||
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
|
||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
||||
r = tm_map_err (uptr, st); /* map error */
|
||||
break;
|
||||
|
||||
case MTC_SPACEF: /* space forward */
|
||||
do {
|
||||
tm_bc = (tm_bc + 1) & 0177777; /* incr wc */
|
||||
if (st = sim_tape_sprecf (uptr, &tbc)) { /* spc rec fwd, err? */
|
||||
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* spc rec fwd, err? */
|
||||
r = tm_map_err (uptr, st); /* map error */
|
||||
break;
|
||||
}
|
||||
@@ -481,7 +481,7 @@ switch (f) { /* case on function */
|
||||
case MTC_SPACER: /* space reverse */
|
||||
do {
|
||||
tm_bc = (tm_bc + 1) & 0177777; /* incr wc */
|
||||
if (st = sim_tape_sprecr (uptr, &tbc)) { /* spc rec rev, err? */
|
||||
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* spc rec rev, err? */
|
||||
r = tm_map_err (uptr, st); /* map error */
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -828,13 +828,13 @@ else if (mdf & ~tq_cmf[cmd]) { /* invalid mod? */
|
||||
sts = ST_CMD | I_MODF; /* ill mods */
|
||||
}
|
||||
else { /* valid cmd */
|
||||
if (uptr = tq_getucb (lu)) { /* valid unit? */
|
||||
if ((uptr = tq_getucb (lu))) { /* valid unit? */
|
||||
if (q && (tq_cmf[cmd] & CMF_SEQ) && /* queueing, seq, */
|
||||
(uptr->cpkt || uptr->pktq)) { /* and active? */
|
||||
tq_enqt (&uptr->pktq, pkt); /* do later */
|
||||
return OK;
|
||||
}
|
||||
/* if (tq_cmf[cmd] & MD_CDL) /* clr cch lost? */
|
||||
/* if (tq_cmf[cmd] & MD_CDL) *//* clr cch lost? */
|
||||
/* uptr->flags = uptr->flags & ~UNIT_CDL; */
|
||||
if ((mdf & MD_CSE) && (uptr->flags & UNIT_SXC)) /* clr ser exc? */
|
||||
uptr->flags = uptr->flags & ~UNIT_SXC;
|
||||
@@ -909,7 +909,7 @@ UNIT *uptr;
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_abo\n");
|
||||
|
||||
tpkt = 0; /* set no mtch */
|
||||
if (uptr = tq_getucb (lu)) { /* get unit */
|
||||
if ((uptr = tq_getucb (lu))) { /* get unit */
|
||||
if (uptr->cpkt && /* curr pkt? */
|
||||
(GETP32 (uptr->cpkt, CMD_REFL) == ref)) { /* match ref? */
|
||||
tpkt = uptr->cpkt; /* save match */
|
||||
@@ -922,8 +922,8 @@ if (uptr = tq_getucb (lu)) { /* get unit */
|
||||
tpkt = uptr->pktq; /* save match */
|
||||
uptr->pktq = tq_pkt[tpkt].link; /* unlink */
|
||||
}
|
||||
else if (prv = uptr->pktq) { /* srch pkt q */
|
||||
while (tpkt = tq_pkt[prv].link) { /* walk list */
|
||||
else if ((prv = uptr->pktq)) { /* srch pkt q */
|
||||
while ((tpkt = tq_pkt[prv].link)) { /* walk list */
|
||||
if (GETP32 (tpkt, RSP_REFL) == ref) { /* match ref? */
|
||||
tq_pkt[prv].link = tq_pkt[tpkt].link; /* unlink */
|
||||
break;
|
||||
@@ -953,7 +953,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_avl\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
if (uptr->flags & UNIT_SXC) /* ser exc pending? */
|
||||
sts = ST_SXC;
|
||||
else {
|
||||
@@ -1012,7 +1012,7 @@ if (tq_pkt[pkt].d[CMD_MOD] & MD_NXU) { /* next unit? */
|
||||
tq_pkt[pkt].d[RSP_UN] = lu;
|
||||
}
|
||||
}
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
|
||||
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
|
||||
else if (uptr->flags & UNIT_ONL) /* online */
|
||||
@@ -1039,7 +1039,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_onl\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
|
||||
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
|
||||
else if (uptr->flags & UNIT_ONL) /* already online? */
|
||||
@@ -1070,7 +1070,7 @@ if (tq_pkt[pkt].d[SCC_MSV]) /* MSCP ver = 0? */
|
||||
else {
|
||||
tq_cflgs = (tq_cflgs & CF_RPL) | /* hack ctrl flgs */
|
||||
tq_pkt[pkt].d[SCC_CFL];
|
||||
if (tq_htmo = tq_pkt[pkt].d[SCC_TMO]) /* set timeout */
|
||||
if ((tq_htmo = tq_pkt[pkt].d[SCC_TMO])) /* set timeout */
|
||||
tq_htmo = tq_htmo + 2; /* if nz, round up */
|
||||
tq_pkt[pkt].d[SCC_CFL] = tq_cflgs; /* return flags */
|
||||
tq_pkt[pkt].d[SCC_TMO] = TQ_DCTMO; /* ctrl timeout */
|
||||
@@ -1096,7 +1096,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_suc\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
if ((uptr->flags & UNIT_ATT) == 0) /* not attached? */
|
||||
sts = ST_OFL | SB_OFL_NV; /* offl no vol */
|
||||
else {
|
||||
@@ -1120,7 +1120,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_flu\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) /* unit exist? */
|
||||
sts = tq_mot_valid (uptr, OP_FLU); /* validate req */
|
||||
else sts = ST_OFL; /* offline */
|
||||
tq_putr (pkt, OP_FLU | OP_END, tq_efl (uptr), sts, FLU_LNT, UQ_TYP_SEQ);
|
||||
@@ -1138,7 +1138,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_erase\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
sts = tq_mot_valid (uptr, cmd); /* validity checks */
|
||||
if (sts == ST_SUC) { /* ok? */
|
||||
uptr->cpkt = pkt; /* op in progress */
|
||||
@@ -1162,7 +1162,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_wtm\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
objp = uptr->objp; /* position op */
|
||||
sts = tq_mot_valid (uptr, OP_WTM); /* validity checks */
|
||||
if (sts == ST_SUC) { /* ok? */
|
||||
@@ -1188,7 +1188,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_pos\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
objp = uptr->objp; /* position op */
|
||||
sts = tq_mot_valid (uptr, OP_POS); /* validity checks */
|
||||
if (sts == ST_SUC) { /* ok? */
|
||||
@@ -1224,7 +1224,7 @@ UNIT *uptr;
|
||||
|
||||
sim_debug(DBG_TRC, &tq_dev, "tq_rw\n");
|
||||
|
||||
if (uptr = tq_getucb (lu)) { /* unit exist? */
|
||||
if ((uptr = tq_getucb (lu))) { /* unit exist? */
|
||||
objp = uptr->objp; /* position op */
|
||||
sts = tq_mot_valid (uptr, cmd); /* validity checks */
|
||||
if (sts == ST_SUC) { /* ok? */
|
||||
@@ -1363,7 +1363,7 @@ switch (cmd) { /* case on command */
|
||||
}
|
||||
else wbc = res->tbc;
|
||||
if (cmd == OP_RD) { /* read? */
|
||||
if (t = Map_WriteB (ba, wbc, res->tqxb)) { /* store, nxm? */
|
||||
if ((t = Map_WriteB (ba, wbc, res->tqxb))) {/* store, nxm? */
|
||||
PUTP32 (pkt, RW_BCL, wbc - t); /* adj bc */
|
||||
if (tq_hbe (uptr, ba + wbc - t)) /* post err log */
|
||||
tq_mot_end (uptr, EF_LOG, ST_HST | SB_HST_NXM, res->tbc);
|
||||
@@ -1402,7 +1402,7 @@ switch (cmd) { /* case on command */
|
||||
|
||||
case OP_WR: /* write */
|
||||
if (!io_complete) { /* Top half processing */
|
||||
if (t = Map_ReadB (ba, bc, res->tqxb)) { /* fetch buf, nxm? */
|
||||
if ((t = Map_ReadB (ba, bc, res->tqxb))) { /* fetch buf, nxm? */
|
||||
PUTP32 (pkt, RW_BCL, 0); /* no bytes xfer'd */
|
||||
if (tq_hbe (uptr, ba + bc - t)) /* post err log */
|
||||
tq_mot_end (uptr, EF_LOG, ST_HST | SB_HST_NXM, bc);
|
||||
@@ -2291,11 +2291,11 @@ if ((uptr->flags & UNIT_ONL) == 0) {
|
||||
if (uptr->cpkt) {
|
||||
fprintf (st, "Unit %d current ", u);
|
||||
tq_show_pkt (st, uptr->cpkt);
|
||||
if (pkt = uptr->pktq) {
|
||||
if ((pkt = uptr->pktq)) {
|
||||
do {
|
||||
fprintf (st, "Unit %d queued ", u);
|
||||
tq_show_pkt (st, pkt);
|
||||
} while (pkt = tq_pkt[pkt].link);
|
||||
} while ((pkt = tq_pkt[pkt].link));
|
||||
}
|
||||
}
|
||||
else fprintf (st, "Unit %d queues are empty\n", u);
|
||||
@@ -2320,7 +2320,7 @@ if (val & TQ_SH_RI) {
|
||||
tq_show_ring (st, &tq_rq);
|
||||
}
|
||||
if (val & TQ_SH_FR) {
|
||||
if (pkt = tq_freq) {
|
||||
if ((pkt = tq_freq)) {
|
||||
for (i = 0; pkt != 0; i++, pkt = tq_pkt[pkt].link) {
|
||||
if (i == 0)
|
||||
fprintf (st, "Free queue = %d", pkt);
|
||||
@@ -2333,11 +2333,11 @@ if (val & TQ_SH_FR) {
|
||||
else fprintf (st, "Free queue is empty\n");
|
||||
}
|
||||
if (val & TQ_SH_RS) {
|
||||
if (pkt = tq_rspq) {
|
||||
if ((pkt = tq_rspq)) {
|
||||
do {
|
||||
fprintf (st, "Response ");
|
||||
tq_show_pkt (st, pkt);
|
||||
} while (pkt = tq_pkt[pkt].link);
|
||||
} while ((pkt = tq_pkt[pkt].link));
|
||||
}
|
||||
else fprintf (st, "Response queue is empty\n");
|
||||
}
|
||||
|
||||
@@ -490,7 +490,7 @@ do {
|
||||
fc = (fc - 1) & DMASK; /* decr wc */
|
||||
if (upd)
|
||||
msgrfc = fc;
|
||||
if (st = sim_tape_sprecf (uptr, &tbc)) /* space rec fwd, err? */
|
||||
if ((st = sim_tape_sprecf (uptr, &tbc))) /* space rec fwd, err? */
|
||||
return ts_map_status (st); /* map status */
|
||||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||||
} while (fc != 0);
|
||||
@@ -533,7 +533,7 @@ do {
|
||||
fc = (fc - 1) & DMASK; /* decr wc */
|
||||
if (upd)
|
||||
msgrfc = fc;
|
||||
if (st = sim_tape_sprecr (uptr, &tbc)) /* space rec rev, err? */
|
||||
if ((st = sim_tape_sprecr (uptr, &tbc))) /* space rec rev, err? */
|
||||
return ts_map_status (st); /* map status */
|
||||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||||
} while (fc != 0);
|
||||
@@ -666,7 +666,7 @@ else {
|
||||
return TC5;
|
||||
}
|
||||
}
|
||||
if (st = sim_tape_wrrecf (uptr, tsxb, fc)) /* write rec, err? */
|
||||
if ((st = sim_tape_wrrecf (uptr, tsxb, fc))) /* write rec, err? */
|
||||
return ts_map_status (st); /* return status */
|
||||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||||
msgrfc = 0;
|
||||
@@ -679,7 +679,7 @@ int32 ts_wtmk (UNIT *uptr)
|
||||
{
|
||||
t_stat st;
|
||||
|
||||
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
|
||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
||||
return ts_map_status (st); /* return status */
|
||||
msgxs0 = msgxs0 | XS0_MOT; /* tape has moved */
|
||||
if (sim_tape_eot (&ts_unit)) /* EOT on write? */
|
||||
|
||||
@@ -647,7 +647,7 @@ switch (fnc) { /* case on function */
|
||||
case FNC_SPACEF: /* space forward */
|
||||
do {
|
||||
tufc = (tufc + 1) & 0177777; /* incr fc */
|
||||
if (st = sim_tape_sprecf (uptr, &tbc)) { /* space rec fwd, err? */
|
||||
if ((st = sim_tape_sprecf (uptr, &tbc))) { /* space rec fwd, err? */
|
||||
r = tu_map_err (drv, st, 0); /* map error */
|
||||
break;
|
||||
}
|
||||
@@ -660,7 +660,7 @@ switch (fnc) { /* case on function */
|
||||
case FNC_SPACER: /* space reverse */
|
||||
do {
|
||||
tufc = (tufc + 1) & 0177777; /* incr wc */
|
||||
if (st = sim_tape_sprecr (uptr, &tbc)) { /* space rec rev, err? */
|
||||
if ((st = sim_tape_sprecr (uptr, &tbc))) { /* space rec rev, err? */
|
||||
r = tu_map_err (drv, st, 0); /* map error */
|
||||
break;
|
||||
}
|
||||
@@ -671,7 +671,7 @@ switch (fnc) { /* case on function */
|
||||
break;
|
||||
|
||||
case FNC_WREOF: /* write end of file */
|
||||
if (st = sim_tape_wrtmk (uptr)) /* write tmk, err? */
|
||||
if ((st = sim_tape_wrtmk (uptr))) /* write tmk, err? */
|
||||
r = tu_map_err (drv, st, 0); /* map error */
|
||||
break;
|
||||
|
||||
@@ -687,7 +687,7 @@ switch (fnc) { /* case on function */
|
||||
tufc = 0; /* clear frame count */
|
||||
if ((uptr->UDENS == TC_1600) && sim_tape_bot (uptr))
|
||||
tufs = tufs | FS_ID; /* PE BOT? ID burst */
|
||||
if (st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR)) { /* read fwd */
|
||||
if ((st = sim_tape_rdrecf (uptr, xbuf, &tbc, MT_MAXFR))) {/* read fwd */
|
||||
if (st == MTSE_TMK) /* tmk also sets FCE */
|
||||
tu_set_er (ER_FCE);
|
||||
r = tu_map_err (drv, st, 1); /* map error */
|
||||
@@ -739,7 +739,7 @@ switch (fnc) { /* case on function */
|
||||
}
|
||||
tbc = xbc;
|
||||
}
|
||||
if (st = sim_tape_wrrecf (uptr, xbuf, tbc)) /* write rec, err? */
|
||||
if ((st = sim_tape_wrrecf (uptr, xbuf, tbc))) /* write rec, err? */
|
||||
r = tu_map_err (drv, st, 1); /* map error */
|
||||
else {
|
||||
tufc = (tufc + tbc) & 0177777;
|
||||
@@ -751,7 +751,7 @@ switch (fnc) { /* case on function */
|
||||
case FNC_READR: /* read reverse */
|
||||
case FNC_WCHKR: /* wcheck = read */
|
||||
tufc = 0; /* clear frame count */
|
||||
if (st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR)) { /* read rev */
|
||||
if ((st = sim_tape_rdrecr (uptr, xbuf + 4, &tbc, MT_MAXFR))) {/* read rev */
|
||||
if (st == MTSE_TMK) /* tmk also sets FCE */
|
||||
tu_set_er (ER_FCE);
|
||||
r = tu_map_err (drv, st, 1); /* map error */
|
||||
|
||||
@@ -702,7 +702,7 @@ t_stat xq_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc)
|
||||
fprintf(st, "Filters:\n");
|
||||
for (i=0; i<XQ_FILTER_MAX; i++) {
|
||||
eth_mac_fmt((ETH_MAC*)xq->var->setup.macs[i], buffer);
|
||||
fprintf(st, " [%2d]: %s\n", i, buffer);
|
||||
fprintf(st, " [%2d]: %s\n", (int)i, buffer);
|
||||
}
|
||||
if (xq->var->setup.multicast)
|
||||
fprintf(st, "All Multicast Receive Mode\n");
|
||||
@@ -1187,7 +1187,7 @@ t_stat xq_process_setup(CTLR* xq)
|
||||
|
||||
xq->var->setup.multicast = (0 != (len & XQ_SETUP_MC));
|
||||
xq->var->setup.promiscuous = (0 != (len & XQ_SETUP_PM));
|
||||
if (led = (len & XQ_SETUP_LD) >> 2) {
|
||||
if ((led = (len & XQ_SETUP_LD) >> 2)) {
|
||||
switch (led) {
|
||||
case 1: xq->var->setup.l1 = 0; break;
|
||||
case 2: xq->var->setup.l2 = 0; break;
|
||||
@@ -2073,6 +2073,9 @@ t_stat xq_process_bootrom (CTLR* xq)
|
||||
/* set to next bdl (implicit chain) */
|
||||
xq->var->rbdl_ba += 12;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
} /* switch */
|
||||
|
||||
/* --------------------------- Done, finish up -----------------------------*/
|
||||
|
||||
@@ -1041,7 +1041,7 @@ void xu_process_receive(CTLR* xu)
|
||||
|
||||
sim_debug(DBG_TRC, xu->dev, "xu_process_receive(), buffers: %d\n", xu->var->rrlen);
|
||||
|
||||
/* xu_dump_rxring(xu); /* debug receive ring */
|
||||
/* xu_dump_rxring(xu); *//* debug receive ring */
|
||||
|
||||
/* process only when in the running state, and host buffers are available */
|
||||
if ((state != STATE_RUNNING) || no_buffers)
|
||||
@@ -1213,7 +1213,7 @@ void xu_process_transmit(CTLR* xu)
|
||||
t_stat rstatus, wstatus;
|
||||
|
||||
sim_debug(DBG_TRC, xu->dev, "xu_process_transmit()\n");
|
||||
/* xu_dump_txring(xu); /* debug receive ring */
|
||||
/* xu_dump_txring(xu); *//* debug receive ring */
|
||||
|
||||
for (;;) {
|
||||
|
||||
|
||||
Reference in New Issue
Block a user