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mirror of https://github.com/simh/simh.git synced 2026-01-11 23:52:58 +00:00

VAX: Move CPU register and routine declarations into vax_defs.h

Avoid redundant declarations in every simulator module that uses them
and allow compiler to validate consistency of declarations and definitions.
This commit is contained in:
Mark Pizzolato 2016-02-29 16:37:18 -08:00
parent 8d51b3517d
commit 253f8a8dcf
54 changed files with 149 additions and 370 deletions

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@ -325,6 +325,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -35,10 +35,6 @@ int32 int_req[IPL_HLVL] = { 0 }; /* intr, IPL 14-17 */
int32 int_vec_set[IPL_HLVL][32] = { 0 }; /* bits to set in vector */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 PSL, SISR, trpirq, mem_err, hlt_pin;
extern int32 p1;
extern jmp_buf save_env;
int32 eval_int (void);
t_stat qba_reset (DEVICE *dptr);
const char *qba_description (DEVICE *dptr);

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@ -35,8 +35,6 @@
#define MCSR_ECR 0x4000 /* extended CSR read enable */
#define MCSR_RW (MCSR_ECR|MCSR_WWP|MCSR_PEN)
extern UNIT cpu_unit;
int32 mctl_csr[MAX_MCTL_COUNT];
int32 mctl_count = 0;

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@ -68,11 +68,6 @@
#define CLK_DELAY 5000 /* 100 Hz */
#define TMXR_MULT 1 /* 100 Hz */
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
extern jmp_buf save_env;
extern int32 p1;
int32 tti_csr = 0; /* control/status */
uint32 tti_buftime; /* time input character arrived */
int32 tto_csr = 0; /* control/status */

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@ -48,13 +48,6 @@ struct boot_dev {
int32 code;
};
extern int32 R[16];
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 int_req[IPL_HLVL];
extern jmp_buf save_env;
extern int32 p1;
extern int32 trpirq, mem_err;
extern DEVICE vc_dev, lk_dev, vs_dev;
int32 conisp, conpc, conpsl; /* console reg */
@ -72,9 +65,7 @@ t_stat sysd_reset (DEVICE *dptr);
const char *sysd_description (DEVICE *dptr);
t_stat vax610_boot (int32 flag, char *ptr);
t_stat vax610_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 vc_mem_rd (int32 pa);
extern void vc_mem_wr (int32 pa, int32 val, int32 lnt);
extern int32 iccs_rd (void);
@ -88,7 +79,6 @@ extern void rxcs_wr (int32 dat);
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern int32 eval_int (void);
/* SYSD data structures

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@ -59,9 +59,6 @@ extern DEVICE vc_dev;
extern DEVICE lk_dev;
extern DEVICE vs_dev;
extern void WriteB (uint32 pa, int32 val);
extern UNIT cpu_unit;
DEVICE *sim_devices[] = {
&cpu_dev,
&mctl_dev,

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@ -381,6 +381,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -73,12 +73,6 @@ int32 qb_ipc = 0; /* IPC */
int32 qb_map[QBNMAPR] = { 0 }; /* map registers */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 R[16];
extern uint32 *M;
extern UNIT cpu_unit;
extern int32 PSL, SISR, trpirq, mem_err, hlt_pin;
extern int32 p1;
extern jmp_buf save_env;
extern int32 ka_mser; /* KA630 mem sys err */
t_stat dbl_rd (int32 *data, int32 addr, int32 access);

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@ -48,9 +48,6 @@
#define CLK_DELAY 5000 /* 100 Hz */
#define TMXR_MULT 1 /* 100 Hz */
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
int32 tti_csr = 0; /* control/status */
uint32 tti_buftime; /* time input character arrived */
int32 tto_csr = 0; /* control/status */

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@ -121,23 +121,7 @@ CTAB vax630_cmd[] = {
#define DEAR_LMADD 0x00007FFF /* local mem addr */
#define DEAR_RD (DEAR_LMADD)
extern int32 R[16];
extern int32 STK[5];
extern int32 PSL;
extern int32 SISR;
extern int32 SCBB;
extern int32 mapen;
extern int32 pcq[PCQ_SIZE];
extern int32 pcq_p;
extern int32 ibcnt, ppc;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 fault_PC;
extern int32 int_req[IPL_HLVL];
extern UNIT cpu_unit;
extern UNIT clk_unit;
extern jmp_buf save_env;
extern int32 p1;
extern int32 tmr_poll;
extern DEVICE vc_dev, lk_dev, vs_dev;
@ -178,7 +162,6 @@ void ka_wr (int32 pa, int32 val, int32 lnt);
t_stat sysd_powerup (void);
int32 con_halt (int32 code, int32 cc);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 qbmap_rd (int32 pa);
extern void qbmap_wr (int32 pa, int32 val, int32 lnt);
extern int32 qbmem_rd (int32 pa);

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@ -70,10 +70,6 @@ extern DEVICE vc_dev;
extern DEVICE lk_dev;
extern DEVICE vs_dev;
extern void WriteB (uint32 pa, int32 val);
extern void rom_wr_B (int32 pa, int32 val);
extern UNIT cpu_unit;
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,

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@ -341,6 +341,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -65,8 +65,6 @@
#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1)
extern UNIT cpu_unit;
uint32 mcsr0 = 0;
uint32 mcsr1 = 0;
uint32 mcsr2 = 0;

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@ -197,8 +197,6 @@
#define DBG_RD 0x0004 /* disk reads */
#define DBG_WR 0x0008 /* disk writes */
extern int32 int_req[IPL_HLVL];
uint16 *rbxb = NULL; /* xfer buffer */
int32 rbcs = 0; /* control/status */
int32 rbba = 0; /* memory address */

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@ -185,8 +185,6 @@ typedef struct todr_battery_info TOY;
int32 td_regval; /* temp location used in reg declarations */
extern jmp_buf save_env;
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat clk_svc (UNIT *uptr);

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@ -68,24 +68,13 @@ static struct boot_dev boot_tab[] = {
{ NULL }
};
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern int32 mapen, pme, trpirq;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 crd_err, mem_err, hlt_pin;
extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int;
extern jmp_buf save_env;
extern int32 p1;
t_stat sysb_reset (DEVICE *dptr);
const char *sysb_description (DEVICE *dptr);
t_stat vax730_boot (int32 flag, char *ptr);
t_stat vax730_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 iccs_rd (void);
extern int32 nicr_rd (void);
extern int32 icr_rd (t_bool interp);

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@ -55,9 +55,6 @@ extern DEVICE vh_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev;
extern UNIT cpu_unit;
extern void WriteB (uint32 pa, int32 val);
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,

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@ -93,11 +93,7 @@ uint32 uba_fmer = 0; /* failing map reg */
uint32 uba_map[UBA_NMAPR] = { 0 }; /* map registers */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 trpirq;
extern int32 autcon_enb;
extern jmp_buf save_env;
extern UNIT cpu_unit;
extern int32 p1;
t_stat uba_reset (DEVICE *dptr);
const char *uba_description (DEVICE *dptr);

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@ -83,28 +83,17 @@ uint32 vax750_wcsmem[16384];
static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
extern int32 R[16];
extern int32 PSL;
extern uint32 rom[ROMSIZE/sizeof(uint32)]; /* boot ROM */
extern int32 ASTLVL, SISR;
extern int32 mapen, pme, trpirq;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 crd_err, mem_err, hlt_pin;
extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int;
extern jmp_buf save_env;
extern int32 p1;
t_stat cmi_reset (DEVICE *dptr);
const char *cmi_description (DEVICE *dptr);
void cmi_set_tmo (void);
t_stat vax750_boot (int32 flag, char *ptr);
t_stat vax750_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
t_stat vax750_set_bootdev (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat vax750_show_bootdev (FILE *st, UNIT *uptr, int32 val, void *desc);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 iccs_rd (void);
extern int32 nicr_rd (void);
extern int32 icr_rd (t_bool interp);

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@ -381,6 +381,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -90,8 +90,6 @@
#define MEM_256K_MASK 0x5555
#define MEM_BOARD_MASK_256K(x) ((((1u << (uint32)(x/MEM_SIZE_256K)) - 1) & MEM_256K_MASK) | MCSR2_CS256)
extern UNIT cpu_unit;
uint32 mcsr0 = 0;
uint32 mcsr1 = 0;
uint32 mcsr2 = 0;

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@ -175,8 +175,6 @@ typedef struct todr_battery_info TOY;
int32 td_regval; /* temp location used in reg declarations */
extern jmp_buf save_env;
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat clk_svc (UNIT *uptr);

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@ -57,10 +57,6 @@ extern DEVICE vh_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev;
extern void WriteB (uint32 pa, int32 val);
extern void rom_wr_B (int32 pa, int32 val);
extern UNIT cpu_unit;
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,

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@ -98,14 +98,8 @@ uint32 uba_dpr[UBA_NDPATH] = { 0 }; /* number data paths */
uint32 uba_map[UBA_NMAPR] = { 0 }; /* map registers */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 trpirq;
extern int32 autcon_enb;
extern jmp_buf save_env;
extern UNIT cpu_unit;
extern uint32 nexus_req[NEXUS_HLVL];
extern int32 p1;
extern int32 fault_PC; /* fault PC */
extern int32 mem_err;
t_stat uba_reset (DEVICE *dptr);
const char *uba_description (DEVICE *dptr);

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@ -394,6 +394,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -77,7 +77,6 @@
#define DE_SIZE 7 /* entry size in words */
#define DE_GET_STAT(x) (((x) >> 8) & 0377)
extern UNIT cpu_unit;
extern UNIT fl_unit;
t_bool rtfile_parse (char *pntr, uint16 *file_name);

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@ -88,8 +88,6 @@ uint32 mcr_c[MCTL_NUM];
uint32 mcr_d[MCTL_NUM];
uint32 rom_lw[MCTL_NUM][ROMSIZE >> 2];
extern UNIT cpu_unit;
t_stat mctl_reset (DEVICE *dptr);
const char *mctl_description (DEVICE *dptr);
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);

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@ -128,16 +128,7 @@ static struct boot_dev boot_tab[] = {
{ NULL }
};
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern int32 mapen, pme, trpirq;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 crd_err, mem_err, hlt_pin;
extern int32 tmr_int, tti_int, tto_int;
extern jmp_buf save_env;
extern int32 p1;
t_stat sbi_reset (DEVICE *dptr);
const char *sbi_description (DEVICE *dptr);
@ -145,10 +136,8 @@ void sbi_set_tmo (int32 pa);
void uba_eval_int (void);
t_stat vax780_boot (int32 flag, char *ptr);
t_stat vax780_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern t_stat vax780_fload (int32 flag, char *cptr);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 iccs_rd (void);
extern int32 nicr_rd (void);
extern int32 icr_rd (void);

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@ -219,8 +219,6 @@ int32 fl_bptr = 0; /* buffer pointer */
uint8 comm_region[COMM_LNT] = { 0 }; /* comm region */
extern jmp_buf save_env;
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat clk_svc (UNIT *uptr);

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@ -64,10 +64,6 @@ extern DEVICE vh_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev;
extern UNIT cpu_unit;
extern void WriteB (uint32 pa, int32 val);
extern void rom_wr_B (int32 pa, int32 val);
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,

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@ -177,10 +177,7 @@ uint32 uba_aitime = 250; /* adapter init time */
uint32 uba_uitime = 12250; /* Unibus init time */
int32 autcon_enb = 1; /* autoconfig enable */
extern int32 trpirq;
extern int32 autcon_enb;
extern jmp_buf save_env;
extern UNIT cpu_unit;
extern uint32 nexus_req[NEXUS_HLVL];
t_stat uba_svc (UNIT *uptr);

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@ -252,7 +252,6 @@ uint32 mba_smr[MBA_NUM]; /* sel map reg */
uint32 mba_map[MBA_NUM][MBA_NMAPR]; /* map */
extern uint32 nexus_req[NEXUS_HLVL];
extern UNIT cpu_unit;
t_stat mba_reset (DEVICE *dptr);
t_stat mba_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);

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@ -107,31 +107,18 @@ static struct boot_dev boot_tab[] = {
{ NULL }
};
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern int32 mapen, pme, trpirq;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 crd_err, mem_err, hlt_pin;
extern int32 tmr_int, tti_int, tto_int, csi_int;
extern uint32 sbi_er;
extern jmp_buf save_env;
extern int32 p1;
extern int32 fault_PC; /* fault PC */
extern UNIT cpu_unit;
void uba_eval_int (void);
t_stat abus_reset (DEVICE *dptr);
const char *abus_description (DEVICE *dptr);
t_stat vax860_boot (int32 flag, char *ptr);
t_stat vax860_boot_parse (int32 flag, char *ptr);
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
void init_pamm (void);
extern t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
extern t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 iccs_rd (void);
extern int32 nicr_rd (void);
extern int32 icr_rd (t_bool interp);

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@ -424,6 +424,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */

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@ -80,17 +80,6 @@ uint32 sbi_er = 0; /* SBI error status */
uint32 sbi_tmo = 0; /* SBI timeout addr */
uint32 sbi_csr = 0; /* SBI control/status */
extern int32 R[16];
extern int32 PSL;
extern int32 ASTLVL, SISR;
extern jmp_buf save_env;
extern int32 trpirq;
extern int32 p1;
extern int32 mchk_ref;
extern int32 crd_err;
extern int32 fault_PC; /* fault PC */
extern UNIT cpu_unit;
t_stat sbia_reset (DEVICE *dptr);
const char *sbia_description (DEVICE *dptr);
void sbi_set_tmo (int32 pa);

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@ -233,10 +233,6 @@ int32 rlcs_mp = 0;
int32 rlcs_bcnt = 0; /* byte count */
uint16 *rlcs_buf = NULL;
extern jmp_buf save_env;
extern UNIT cpu_unit;
extern int32 brk_req;
t_stat tti_svc (UNIT *uptr);
t_stat tto_svc (UNIT *uptr);
t_stat clk_svc (UNIT *uptr);

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@ -64,9 +64,6 @@ extern DEVICE vh_dev;
extern DEVICE xu_dev, xub_dev;
extern DEVICE dmc_dev;
extern UNIT cpu_unit;
extern void WriteB (uint32 pa, int32 val);
DEVICE *sim_devices[] = {
&cpu_dev,
&tlb_dev,

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@ -74,14 +74,6 @@ typedef struct {
static DSTR Dstr_zero = { 0, {0, 0, 0, 0} };
static DSTR Dstr_one = { 0, {0x10, 0, 0, 0} };
extern int32 R[16];
extern int32 PSL;
extern int32 trpirq;
extern int32 p1;
extern int32 fault_PC;
extern int32 ibcnt, ppc;
extern jmp_buf save_env;
int32 ReadDstr (int32 lnt, int32 addr, DSTR *dec, int32 acc);
int32 WriteDstr (int32 lnt, int32 addr, DSTR *dec, int32 v, int32 acc);
int32 SetCCDstr (int32 lnt, DSTR *src, int32 pslv);
@ -1653,15 +1645,6 @@ return sign;
#else
extern int32 R[16];
extern int32 PSL;
extern int32 SCBB;
extern int32 fault_PC;
extern int32 ibcnt, ppc;
extern int32 pcq[PCQ_SIZE];
extern int32 pcq_p;
extern jmp_buf save_env;
/* CIS instructions - invoke emulator interface
opnd[0:5] = six operands to be pushed (if PSL<fpd> = 0)

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@ -49,18 +49,6 @@
#define CC_XOR_NV(x) ((((x) & CC_N) != 0) ^ (((x) & CC_V) != 0))
#define CC_XOR_NC(x) ((((x) & CC_N) != 0) ^ (((x) & CC_C) != 0))
extern int32 R[16];
extern int32 PSL;
extern int32 trpirq;
extern int32 p1;
extern int32 fault_PC;
extern int32 recq[]; /* recovery queue */
extern int32 recqptr; /* recq pointer */
extern int32 pcq[];
extern int32 pcq_p;
extern int32 ibcnt, ppc;
extern jmp_buf save_env;
int32 GeteaB (int32 spec);
int32 GeteaW (int32 spec);
int32 RdMemW (int32 a);
@ -1312,8 +1300,6 @@ return;
Should never get to instruction execution
*/
extern jmp_buf save_env;
t_bool BadCmPSL (int32 newpsl)
{
return TRUE; /* always bad */

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@ -182,7 +182,6 @@
#include "vax_defs.h"
#define OP_MEM -1
#define UNIT_V_CONH (UNIT_V_UF + 0) /* halt to console */
#define UNIT_V_MSIZE (UNIT_V_UF + 1) /* dummy */
#define UNIT_CONH (1u << UNIT_V_CONH)
@ -314,79 +313,8 @@ const uint32 align[4] = {
/* External and forward references */
extern t_stat build_dib_tab (void);
extern UNIT rom_unit, nvr_unit;
extern int32 sys_model;
extern int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_emul (int32 mpy, int32 mpc, int32 *rh);
extern int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_bb_n (int32 *opnd, int32 acc);
extern int32 op_bb_x (int32 *opnd, int32 newb, int32 acc);
extern int32 op_extv (int32 *opnd, int32 vfldrp1, int32 acc);
extern int32 op_ffs (uint32 fld, int32 size);
extern void op_insv (int32 *opnd, int32 vfldrp1, int32 acc);
extern int32 op_call (int32 *opnd, t_bool gs, int32 acc);
extern int32 op_ret (int32 acc);
extern int32 op_insque (int32 *opnd, int32 acc);
extern int32 op_remque (int32 *opnd, int32 acc);
extern int32 op_insqhi (int32 *opnd, int32 acc);
extern int32 op_insqti (int32 *opnd, int32 acc);
extern int32 op_remqhi (int32 *opnd, int32 acc);
extern int32 op_remqti (int32 *opnd, int32 acc);
extern void op_pushr (int32 *opnd, int32 acc);
extern void op_popr (int32 *opnd, int32 acc);
extern int32 op_movc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_cmpc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_locskp (int32 *opnd, int32 opc, int32 acc);
extern int32 op_scnspn (int32 *opnd, int32 opc, int32 acc);
extern int32 op_chm (int32 *opnd, int32 cc, int32 opc);
extern int32 op_rei (int32 acc);
extern void op_ldpctx (int32 acc);
extern void op_svpctx (int32 acc);
extern int32 op_probe (int32 *opnd, int32 opc);
extern int32 op_mtpr (int32 *opnd);
extern int32 op_mfpr (int32 *opnd);
extern int32 op_movfd (int32 val);
extern int32 op_movg (int32 val);
extern int32 op_mnegfd (int32 val);
extern int32 op_mnegg (int32 val);
extern int32 op_cmpfd (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cmpg (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cvtifdg (int32 val, int32 *rh, int32 opc);
extern int32 op_cvtfdgi (int32 *opnd, int32 *flg, int32 opc);
extern int32 op_cvtdf (int32 *opnd);
extern int32 op_cvtgf (int32 *opnd);
extern int32 op_cvtfg (int32 *opnd, int32 *rh);
extern int32 op_cvtgh (int32 *opnd, int32 *hflt);
extern int32 op_addf (int32 *opnd, t_bool sub);
extern int32 op_addd (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_addg (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_mulf (int32 *opnd);
extern int32 op_muld (int32 *opnd, int32 *rh);
extern int32 op_mulg (int32 *opnd, int32 *rh);
extern int32 op_divf (int32 *opnd);
extern int32 op_divd (int32 *opnd, int32 *rh);
extern int32 op_divg (int32 *opnd, int32 *rh);
extern int32 op_emodf (int32 *opnd, int32 *intgr, int32 *flg);
extern int32 op_emodd (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern int32 op_emodg (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern void op_polyf (int32 *opnd, int32 acc);
extern void op_polyd (int32 *opnd, int32 acc);
extern void op_polyg (int32 *opnd, int32 acc);
extern int32 op_cmode (int32 cc);
extern int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc);
extern int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 Test (uint32 va, int32 acc, int32 *status);
extern int32 BadCmPSL (int32 newpsl);
extern int32 eval_int (void);
extern int32 get_vector (int32 lvl);
extern void set_map_reg (void);
extern void rom_wr_B (int32 pa, int32 val);
extern int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta);
extern const uint16 drom[NUM_INST][MAX_SPEC + 1];
extern t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern int32 con_halt (int32 code, int32 cc);
extern const char *opcode[];
t_stat cpu_reset (DEVICE *dptr);
t_bool cpu_is_pc_a_subroutine_call (t_addr **ret_addrs);
@ -3550,8 +3478,6 @@ t_stat cpu_show_hist_records (FILE *st, t_bool do_header, int32 start, int32 cou
{
int32 i, k, numspec;
InstHistory *h;
extern const char *opcode[];
extern t_value *sim_eval;
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

View File

@ -82,37 +82,12 @@ static const uint8 rcnt[128] = {
12,16,16,20,16,20,20,24,16,20,20,24,20,24,24,28 /* 70 - 7F */
};
int32 last_chm = 0;
extern uint32 *M;
extern const uint32 byte_mask[33];
extern int32 R[16];
extern int32 STK[5];
extern int32 PSL;
extern int32 SCBB, PCBB, SBR, SLR;
extern int32 P0BR, P0LR, P1BR, P1LR;
extern int32 ASTLVL, SISR, mapen;
extern int32 pme;
extern int32 trpirq;
extern int32 p1, p2;
extern int32 fault_PC;
extern int32 pcq[PCQ_SIZE];
extern int32 pcq_p;
extern int32 in_ie;
extern int32 ibcnt, ppc;
extern DEVICE cpu_dev;
extern int32 Test (uint32 va, int32 acc, int32 *status);
extern void set_map_reg (void);
extern void zap_tb (int stb);
extern void zap_tb_ent (uint32 va);
extern t_bool chk_tb_ent (uint32 va);
extern int32 ReadIPR (int32 rg);
extern void WriteIPR (int32 rg, int32 val);
extern t_bool BadCmPSL (int32 newpsl);
extern jmp_buf save_env;
/* Branch on bit and no modify
Branch on bit and modify
@ -126,9 +101,10 @@ int32 op_bb_n (int32 *opnd, int32 acc)
{
int32 pos = opnd[0];
int32 rn = opnd[1];
int32 ea, by;
int32 ea;
int32 by;
if (rn >= 0) { /* register? */
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
return (R[rn] >> pos) & 1; /* get bit */
@ -143,9 +119,10 @@ int32 op_bb_x (int32 *opnd, int32 newb, int32 acc)
{
int32 pos = opnd[0];
int32 rn = opnd[1];
int32 ea, by, bit;
int32 ea;
int32 by, bit;
if (rn >= 0) { /* register? */
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
bit = (R[rn] >> pos) & 1; /* get bit */
@ -183,7 +160,7 @@ if (size == 0) /* size 0? field = 0 */
return 0;
if (size > 32) /* size > 32? fault */
RSVD_OPND_FAULT;
if (rn >= 0) { /* register? */
if (rn != OP_MEM) { /* register? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
if (((pos + size) > 32) && (rn >= nSP)) /* span 2 reg, PC? */
@ -227,7 +204,7 @@ if (size == 0) /* size = 0? done */
return;
if (size > 32) /* size > 32? fault */
RSVD_OPND_FAULT;
if (rn >= 0) { /* in registers? */
if (rn != OP_MEM) { /* in registers? */
if (((uint32) pos) > 31) /* pos > 31? fault */
RSVD_OPND_FAULT;
if ((pos + size) > 32) { /* span two reg? */
@ -573,13 +550,13 @@ p = Read (e + 4, L_LONG, RA); /* p <- (e+4) */
CC_CMP_L (s, p); /* set cc's */
if (e != p) { /* queue !empty? */
Read (s + 4, L_LONG, WA); /* wchk (s+4) */
if (opnd[1] < 0) /* wchk dest */
if (opnd[1] == OP_MEM) /* wchk dest */
Read (opnd[2], L_LONG, WA);
Write (p, s, L_LONG, WA); /* (p) <- s */
Write (s + 4, p, L_LONG, WA); /* (s+4) <- p */
}
else cc = cc | CC_V; /* else set v */
if (opnd[1] >= 0) /* store result */
if (opnd[1] != OP_MEM) /* store result */
R[opnd[1]] = e;
else Write (opnd[2], e, L_LONG, WA);
return cc;
@ -619,7 +596,8 @@ int32 op_insqhi (int32 *opnd, int32 acc)
{
int32 h = opnd[1];
int32 d = opnd[0];
int32 a, t;
int32 a;
int32 t;
if ((h == d) || ((h | d) & 07)) /* h, d quad align? */
RSVD_OPND_FAULT;
@ -644,7 +622,8 @@ int32 op_insqti (int32 *opnd, int32 acc)
{
int32 h = opnd[1];
int32 d = opnd[0];
int32 a, c, t;
int32 a, c;
int32 t;
if ((h == d) || ((h | d) & 07)) /* h, d quad align? */
RSVD_OPND_FAULT;
@ -701,11 +680,12 @@ return 0; /* q >= 2 entries */
int32 op_remqhi (int32 *opnd, int32 acc)
{
int32 h = opnd[0];
int32 ar, a, b, t;
int32 ar, a, b;
int32 t;
if (h & 07) /* h quad aligned? */
RSVD_OPND_FAULT;
if (opnd[1] < 0) { /* mem destination? */
if (opnd[1] == OP_MEM) { /* mem destination? */
if (h == opnd[2]) /* hdr = dst? */
RSVD_OPND_FAULT;
Read (opnd[2], L_LONG, WA); /* wchk dst */
@ -730,7 +710,7 @@ if (ar) { /* queue not empty? */
Write (b + 4, h - b, L_LONG, WA); /* (b+4) <- h-b, flt ok */
Write (h, b - h, L_LONG, WA); /* (h) <- b-h, rls int */
}
if (opnd[1] >= 0) /* store result */
if (opnd[1] != OP_MEM) /* store result */
R[opnd[1]] = a;
else Write (opnd[2], a, L_LONG, WA);
if (ar == 0) /* empty, cc = 0110 */
@ -741,11 +721,12 @@ return (b == h)? CC_Z: 0; /* if b = h, q empty */
int32 op_remqti (int32 *opnd, int32 acc)
{
int32 h = opnd[0];
int32 ar, b, c, t;
int32 ar, b, c;
int32 t;
if (h & 07) /* h quad aligned? */
RSVD_OPND_FAULT;
if (opnd[1] < 0) { /* mem destination? */
if (opnd[1] == OP_MEM) { /* mem destination? */
if (h == opnd[2]) /* hdr = dst? */
RSVD_OPND_FAULT;
Read (opnd[2], L_LONG, WA); /* wchk dst */
@ -781,7 +762,7 @@ if (ar) { /* queue not empty */
Write (h, ar, L_LONG, WA); /* release interlock */
}
else c = h; /* empty, result = h */
if (opnd[1] >= 0) /* store result */
if (opnd[1] != OP_MEM) /* store result */
R[opnd[1]] = c;
else Write (opnd[2], c, L_LONG, WA);
if (ar == 0) /* empty, cc = 0110 */
@ -1167,7 +1148,8 @@ int32 op_chm (int32 *opnd, int32 cc, int32 opc)
{
int32 mode = opc & PSL_M_MODE;
int32 cur = PSL_GETCUR (PSL);
int32 tsp, newpc, acc, sta;
int32 tsp, newpc, acc;
int32 sta;
if (PSL & PSL_IS)
ABORT (STOP_CHMFI);
@ -1191,7 +1173,6 @@ Write (tsp - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = tsp - 12; /* set new stk */
PSL = (mode << PSL_V_CUR) | (PSL & PSL_IPL) | /* set new PSL */
(cur << PSL_V_PRV); /* IPL unchanged */
last_chm = fault_PC;
JUMP (newpc & ~03); /* set new PC */
return 0; /* cc = 0 */
}

View File

@ -76,6 +76,7 @@
#define ABORT_ACV (-SCB_ACV) /* access violation */
#define ABORT_TNV (-SCB_TNV) /* transl not vaid */
#define ABORT(x) longjmp (save_env, (x)) /* abort */
extern jmp_buf save_env;
#define RSVD_INST_FAULT ABORT (ABORT_RESIN)
#define RSVD_ADDR_FAULT ABORT (ABORT_RESAD)
#define RSVD_OPND_FAULT ABORT (ABORT_RESOP)
@ -743,6 +744,9 @@ enum opcodes {
else cc = 0; \
if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C
/* Operand Memory vs Register Indicator */
#define OP_MEM 0xFFFFFFFF
#define VAX_IDLE_VMS 0x01
#define VAX_IDLE_ULT 0x02 /* Ultrix more recent versions */
#define VAX_IDLE_ULTOLD 0x04 /* Ultrix older versions */
@ -754,7 +758,113 @@ enum opcodes {
extern uint32 cpu_idle_mask; /* idle mask */
void cpu_idle (void);
/* CPU Register definitions */
extern int32 R[16]; /* registers */
extern int32 STK[5]; /* stack pointers */
extern int32 PSL; /* PSL */
extern int32 SCBB; /* SCB base */
extern int32 PCBB; /* PCB base */
extern int32 SBR, SLR; /* S0 mem mgt */ /* S0 mem mgt */
extern int32 P0BR, P0LR; /* P0 mem mgt */
extern int32 P1BR, P1LR; /* P1 mem mgt */
extern int32 ASTLVL; /* AST Level */
extern int32 SISR; /* swre int req */
extern int32 pme; /* perf mon enable */
extern int32 trpirq; /* trap/intr req */
extern int32 fault_PC; /* fault PC */
extern int32 p1, p2; /* fault parameters */
extern int32 recq[]; /* recovery queue */
extern int32 recqptr; /* recq pointer */
extern int32 pcq[PCQ_SIZE]; /* PC queue */
extern int32 pcq_p; /* PC queue ptr */
extern int32 in_ie; /* in exc, int */
extern int32 ibcnt, ppc; /* prefetch ctl */
extern int32 hlt_pin; /* HLT pin intr */
extern int32 mem_err;
extern int32 crd_err;
/* vax_cpu1.c externals */
extern int32 op_bb_n (int32 *opnd, int32 acc);
extern int32 op_bb_x (int32 *opnd, int32 newb, int32 acc);
extern int32 op_extv (int32 *opnd, int32 vfldrp1, int32 acc);
extern void op_insv (int32 *opnd, int32 vfldrp1, int32 acc);
extern int32 op_ffs (uint32 fld, int32 size);
extern int32 op_call (int32 *opnd, t_bool gs, int32 acc);
extern int32 op_ret (int32 acc);
extern int32 op_insque (int32 *opnd, int32 acc);
extern int32 op_remque (int32 *opnd, int32 acc);
extern int32 op_insqhi (int32 *opnd, int32 acc);
extern int32 op_insqti (int32 *opnd, int32 acc);
extern int32 op_remqhi (int32 *opnd, int32 acc);
extern int32 op_remqti (int32 *opnd, int32 acc);
extern void op_pushr (int32 *opnd, int32 acc);
extern void op_popr (int32 *opnd, int32 acc);
extern int32 op_movc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_cmpc (int32 *opnd, int32 opc, int32 acc);
extern int32 op_locskp (int32 *opnd, int32 opc, int32 acc);
extern int32 op_scnspn (int32 *opnd, int32 opc, int32 acc);
extern int32 op_chm (int32 *opnd, int32 cc, int32 opc);
extern int32 op_rei (int32 acc);
extern void op_ldpctx (int32 acc);
extern void op_svpctx (int32 acc);
extern int32 op_probe (int32 *opnd, int32 opc);
extern int32 op_mtpr (int32 *opnd);
extern int32 op_mfpr (int32 *opnd);
extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
/* vax_cis.c externals */
extern int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc);
/* vax_fpa.c externals */
extern int32 op_ashq (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_emul (int32 mpy, int32 mpc, int32 *rh);
extern int32 op_ediv (int32 *opnd, int32 *rh, int32 *flg);
extern int32 op_cmpfd (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cmpg (int32 h1, int32 l1, int32 h2, int32 l2);
extern int32 op_cvtifdg (int32 val, int32 *rh, int32 opc);
extern int32 op_cvtfdgi (int32 *opnd, int32 *flg, int32 opc);
extern int32 op_emodf (int32 *opnd, int32 *intgr, int32 *flg);
extern int32 op_emodd (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern int32 op_emodg (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
extern int32 op_movfd (int32 val);
extern int32 op_mnegfd (int32 val);
extern int32 op_movg (int32 val);
extern int32 op_mnegg (int32 val);
extern int32 op_cvtdf (int32 *opnd);
extern int32 op_cvtfg (int32 *opnd, int32 *rh);
extern int32 op_cvtgf (int32 *opnd);
extern int32 op_addf (int32 *opnd, t_bool sub);
extern int32 op_addd (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_addg (int32 *opnd, int32 *rh, t_bool sub);
extern int32 op_mulf (int32 *opnd);
extern int32 op_muld (int32 *opnd, int32 *rh);
extern int32 op_mulg (int32 *opnd, int32 *rh);
extern int32 op_divf (int32 *opnd);
extern int32 op_divd (int32 *opnd, int32 *rh);
extern int32 op_divg (int32 *opnd, int32 *rh);
extern void op_polyf (int32 *opnd, int32 acc);
extern void op_polyd (int32 *opnd, int32 acc);
extern void op_polyg (int32 *opnd, int32 acc);
/* vax_octa.c externals */
extern int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va);
/* vax_cmode.c externals */
extern int32 op_cmode (int32 cc);
extern int32 BadCmPSL (int32 newpsl);
/* vax_sys.c externals */
extern const uint16 drom[NUM_INST][MAX_SPEC + 1];
/* Model dependent definitions */
extern int32 eval_int (void);
extern int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta);
extern int32 get_vector (int32 lvl);
extern int32 con_halt (int32 code, int32 cc);
extern t_stat cpu_boot (int32 unitno, DEVICE *dptr);
extern t_stat build_dib_tab (void);
extern void rom_wr_B (int32 pa, int32 val);
#if defined (VAX_780)
#include "vax780_defs.h"

View File

@ -59,11 +59,6 @@
#include "vax_defs.h"
#include <setjmp.h>
extern int32 R[16];
extern int32 PSL;
extern int32 p1;
extern jmp_buf save_env;
#if defined (USE_INT64)
#define M64 0xFFFFFFFFFFFFFFFF /* 64b */

View File

@ -115,12 +115,7 @@ int32 cq_mbr = 0; /* MBR */
int32 cq_ipc = 0; /* IPC */
int32 autcon_enb = 1; /* autoconfig enable */
extern uint32 *M;
extern UNIT cpu_unit;
extern int32 PSL, SISR, trpirq, mem_err, crd_err, hlt_pin;
extern int32 p1;
extern int32 ssc_bto;
extern jmp_buf save_env;
extern int32 vc_mem_rd (int32 pa);
extern void vc_mem_wr (int32 pa, int32 val, int32 lnt);
extern uint32 *vc_buf;

View File

@ -53,16 +53,6 @@
#include "vax_mmu.h"
#include <setjmp.h>
extern uint32 *M;
extern int32 PSL;
extern int32 mapen;
extern int32 p1, p2;
extern int32 P0BR, P0LR;
extern int32 P1BR, P1LR;
extern int32 SBR, SLR;
extern int32 SISR;
extern jmp_buf save_env;
int32 d_p0br, d_p0lr; /* dynamic copies */
int32 d_p1br, d_p1lr; /* altered per ucode */
int32 d_sbr, d_slr;
@ -219,7 +209,7 @@ return stlb[tbi];
/* Utility routines */
extern void set_map_reg (void)
void set_map_reg (void)
{
d_p0br = P0BR & ~03;
d_p1br = (P1BR - 0x800000) & ~03; /* VA<30> >> 7 */
@ -227,7 +217,6 @@ d_sbr = (SBR - 0x1000000) & ~03; /* VA<31> >> 7 */
d_p0lr = (P0LR << 2);
d_p1lr = (P1LR << 2) + 0x800000; /* VA<30> >> 7 */
d_slr = (SLR << 2) + 0x1000000; /* VA<31> >> 7 */
return;
}
/* Zap process (0) or whole (1) tb */
@ -241,7 +230,6 @@ for (i = 0; i < VA_TBSIZE; i++) {
if (stb)
stlb[i].tag = stlb[i].pte = -1;
}
return;
}
/* Zap single tb entry corresponding to va */
@ -253,7 +241,6 @@ int32 tbi = VA_GETTBI (VA_GETVPN (va));
if (va & VA_S0)
stlb[tbi].tag = stlb[tbi].pte = -1;
else ptlb[tbi].tag = ptlb[tbi].pte = -1;
return;
}
/* Check for tlb entry corresponding to va */

View File

@ -57,8 +57,9 @@ typedef struct {
} TLBENT;
extern uint32 *M;
extern int32 mapen;
extern int32 mapen; /* map enable */
extern UNIT cpu_unit;
extern DEVICE cpu_dev;
extern int32 mchk_va, mchk_ref; /* for mcheck */
extern TLBENT stlb[VA_TBSIZE], ptlb[VA_TBSIZE];
@ -67,6 +68,10 @@ static const int32 insert[4] = {
0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF
};
extern void zap_tb (int stb);
extern void zap_tb_ent (uint32 va);
extern t_bool chk_tb_ent (uint32 va);
extern void set_map_reg (void);
extern int32 ReadIO (uint32 pa, int32 lnt);
extern void WriteIO (uint32 pa, int32 val, int32 lnt);
extern int32 ReadReg (uint32 pa, int32 lnt);

View File

@ -48,14 +48,6 @@
#if defined (FULL_VAX)
extern int32 R[16];
extern int32 PSL;
extern int32 trpirq;
extern int32 p1;
extern jmp_buf save_env;
extern int32 Test (uint32 va, int32 acc, int32 *status);
#define WORDSWAP(x) ((((x) & WMASK) << 16) | (((x) >> 16) & WMASK))
typedef struct {
@ -1251,8 +1243,6 @@ return;
#else
extern jmp_buf save_env;
int32 op_octa (int32 *opnd, int32 cc, int32 opc, int32 acc, int32 spec, int32 va)
{
RSVD_INST_FAULT;

View File

@ -93,9 +93,6 @@
#define CLK_DELAY 5000 /* 100 Hz */
#define TMXR_MULT 1 /* 100 Hz */
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
int32 tti_csr = 0; /* control/status */
uint32 tti_buftime; /* time input character arrived */
int32 tto_csr = 0; /* control/status */

View File

@ -53,10 +53,7 @@
#define ODC(x) ((x) << DR_V_USPMASK)
#endif
extern UNIT cpu_unit;
extern REG cpu_reg[];
extern int32 saved_PC;
extern int32 PSL;
t_stat fprint_sym_m (FILE *of, uint32 addr, t_value *val);
int32 fprint_sym_qoimm (FILE *of, t_value *val, int32 vp, int32 lnt);

View File

@ -32,7 +32,6 @@
*/
#include "vax_defs.h"
#include <ctype.h>
/* Symbol tables */
/* Warning: for literals, the class number MUST equal the field width!! */

View File

@ -189,22 +189,7 @@ CTAB vax_cmd[] = {
#define SSCADS_MASK 0x3FFFFFFC /* match or mask */
extern int32 R[16];
extern int32 STK[5];
extern int32 PSL;
extern int32 SISR;
extern int32 mapen;
extern int32 pcq[PCQ_SIZE];
extern int32 pcq_p;
extern int32 ibcnt, ppc;
extern int32 in_ie;
extern int32 mchk_va, mchk_ref;
extern int32 fault_PC;
extern int32 int_req[IPL_HLVL];
extern UNIT cpu_unit;
extern UNIT clk_unit;
extern jmp_buf save_env;
extern int32 p1;
extern int32 MSER;
extern int32 tmr_poll;
extern DEVICE vc_dev, lk_dev, vs_dev;

View File

@ -62,8 +62,6 @@ extern DEVICE vc_dev;
extern DEVICE lk_dev;
extern DEVICE vs_dev;
extern void WriteB (uint32 pa, int32 val);
extern void rom_wr_B (int32 pa, int32 val);
extern UNIT cpu_unit;
DEVICE *sim_devices[] = {

View File

@ -193,7 +193,6 @@ BITFIELD vc_ic_mode_bits[] = {
#define IOLN_QVSS 0100
extern int32 int_req[IPL_HLVL];
extern int32 tmxr_poll; /* calibrated delay */
extern t_stat lk_wr (uint8 c);
@ -666,9 +665,6 @@ switch (rg) {
return SCPE_OK;
}
extern jmp_buf save_env;
extern int32 p1;
int32 vc_mem_rd (int32 pa)
{
uint32 rg = (pa >> 2) & 0xFFFF;

View File

@ -431,6 +431,7 @@ typedef struct {
#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */