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IMDS-225: Initial check in of new experimental simulator for the Intel MDS-225 IPC
This commit is contained in:
Bill Beech
committed by
Mark Pizzolato
Mark Pizzolato
parent
cdb94a9d9f
commit
27e65d1fa9
125
Intel-Systems/common/ioc-cont.c
Normal file
125
Intel-Systems/common/ioc-cont.c
Normal file
@@ -0,0 +1,125 @@
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/* ioc-cont.c: Intel IPC DBB adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
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||||
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MODIFICATIONS:
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27 Jun 16 - Original file.
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NOTES:
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*/
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#include "system_defs.h" /* system header in system dir */
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/* function prototypes */
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uint8 ioc_cont(t_bool io, uint8 data, uint8 devnum); /* ioc_cont*/
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t_stat ioc_cont_reset (DEVICE *dptr, uint16 base, uint8 devnum);
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);
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extern uint32 saved_PC; /* program counter */
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/* globals */
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UNIT ioc_cont_unit[] = {
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{ UDATA (0, 0, 0) }, /* ioc_cont*/
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};
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REG ioc_cont_reg[] = {
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{ HRDATA (CONTROL0, ioc_cont_unit[0].u3, 8) }, /* ioc_cont */
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{ NULL }
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};
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DEBTAB ioc_cont_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE ioc_cont_dev = {
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"IOC-CONT", //name
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ioc_cont_unit, //units
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ioc_cont_reg, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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// &ioc_cont_reset, //reset
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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ioc_cont_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* IOC control port functions */
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uint8 ioc_cont(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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sim_printf(" ioc_cont: read data=%02X port=%02X returned 0x00 from PC=%04X\n", data, devnum, saved_PC);
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return 0x00;
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} else { /* write control port */
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sim_printf(" ioc_cont: data=%02X port=%02X\n", data, devnum);
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}
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}
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/* Reset routine */
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t_stat ioc_cont_reset(DEVICE *dptr, uint16 base, uint8 devnum)
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{
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reg_dev(ioc_cont, base, devnum);
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reg_dev(ioc_cont, base + 1, devnum);
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ioc_cont_unit[devnum].u3 = 0x00; /* ipc reset */
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sim_printf(" ioc_cont[%d]: Reset\n", devnum);
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sim_printf(" ioc_cont[%d]: Registered at %04X\n", devnum, base);
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return SCPE_OK;
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}
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/* end of ioc-cont.c */
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160
Intel-Systems/common/ipc-cont.c
Normal file
160
Intel-Systems/common/ipc-cont.c
Normal file
@@ -0,0 +1,160 @@
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/* ipc-cont.c: Intel IPC control port PIO adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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07 Jun 16 - Original file.
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NOTES:
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*/
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#include "system_defs.h" /* system header in system dir */
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/* function prototypes */
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uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum); /* ipc_cont*/
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t_stat ipc_cont_reset (DEVICE *dptr, uint16 base, uint8 devnum);
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/* external function prototypes */
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);
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/* globals */
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UNIT ipc_cont_unit[] = {
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{ UDATA (0, 0, 0) }, /* ipc_cont*/
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};
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REG ipc_cont_reg[] = {
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{ HRDATA (CONTROL0, ipc_cont_unit[0].u3, 8) }, /* ipc_cont */
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{ NULL }
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};
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DEBTAB ipc_cont_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE ipc_cont_dev = {
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"IPC-CONT", //name
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ipc_cont_unit, //units
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ipc_cont_reg, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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// &ipc_cont_reset, //reset
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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ipc_cont_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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/* IPC control port functions */
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uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum)
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{
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if (io == 0) { /* read status port */
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sim_printf(" ipc_cont: read data=%02X port=%02X returned 0xFF\n", ipc_cont_unit[devnum].u3, devnum);
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return ipc_cont_unit[devnum].u3;
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} else { /* write control port */
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//this simulates an 74ls259 register
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//d0-d2 address the reg(in reverse order!), d3 is the data to be latched
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switch(data & 0x07) {
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case 5: //interrupt enable
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if(data & 0x08) //bit high
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ipc_cont_unit[0].u3 |= 0x10;
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else //bit low
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ipc_cont_unit[0].u3 &= 0xEF;
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break;
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case 4: //*selboot
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if(data & 0x08) //bit high
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ipc_cont_unit[0].u3 |= 0x08;
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else //bit low
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ipc_cont_unit[0].u3 &= 0xF7;
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break;
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case 2: //*startup
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if(data & 0x08) //bit high
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ipc_cont_unit[0].u3 |= 0x04;
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else //bit low
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ipc_cont_unit[0].u3 &= 0xFB;
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break;
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case 1: //over ride
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if(data & 0x08) //bit high
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ipc_cont_unit[0].u3 |= 0x02;
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else //bit low
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ipc_cont_unit[0].u3 &= 0xFD;
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break;
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case 0: //aux prom enable
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if(data & 0x08) //bit high
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ipc_cont_unit[0].u3 |= 0x01;
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else //bit low
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ipc_cont_unit[0].u3 &= 0xFE;
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break;
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default:
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break;
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}
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sim_printf(" ipc_cont: data=%02X ipc_cont[%d]=%02X\n", data, devnum, ipc_cont_unit[0].u3);
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}
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return 0;
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}
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/* Reset routine */
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t_stat ipc_cont_reset(DEVICE *dptr, uint16 base, uint8 devnum)
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{
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reg_dev(ipc_cont, base, devnum);
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ipc_cont_unit[devnum].u3 = 0x00; /* ipc reset */
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sim_printf(" ipc_cont[%d]: Reset\n", devnum);
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sim_printf(" ipc_cont[%d]: Registered at %04X\n", devnum, base);
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return SCPE_OK;
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}
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/* end of ipc-cont.c */
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187
Intel-Systems/common/ipceprom.c
Normal file
187
Intel-Systems/common/ipceprom.c
Normal file
@@ -0,0 +1,187 @@
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/* iEPROM.c: Intel EPROM simulator for 8-bit SBCs
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
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MODIFICATIONS:
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
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24 Apr 15 -- Modified to use simh_debug
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NOTES:
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These functions support a simulated ROM devices on an iSBC-80/XX SBCs.
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This allows the attachment of the device to a binary file containing the EPROM
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code image. Unit will support a single 2708, 2716, 2732, or 2764 type EPROM.
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These functions also support bit 1 of 8255 number 1, port B, to enable/
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disable the onboard ROM.
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*/
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#include "system_defs.h"
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#define SET_XACK(VAL) (xack = VAL)
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/* function prototypes */
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t_stat EPROM_attach (UNIT *uptr, CONST char *cptr);
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t_stat EPROM_reset (DEVICE *dptr, uint16 size);
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uint8 EPROM_get_mbyte(uint16 addr);
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/* external function prototypes */
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extern uint8 xack; /* XACK signal */
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/* SIMH EPROM Standard I/O Data Structures */
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UNIT EPROM_unit = {
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UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO, 0), 0
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};
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DEBTAB EPROM_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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DEVICE EPROM_dev = {
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"EPROM", //name
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&EPROM_unit, //units
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NULL, //registers
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NULL, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
|
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NULL, //deposit
|
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// &EPROM_reset, //reset
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NULL, //reset
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NULL, //boot
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&EPROM_attach, //attach
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NULL, //detach
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NULL, //ctxt
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DEV_DEBUG, //flags
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0, //dctrl
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EPROM_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* global variables */
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|
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/* EPROM functions */
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/* EPROM attach */
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t_stat EPROM_attach (UNIT *uptr, CONST char *cptr)
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{
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uint16 j;
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int c;
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FILE *fp;
|
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t_stat r;
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sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: cptr=%s\n", cptr);
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if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
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sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Error\n");
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return r;
|
||||
}
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sim_debug (DEBUG_read, &EPROM_dev, "\tAllocate buffer\n");
|
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if (EPROM_unit.filebuf == NULL) { /* no buffer allocated */
|
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EPROM_unit.filebuf = malloc(EPROM_unit.capac); /* allocate EPROM buffer */
|
||||
if (EPROM_unit.filebuf == NULL) {
|
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sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Malloc error\n");
|
||||
return SCPE_MEM;
|
||||
}
|
||||
}
|
||||
sim_debug (DEBUG_read, &EPROM_dev, "\tOpen file %s\n", EPROM_unit.filename);
|
||||
fp = fopen(EPROM_unit.filename, "rb"); /* open EPROM file */
|
||||
if (fp == NULL) {
|
||||
sim_printf("EPROM: Unable to open ROM file %s\n", EPROM_unit.filename);
|
||||
sim_printf("\tNo ROM image loaded!!!\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
sim_debug (DEBUG_read, &EPROM_dev, "\tRead file\n");
|
||||
j = 0; /* load EPROM file */
|
||||
c = fgetc(fp);
|
||||
while (c != EOF) {
|
||||
*((uint8 *)EPROM_unit.filebuf + j++) = c & 0xFF;
|
||||
c = fgetc(fp);
|
||||
if (j > EPROM_unit.capac) {
|
||||
sim_printf("\tImage is too large - Load truncated!!!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
sim_printf("\tImage size=%04X unit_capac=%04X\n", j, EPROM_unit.capac);
|
||||
sim_debug (DEBUG_read, &EPROM_dev, "\tClose file\n");
|
||||
fclose(fp);
|
||||
sim_printf("EPROM: %d bytes of ROM image %s loaded\n", j, EPROM_unit.filename);
|
||||
sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Done\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* EPROM reset */
|
||||
|
||||
t_stat EPROM_reset (DEVICE *dptr, uint16 size)
|
||||
{
|
||||
// sim_debug (DEBUG_flow, &EPROM_dev, " EPROM_reset: base=0000 size=%04X\n", size);
|
||||
if ((EPROM_unit.flags & UNIT_ATT) == 0) { /* if unattached */
|
||||
EPROM_unit.capac = size; /* set EPROM size to 0 */
|
||||
sim_debug (DEBUG_flow, &EPROM_dev, "Done1\n");
|
||||
// sim_printf(" EPROM: Available [%04X-%04XH]\n",
|
||||
// 0, EPROM_unit.capac - 1);
|
||||
return SCPE_OK;
|
||||
}
|
||||
if ((EPROM_unit.flags & UNIT_ATT) == 0) {
|
||||
sim_printf("EPROM: No file attached\n");
|
||||
}
|
||||
sim_debug (DEBUG_flow, &EPROM_dev, "Done2\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* get a byte from memory */
|
||||
|
||||
uint8 EPROM_get_mbyte(uint16 addr)
|
||||
{
|
||||
uint8 val;
|
||||
|
||||
sim_debug (DEBUG_read, &EPROM_dev, "EPROM_get_mbyte: addr=%04X\n", addr);
|
||||
if (addr < EPROM_unit.capac) {
|
||||
SET_XACK(1); /* good memory address */
|
||||
sim_debug (DEBUG_xack, &EPROM_dev, "EPROM_get_mbyte: Set XACK for %04X\n", addr);
|
||||
val = *((uint8 *)EPROM_unit.filebuf + addr);
|
||||
sim_debug (DEBUG_read, &EPROM_dev, " val=%04X\n", val);
|
||||
return (val & 0xFF);
|
||||
}
|
||||
sim_debug (DEBUG_read, &EPROM_dev, " Out of range\n");
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
/* end of iEPROM.c */
|
||||
258
Intel-Systems/common/ipcmultibus.c
Normal file
258
Intel-Systems/common/ipcmultibus.c
Normal file
@@ -0,0 +1,258 @@
|
||||
/* ipcmultibus.c: Multibus I simulator
|
||||
|
||||
Copyright (c) 2010, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
MODIFICATIONS:
|
||||
|
||||
?? ??? 10 - Original file.
|
||||
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
||||
24 Apr 15 -- Modified to use simh_debug
|
||||
|
||||
NOTES:
|
||||
|
||||
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
|
||||
Computer Systems.
|
||||
|
||||
*/
|
||||
|
||||
#include "system_defs.h"
|
||||
|
||||
#define SET_XACK(VAL) (xack = VAL)
|
||||
|
||||
int32 mbirq = 0; /* set no multibus interrupts */
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
t_stat multibus_svc(UNIT *uptr);
|
||||
t_stat multibus_reset(DEVICE *dptr);
|
||||
void set_irq(int32 int_num);
|
||||
void clr_irq(int32 int_num);
|
||||
uint8 nulldev(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum);
|
||||
t_stat multibus_reset (DEVICE *dptr);
|
||||
uint8 multibus_get_mbyte(uint16 addr);
|
||||
void multibus_put_mbyte(uint16 addr, uint8 val);
|
||||
|
||||
/* external function prototypes */
|
||||
|
||||
extern t_stat SBC_reset(DEVICE *dptr); /* reset the IPC simulator */
|
||||
extern void set_cpuint(int32 int_num);
|
||||
extern UNIT zx200a_unit;
|
||||
extern t_stat zx200a_reset(DEVICE *dptr, uint16 base, uint8 devnum);
|
||||
|
||||
/* external globals */
|
||||
|
||||
extern uint8 xack; /* XACK signal */
|
||||
extern int32 int_req; /* i8080 INT signal */
|
||||
|
||||
/* multibus Standard SIMH Device Data Structures */
|
||||
|
||||
UNIT multibus_unit = {
|
||||
UDATA (&multibus_svc, 0, 0), 20
|
||||
};
|
||||
|
||||
REG multibus_reg[] = {
|
||||
{ HRDATA (MBIRQ, mbirq, 32) },
|
||||
{ HRDATA (XACK, xack, 8) }
|
||||
};
|
||||
|
||||
DEBTAB multibus_debug[] = {
|
||||
{ "ALL", DEBUG_all },
|
||||
{ "FLOW", DEBUG_flow },
|
||||
{ "READ", DEBUG_read },
|
||||
{ "WRITE", DEBUG_write },
|
||||
{ "LEV1", DEBUG_level1 },
|
||||
{ "LEV2", DEBUG_level2 },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
DEVICE multibus_dev = {
|
||||
"MBIRQ", //name
|
||||
&multibus_unit, //units
|
||||
multibus_reg, //registers
|
||||
NULL, //modifiers
|
||||
1, //numunits
|
||||
16, //aradix
|
||||
16, //awidth
|
||||
1, //aincr
|
||||
16, //dradix
|
||||
8, //dwidth
|
||||
NULL, //examine
|
||||
NULL, //deposit
|
||||
&multibus_reset, //reset
|
||||
NULL, //boot
|
||||
NULL, //attach
|
||||
NULL, //detach
|
||||
NULL, //ctxt
|
||||
DEV_DEBUG, //flags
|
||||
0, //dctrl
|
||||
multibus_debug, //debflags
|
||||
NULL, //msize
|
||||
NULL //lname
|
||||
};
|
||||
|
||||
/* Service routines to handle simulator functions */
|
||||
|
||||
/* service routine - actually does the simulated interrupts */
|
||||
|
||||
t_stat multibus_svc(UNIT *uptr)
|
||||
{
|
||||
switch (mbirq) {
|
||||
case INT_1:
|
||||
set_cpuint(INT_R);
|
||||
#if NIPC
|
||||
clr_irq(SBC202_INT); /***** bad, bad, bad! */
|
||||
#endif
|
||||
// sim_printf("multibus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req);
|
||||
break;
|
||||
default:
|
||||
// sim_printf("multibus_svc: default mbirq=%04X\n", mbirq);
|
||||
break;
|
||||
}
|
||||
sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat multibus_reset(DEVICE *dptr)
|
||||
{
|
||||
SBC_reset(NULL);
|
||||
zx200a_reset(NULL, ZX200A_BASE_DD, 0);
|
||||
zx200a_reset(NULL, ZX200A_BASE_SD, 0);
|
||||
sim_printf(" Multibus: Reset\n");
|
||||
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
void set_irq(int32 int_num)
|
||||
{
|
||||
mbirq |= int_num;
|
||||
// sim_printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
||||
}
|
||||
|
||||
void clr_irq(int32 int_num)
|
||||
{
|
||||
mbirq &= ~int_num;
|
||||
// sim_printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
||||
}
|
||||
|
||||
/* This is the I/O configuration table. There are 256 possible
|
||||
device addresses, if a device is plugged to a port it's routine
|
||||
address is here, 'nulldev' means no device has been registered.
|
||||
*/
|
||||
struct idev {
|
||||
uint8 (*routine)(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 devnum;
|
||||
};
|
||||
|
||||
struct idev dev_table[256] = {
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
|
||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 0FCH */
|
||||
};
|
||||
|
||||
uint8 nulldev(t_bool flag, uint8 data, uint8 devnum)
|
||||
{
|
||||
SET_XACK(0); /* set no XACK */
|
||||
if (flag == 0) /* if we got here, no valid I/O device */
|
||||
return (0xFF);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum)
|
||||
{
|
||||
if (dev_table[port].routine != &nulldev) { /* port already assigned */
|
||||
// sim_printf("Multibus: I/O Port %02X is already assigned\n", port);
|
||||
} else {
|
||||
// sim_printf("Port %02X is assigned\n", port);
|
||||
dev_table[port].routine = routine;
|
||||
dev_table[port].devnum = devnum;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* end of ipcmultibus.c */
|
||||
|
||||
164
Intel-Systems/common/ipcram8.c
Normal file
164
Intel-Systems/common/ipcram8.c
Normal file
@@ -0,0 +1,164 @@
|
||||
/* iRAM8.c: Intel RAM simulator for 8-bit SBCs
|
||||
|
||||
Copyright (c) 2011, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
MODIFICATIONS:
|
||||
|
||||
?? ??? 11 - Original file.
|
||||
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
||||
24 Apr 15 -- Modified to use simh_debug
|
||||
|
||||
NOTES:
|
||||
|
||||
These functions support a simulated RAM devices on an iSBC-80/XX SBCs.
|
||||
These functions also support bit 2 of 8255 number 1, port B, to enable/
|
||||
disable the onboard RAM.
|
||||
*/
|
||||
|
||||
#include "system_defs.h"
|
||||
|
||||
#define SET_XACK(VAL) (xack = VAL)
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
t_stat RAM_svc (UNIT *uptr);
|
||||
t_stat RAM_reset (DEVICE *dptr, uint16 base, uint16 size);
|
||||
uint8 RAM_get_mbyte(uint16 addr);
|
||||
void RAM_put_mbyte(uint16 addr, uint8 val);
|
||||
|
||||
/* external function prototypes */
|
||||
|
||||
extern UNIT i8255_unit[];
|
||||
extern uint8 xack; /* XACK signal */
|
||||
|
||||
/* SIMH RAM Standard I/O Data Structures */
|
||||
|
||||
UNIT RAM_unit = { UDATA (NULL, UNIT_BINK, 0), KBD_POLL_WAIT };
|
||||
|
||||
DEBTAB RAM_debug[] = {
|
||||
{ "ALL", DEBUG_all },
|
||||
{ "FLOW", DEBUG_flow },
|
||||
{ "READ", DEBUG_read },
|
||||
{ "WRITE", DEBUG_write },
|
||||
{ "XACK", DEBUG_xack },
|
||||
{ "LEV1", DEBUG_level1 },
|
||||
{ "LEV2", DEBUG_level2 },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
DEVICE RAM_dev = {
|
||||
"RAM", //name
|
||||
&RAM_unit, //units
|
||||
NULL, //registers
|
||||
NULL, //modifiers
|
||||
1, //numunits
|
||||
16, //aradix
|
||||
16, //awidth
|
||||
1, //aincr
|
||||
16, //dradix
|
||||
8, //dwidth
|
||||
NULL, //examine
|
||||
NULL, //deposit
|
||||
// &RAM_reset, //reset
|
||||
NULL, //reset
|
||||
NULL, //boot
|
||||
NULL, //attach
|
||||
NULL, //detach
|
||||
NULL, //ctxt
|
||||
DEV_DEBUG, //flags
|
||||
0, //dctrl
|
||||
RAM_debug, //debflags
|
||||
NULL, //msize
|
||||
NULL //lname
|
||||
};
|
||||
|
||||
/* global variables */
|
||||
|
||||
/* RAM functions */
|
||||
|
||||
/* RAM reset */
|
||||
|
||||
t_stat RAM_reset (DEVICE *dptr, uint16 base, uint16 size)
|
||||
{
|
||||
sim_debug (DEBUG_flow, &RAM_dev, " RAM_reset: base=%04X size=%04X\n", base, size-1);
|
||||
if (RAM_unit.capac == 0) { /* if undefined */
|
||||
RAM_unit.capac = size;
|
||||
RAM_unit.u3 = base;
|
||||
}
|
||||
if (RAM_unit.filebuf == NULL) { /* no buffer allocated */
|
||||
RAM_unit.filebuf = malloc(RAM_unit.capac);
|
||||
if (RAM_unit.filebuf == NULL) {
|
||||
sim_debug (DEBUG_flow, &RAM_dev, "RAM_set_size: Malloc error\n");
|
||||
return SCPE_MEM;
|
||||
}
|
||||
}
|
||||
// sim_printf(" RAM: Available [%04X-%04XH]\n",
|
||||
// RAM_unit.u3,
|
||||
// RAM_unit.u3 + RAM_unit.capac - 1);
|
||||
sim_debug (DEBUG_flow, &RAM_dev, "RAM_reset: Done\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* get a byte from memory */
|
||||
|
||||
uint8 RAM_get_mbyte(uint16 addr)
|
||||
{
|
||||
uint8 val;
|
||||
|
||||
if (i8255_unit[0].u5 & 0x02) { /* enable RAM */
|
||||
sim_debug (DEBUG_read, &RAM_dev, "RAM_get_mbyte: addr=%04X\n", addr);
|
||||
if ((addr >= RAM_unit.u3) && ((uint32) addr < (RAM_unit.u3 + RAM_unit.capac))) {
|
||||
SET_XACK(1); /* good memory address */
|
||||
sim_debug (DEBUG_xack, &RAM_dev, "RAM_get_mbyte: Set XACK for %04X\n", addr);
|
||||
val = *((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3));
|
||||
sim_debug (DEBUG_read, &RAM_dev, " val=%04X\n", val);
|
||||
return (val & 0xFF);
|
||||
}
|
||||
sim_debug (DEBUG_read, &RAM_dev, " Out of range\n");
|
||||
return 0xFF;
|
||||
}
|
||||
sim_debug (DEBUG_read, &RAM_dev, " RAM disabled\n");
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
/* put a byte to memory */
|
||||
|
||||
void RAM_put_mbyte(uint16 addr, uint8 val)
|
||||
{
|
||||
if (i8255_unit[0].u5 & 0x02) { /* enable RAM */
|
||||
sim_debug (DEBUG_write, &RAM_dev, "RAM_put_mbyte: addr=%04X, val=%02X\n", addr, val);
|
||||
if ((addr >= RAM_unit.u3) && ((uint32)addr < RAM_unit.u3 + RAM_unit.capac)) {
|
||||
SET_XACK(1); /* good memory address */
|
||||
sim_debug (DEBUG_xack, &RAM_dev, "RAM_put_mbyte: Set XACK for %04X\n", addr);
|
||||
*((uint8 *)RAM_unit.filebuf + (addr - RAM_unit.u3)) = val & 0xFF;
|
||||
sim_debug (DEBUG_write, &RAM_dev, "\n");
|
||||
return;
|
||||
}
|
||||
sim_debug (DEBUG_write, &RAM_dev, " Out of range\n");
|
||||
return;
|
||||
}
|
||||
sim_debug (DEBUG_write, &RAM_dev, " RAM disabled\n");
|
||||
}
|
||||
|
||||
/* end of iRAM8.c */
|
||||
130
Intel-Systems/common/isbc202.c
Normal file
130
Intel-Systems/common/isbc202.c
Normal file
@@ -0,0 +1,130 @@
|
||||
/* isbc202.c: Intel double density disk adapter adapter
|
||||
|
||||
Copyright (c) 2010, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
MODIFICATIONS:
|
||||
|
||||
27 Jun 16 - Original file.
|
||||
|
||||
NOTES:
|
||||
|
||||
|
||||
*/
|
||||
|
||||
#include "system_defs.h" /* system header in system dir */
|
||||
|
||||
/* function prototypes */
|
||||
|
||||
uint8 isbc202(t_bool io, uint8 data, uint8 devnum); /* isbc202*/
|
||||
t_stat isbc202_reset(DEVICE *dptr, uint16 base, uint8 devnum);
|
||||
|
||||
/* external function prototypes */
|
||||
|
||||
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);
|
||||
|
||||
/* globals */
|
||||
|
||||
UNIT isbc202_unit[] = {
|
||||
{ UDATA (0, 0, 0) }, /* isbc202*/
|
||||
};
|
||||
|
||||
REG isbc202_reg[] = {
|
||||
{ HRDATA (CONTROL0, isbc202_unit[0].u3, 8) }, /* isbc202 */
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
DEBTAB isbc202_debug[] = {
|
||||
{ "ALL", DEBUG_all },
|
||||
{ "FLOW", DEBUG_flow },
|
||||
{ "READ", DEBUG_read },
|
||||
{ "WRITE", DEBUG_write },
|
||||
{ "XACK", DEBUG_xack },
|
||||
{ "LEV1", DEBUG_level1 },
|
||||
{ "LEV2", DEBUG_level2 },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
|
||||
|
||||
DEVICE isbc202_dev = {
|
||||
"ISBC202", //name
|
||||
isbc202_unit, //units
|
||||
isbc202_reg, //registers
|
||||
NULL, //modifiers
|
||||
1, //numunits
|
||||
16, //aradix
|
||||
16, //awidth
|
||||
1, //aincr
|
||||
16, //dradix
|
||||
8, //dwidth
|
||||
NULL, //examine
|
||||
NULL, //deposit
|
||||
// &isbc202_reset, //reset
|
||||
NULL, //reset
|
||||
NULL, //boot
|
||||
NULL, //attach
|
||||
NULL, //detach
|
||||
NULL, //ctxt
|
||||
0, //flags
|
||||
0, //dctrl
|
||||
isbc202_debug, //debflags
|
||||
NULL, //msize
|
||||
NULL //lname
|
||||
};
|
||||
|
||||
/* I/O instruction handlers, called from the CPU module when an
|
||||
IN or OUT instruction is issued.
|
||||
*/
|
||||
|
||||
/* ISBC202 control port functions */
|
||||
|
||||
uint8 isbc202(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* always return 0 */
|
||||
sim_printf(" isbc202: read data=%02X port=%02X returned 0\n", data, devnum);
|
||||
return 0x00;
|
||||
} else { /* write control port */
|
||||
sim_printf(" isbc202: data=%02X port=%02X\n", data, devnum);
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat isbc202_reset(DEVICE *dptr, uint16 base, uint8 devnum)
|
||||
{
|
||||
reg_dev(isbc202, base, devnum);
|
||||
reg_dev(isbc202, base + 1, devnum);
|
||||
reg_dev(isbc202, base + 2, devnum);
|
||||
reg_dev(isbc202, base + 3, devnum);
|
||||
reg_dev(isbc202, base + 4, devnum);
|
||||
reg_dev(isbc202, base + 5, devnum);
|
||||
reg_dev(isbc202, base + 6, devnum);
|
||||
reg_dev(isbc202, base + 7, devnum);
|
||||
isbc202_unit[devnum].u3 = 0x00; /* ipc reset */
|
||||
sim_printf(" isbc202-%d: Reset\n", devnum);
|
||||
sim_printf(" isbc202-%d: Registered at %04X\n", devnum, base);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* end of isbc202.c */
|
||||
444
Intel-Systems/common/zx200a.c
Normal file
444
Intel-Systems/common/zx200a.c
Normal file
@@ -0,0 +1,444 @@
|
||||
/* zx-200a.c: Intel double density disk adapter adapter
|
||||
|
||||
Copyright (c) 2010, William A. Beech
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
to deal in the Software without restriction, including without limitation
|
||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
and/or sell copies of the Software, and to permit persons to whom the
|
||||
Software is furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
Except as contained in this notice, the name of William A. Beech shall not be
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from William A. Beech.
|
||||
|
||||
MODIFICATIONS:
|
||||
|
||||
28 Jun 16 - Original file.
|
||||
|
||||
NOTES:
|
||||
|
||||
This controller will mount 4 DD disk images on drives :F0: thru :F3: addressed
|
||||
at ports 078H to 07FH. It also will mount 2 SD disk images on :F4: and :F5:
|
||||
addressed at ports 088H to 08FH. These are on physical drives :F0: and :F1:.
|
||||
|
||||
Registers:
|
||||
|
||||
078H - Read - Subsystem status
|
||||
bit 0 - ready status of drive 0
|
||||
bit 1 - ready status of drive 1
|
||||
bit 2 - state of channel's interrupt FF
|
||||
bit 3 - controller presence indicator
|
||||
bit 4 - DD controller presence indicator
|
||||
bit 5 - ready status of drive 2
|
||||
bit 6 - ready status of drive 3
|
||||
bit 7 - zero
|
||||
|
||||
079H - Read - Read result type (bits 2-7 are zero)
|
||||
00 - I/O complete with error
|
||||
01 - Reserved
|
||||
10 - Result byte contains diskette ready status
|
||||
11 - Reserved
|
||||
079H - Write - IOPB address low byte.
|
||||
|
||||
07AH - Write - IOPB address high byte and start operation.
|
||||
|
||||
07BH - Read - Read result byte
|
||||
If result type is 00H
|
||||
bit 0 - deleted record
|
||||
bit 1 - CRC error
|
||||
bit 2 - seek error
|
||||
bit 3 - address error
|
||||
bit 4 - data overrun/underrun
|
||||
bit 5 - write protect
|
||||
bit 6 - write error
|
||||
bit 7 - not ready
|
||||
If result type is 10H
|
||||
bit 0 - zero
|
||||
bit 1 - zero
|
||||
bit 2 - zero
|
||||
bit 3 - zero
|
||||
bit 4 - drive 2 ready
|
||||
bit 5 - drive 3 ready
|
||||
bit 6 - drive 0 ready
|
||||
bit 7 - drive 1 ready
|
||||
|
||||
07FH - Write - Reset diskette system.
|
||||
|
||||
Operations:
|
||||
Recalibrate -
|
||||
Seek -
|
||||
Format Track -
|
||||
Write Data -
|
||||
Write Deleted Data -
|
||||
Read Data -
|
||||
Verify CRC -
|
||||
|
||||
IOPB - I/O Parameter Block
|
||||
Byte 0 - Channel Word
|
||||
bit 3 - data word length (=8-bit, 1=16-bit)
|
||||
bit 4-5 - interrupt control
|
||||
00 - I/O complete interrupt to be issued
|
||||
01 - I/O complete interrupts are disabled
|
||||
10 - illegal code
|
||||
11 - illegal code
|
||||
bit 6- randon format sequence
|
||||
|
||||
Byte 1 - Diskette Instruction
|
||||
bit 0-2 - operation code
|
||||
000 - no operation
|
||||
001 - seek
|
||||
010 - format track
|
||||
011 - recalibrate
|
||||
100 - read data
|
||||
101 - verify CRC
|
||||
110 - write data
|
||||
111 - write deleted data
|
||||
bit 3 - data word length ( same as byte-0, bit-3)
|
||||
bit 4-5 - unit select
|
||||
00 - drive 0
|
||||
01 - drive 1
|
||||
10 - drive 2
|
||||
11 - drive 3
|
||||
bit 6-7 - reserved (zero)
|
||||
|
||||
Byte 2 - Number of Records
|
||||
|
||||
Byte 4 - Track Address
|
||||
|
||||
Byte 5 - Sector Address
|
||||
|
||||
Byte 6 - Buffer Low Address
|
||||
|
||||
Byte 7 - Buffer High Address
|
||||
|
||||
u3 -
|
||||
u4 -
|
||||
u5 -
|
||||
u6 - fdd number.
|
||||
*/
|
||||
|
||||
#include "system_defs.h" /* system header in system dir */
|
||||
|
||||
#define UNIT_V_WPMODE (UNIT_V_UF) /* Write protect */
|
||||
#define UNIT_WPMODE (1 << UNIT_V_WPMODE)
|
||||
|
||||
#define FDD_NUM 4
|
||||
|
||||
#define WP 0x40 /* Write protect */
|
||||
#define RDY 0x20 /* Ready */
|
||||
#define T0 0x10 /* Track 0 */
|
||||
#define TS 0x08 /* Two sided */
|
||||
|
||||
/* internal function prototypes */
|
||||
|
||||
t_stat zx200a_svc (UNIT *uptr);
|
||||
uint8 zx200a0(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 zx200a1(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 zx200a2(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 zx200a3(t_bool io, uint8 data, uint8 devnum);
|
||||
uint8 zx200a7(t_bool io, uint8 data, uint8 devnum);
|
||||
t_stat zx200a_attach (UNIT *uptr, CONST char *cptr);
|
||||
t_stat zx200a_reset(DEVICE *dptr, uint16 base, uint8 devnum);
|
||||
void zx200a_reset1(void);
|
||||
|
||||
/* external function prototypes */
|
||||
|
||||
extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);
|
||||
|
||||
/* globals */
|
||||
|
||||
uint16 iopb;
|
||||
uint8 syssta = 0, rsttyp = 0, rstbyt1 = 0, rstbyt2 = 0, cmd = 0;
|
||||
|
||||
uint8 *zx200a_buf[FDD_NUM] = { /* FDD buffer pointers */
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
int32 fddst[FDD_NUM] = { // fdd status
|
||||
0, // status of FDD 0
|
||||
0, // status of FDD 1
|
||||
0, // status of FDD 2
|
||||
0 // status of FDD 3
|
||||
};
|
||||
|
||||
int32 maxsec[FDD_NUM] = { // last sector
|
||||
0, // status of FDD 0
|
||||
0, // status of FDD 1
|
||||
0, // status of FDD 2
|
||||
0 // status of FDD 3
|
||||
};
|
||||
|
||||
int8 maxcyl[FDD_NUM] = {
|
||||
0, // last cylinder + 1 of FDD 0
|
||||
0, // last cylinder + 1 of FDD 1
|
||||
0, // last cylinder + 1 of FDD 2
|
||||
0 // last cylinder + 1 of FDD 3
|
||||
};
|
||||
|
||||
UNIT zx200a_unit[] = {
|
||||
{ UDATA (&zx200a_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
|
||||
{ UDATA (&zx200a_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
|
||||
{ UDATA (&zx200a_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
|
||||
{ UDATA (&zx200a_svc, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }
|
||||
};
|
||||
|
||||
REG zx200a_reg[] = {
|
||||
{ HRDATA (SUBSYSSTA, zx200a_unit[0].u3, 8) }, /* subsytem status */
|
||||
{ HRDATA (RSTTYP, zx200a_unit[0].u4, 8) }, /* result type */
|
||||
{ HRDATA (RSTBYT0, zx200a_unit[0].u5, 8) }, /* result byte 0 RSTTYP = 0*/
|
||||
{ HRDATA (RSTBYT1, zx200a_unit[0].u6, 8) }, /* result byte 1 RSTTYP = 10*/
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
DEBTAB zx200a_debug[] = {
|
||||
{ "ALL", DEBUG_all },
|
||||
{ "FLOW", DEBUG_flow },
|
||||
{ "READ", DEBUG_read },
|
||||
{ "WRITE", DEBUG_write },
|
||||
{ "XACK", DEBUG_xack },
|
||||
{ "LEV1", DEBUG_level1 },
|
||||
{ "LEV2", DEBUG_level2 },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
|
||||
|
||||
DEVICE zx200a_dev = {
|
||||
"ZX200A", //name
|
||||
zx200a_unit, //units
|
||||
zx200a_reg, //registers
|
||||
NULL, //modifiers
|
||||
1, //numunits
|
||||
16, //aradix
|
||||
16, //awidth
|
||||
1, //aincr
|
||||
16, //dradix
|
||||
8, //dwidth
|
||||
NULL, //examine
|
||||
NULL, //deposit
|
||||
// &zx200a_reset, //reset
|
||||
NULL, //reset
|
||||
NULL, //boot
|
||||
NULL, //attach
|
||||
NULL, //detach
|
||||
NULL, //ctxt
|
||||
0, //flags
|
||||
0, //dctrl
|
||||
zx200a_debug, //debflags
|
||||
NULL, //msize
|
||||
NULL //lname
|
||||
};
|
||||
|
||||
/* I/O instruction handlers, called from the CPU module when an
|
||||
IN or OUT instruction is issued.
|
||||
*/
|
||||
|
||||
/* Service routines to handle simulator functions */
|
||||
|
||||
/* service routine - actually does the simulated disk I/O */
|
||||
|
||||
t_stat zx200a_svc (UNIT *uptr)
|
||||
{
|
||||
sim_activate(&zx200a_unit[uptr->u6], zx200a_unit[uptr->u6].wait);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* zx200a control port functions */
|
||||
|
||||
uint8 zx200a0(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (io == 0) { /* read operation */
|
||||
val = zx200a_unit[0].u3;
|
||||
sim_printf(" zx200a0: read data=%02X devnum=%02X val=%02X\n", data, devnum, val);
|
||||
return val;
|
||||
} else { /* write control port */
|
||||
sim_printf(" zx200a0: write data=%02X port=%02X\n", data, devnum);
|
||||
}
|
||||
}
|
||||
|
||||
uint8 zx200a1(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (io == 0) { /* read operation */
|
||||
val = zx200a_unit[0].u4;
|
||||
sim_printf(" zx200a1: read data=%02X devnum=%02X val=%02X\n", data, devnum, val);
|
||||
return val;
|
||||
} else { /* write control port */
|
||||
iopb = data;
|
||||
sim_printf(" zx200a1: write data=%02X port=%02X iopb=%04X\n", data, devnum, iopb);
|
||||
}
|
||||
}
|
||||
|
||||
uint8 zx200a2(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* read operation */
|
||||
sim_printf(" zx200a2: read data=%02X devnum=%02X\n", data, devnum);
|
||||
return 0x00;
|
||||
} else { /* write control port */
|
||||
iopb |= (data << 8);
|
||||
sim_printf(" zx200a2: write data=%02X port=%02X iopb=%04X\n", data, devnum, iopb);
|
||||
}
|
||||
}
|
||||
|
||||
uint8 zx200a3(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
int val;
|
||||
|
||||
if (io == 0) { /* read operation */
|
||||
if (zx200a_unit[0].u4)
|
||||
val = zx200a_unit[0].u5;
|
||||
else
|
||||
val = zx200a_unit[0].u6;
|
||||
sim_printf(" zx200a3: read data=%02X devnum=%02X val=%02X\n", data, devnum, val);
|
||||
return val;
|
||||
} else { /* write control port */
|
||||
sim_printf(" zx200a3: write data=%02X port=%02X\n", data, devnum);
|
||||
}
|
||||
}
|
||||
|
||||
/* reset ZX-200A */
|
||||
uint8 zx200a7(t_bool io, uint8 data, uint8 devnum)
|
||||
{
|
||||
if (io == 0) { /* read operation */
|
||||
sim_printf(" zx200a7: read data=%02X devnum=%02X\n", data, devnum);
|
||||
return 0x00;
|
||||
} else { /* write control port */
|
||||
sim_printf(" zx200a7: write data=%02X port=%02X\n", data, devnum);
|
||||
zx200a_reset(NULL, ZX200A_BASE_DD, 0); //for now
|
||||
}
|
||||
}
|
||||
|
||||
/* zx200a attach - attach an .IMG file to a FDD */
|
||||
|
||||
t_stat zx200a_attach (UNIT *uptr, CONST char *cptr)
|
||||
{
|
||||
t_stat r;
|
||||
FILE *fp;
|
||||
int32 i, c = 0;
|
||||
long flen;
|
||||
|
||||
sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_attach: Entered with uptr=%08X cptr=%s\n", uptr, cptr);
|
||||
if ((r = attach_unit (uptr, cptr)) != SCPE_OK) {
|
||||
sim_printf(" zx200a_attach: Attach error\n");
|
||||
return r;
|
||||
}
|
||||
fp = fopen(uptr->filename, "rb");
|
||||
if (fp == NULL) {
|
||||
sim_printf(" Unable to open disk image file %s\n", uptr->filename);
|
||||
sim_printf(" No disk image loaded!!!\n");
|
||||
} else {
|
||||
sim_printf("zx200a: Attach\n");
|
||||
fseek(fp, 0, SEEK_END); /* size disk image */
|
||||
flen = ftell(fp);
|
||||
fseek(fp, 0, SEEK_SET);
|
||||
if (zx200a_buf[uptr->u6] == NULL) { /* no buffer allocated */
|
||||
zx200a_buf[uptr->u6] = (uint8 *)malloc(flen);
|
||||
if (zx200a_buf[uptr->u6] == NULL) {
|
||||
sim_printf(" zx200a_attach: Malloc error\n");
|
||||
return SCPE_MEM;
|
||||
}
|
||||
}
|
||||
uptr->capac = flen;
|
||||
i = 0;
|
||||
c = fgetc(fp); // copy disk image into buffer
|
||||
while (c != EOF) {
|
||||
*(zx200a_buf[uptr->u6] + i++) = c & 0xFF;
|
||||
c = fgetc(fp);
|
||||
}
|
||||
fclose(fp);
|
||||
switch(uptr->u6){
|
||||
case 0:
|
||||
fddst[uptr->u6] |= 0x01; /* set unit ready */
|
||||
break;
|
||||
case 1:
|
||||
fddst[uptr->u6] |= 0x02; /* set unit ready */
|
||||
break;
|
||||
case 2:
|
||||
fddst[uptr->u6] |= 0x20; /* set unit ready */
|
||||
break;
|
||||
case 3:
|
||||
fddst[uptr->u6] |= 0x40; /* set unit ready */
|
||||
break;
|
||||
}
|
||||
if (flen == 256256) { /* 8" 256K SSSD */
|
||||
maxcyl[uptr->u6] = 77;
|
||||
maxsec[uptr->u6] = 26;
|
||||
}
|
||||
else if (flen == 512512) { /* 8" 512K SSDD */
|
||||
maxcyl[uptr->u6] = 77;
|
||||
maxsec[uptr->u6] = 52;
|
||||
}
|
||||
sim_printf(" Drive-%d: %d bytes of disk image %s loaded, fddst=%02X\n",
|
||||
uptr->u6, i, uptr->filename, fddst[uptr->u6]);
|
||||
}
|
||||
sim_debug (DEBUG_flow, &zx200a_dev, " zx200a_attach: Done\n");
|
||||
return SCPE_OK;
|
||||
}
|
||||
/* Reset routine */
|
||||
|
||||
t_stat zx200a_reset(DEVICE *dptr, uint16 base, uint8 devnum)
|
||||
{
|
||||
reg_dev(zx200a0, base, devnum);
|
||||
reg_dev(zx200a1, base + 1, devnum);
|
||||
reg_dev(zx200a2, base + 2, devnum);
|
||||
reg_dev(zx200a3, base + 3, devnum);
|
||||
reg_dev(zx200a7, base + 7, devnum);
|
||||
zx200a_unit[devnum].u3 = 0x00; /* ipc reset */
|
||||
sim_printf(" zx200a-%d: Reset\n", devnum);
|
||||
sim_printf(" zx200a-%d: Registered at %04X\n", devnum, base);
|
||||
if ((zx200a_dev.flags & DEV_DIS) == 0)
|
||||
zx200a_reset1();
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
void zx200a_reset1(void)
|
||||
{
|
||||
int32 i;
|
||||
UNIT *uptr;
|
||||
static int flag = 1;
|
||||
|
||||
if (flag) sim_printf("ZX-200A: Initializing\n");
|
||||
for (i = 0; i < FDD_NUM; i++) { /* handle all units */
|
||||
uptr = zx200a_dev.units + i;
|
||||
if (uptr->capac == 0) { /* if not configured */
|
||||
// sim_printf(" ZX-200A%d: Not configured\n", i);
|
||||
// if (flag) {
|
||||
// sim_printf(" ALL: \"set ZX-200A en\"\n");
|
||||
// sim_printf(" EPROM: \"att ZX-200A0 <filename>\"\n");
|
||||
// flag = 0;
|
||||
// }
|
||||
uptr->capac = 0; /* initialize unit */
|
||||
uptr->u3 = 0;
|
||||
uptr->u4 = 0;
|
||||
uptr->u5 = 0;
|
||||
uptr->u6 = i; /* unit number - only set here! */
|
||||
fddst[i] = WP + T0 + i; /* initial drive status */
|
||||
uptr->flags |= UNIT_WPMODE; /* set WP in unit flags */
|
||||
sim_activate (&zx200a_unit[uptr->u6], zx200a_unit[uptr->u6].wait);
|
||||
} else {
|
||||
fddst[i] = RDY + WP + T0 + i; /* initial attach drive status */
|
||||
// sim_printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename);
|
||||
}
|
||||
}
|
||||
cmd = 0; /* clear command */
|
||||
flag = 0;
|
||||
}
|
||||
/* end of zx-200a.c */
|
||||
Reference in New Issue
Block a user