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ISYS8010, ISYS8020: Latest update
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Bill Beech
228
Intel-Systems/common/i8272.c
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228
Intel-Systems/common/i8272.c
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/* i8272.c: Intel 8272 FDC adapter
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Copyright (c) 2010, William A. Beech
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of William A. Beech shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from William A. Beech.
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MODIFICATIONS:
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?? ??? 10 - Original file.
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16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
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24 Apr 15 -- Modified to use simh_debug
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NOTES:
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u6 - unit number/device number
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*/
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#include "system_defs.h"
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/* external globals */
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extern uint16 port;
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#define UNIT_V_ANSI (UNIT_V_UF + 0) /* ANSI mode */
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#define UNIT_ANSI (1 << UNIT_V_ANSI)
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#define TXR 0x01
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#define RXR 0x02
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#define TXE 0x04
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#define SD 0x40
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extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16);
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/* function prototypes */
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t_stat i8272_svc (UNIT *uptr);
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t_stat i8272_reset (DEVICE *dptr, uint16 base);
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void i8272_reset1(uint8 devnum);
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uint8 i8272_get_dn(void);
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uint8 i8251s(t_bool io, uint8 data);
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uint8 i8251d(t_bool io, uint8 data);
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/* globals */
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int32 i8272_devnum = 0; //initially, no 8251 instances
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uint16 i8272_port[4]; //base port assigned to each 8251 instance
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/* i8251 Standard I/O Data Structures */
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/* up to 1 i8251 devices */
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UNIT i8272_unit[4] = {
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{ UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
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{ UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT }
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};
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REG i8272_reg[4] = {
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{ HRDATA (DATA, i8272_unit[0].buf, 8) },
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{ HRDATA (STAT, i8272_unit[0].u3, 8) },
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{ HRDATA (MODE, i8272_unit[0].u4, 8) },
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{ HRDATA (CMD, i8272_unit[0].u5, 8) }
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};
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DEBTAB i8272_debug[] = {
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{ "ALL", DEBUG_all },
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{ "FLOW", DEBUG_flow },
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{ "READ", DEBUG_read },
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{ "WRITE", DEBUG_write },
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{ "XACK", DEBUG_xack },
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{ "LEV1", DEBUG_level1 },
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{ "LEV2", DEBUG_level2 },
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{ NULL }
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};
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MTAB i8272_mod[] = {
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{ UNIT_ANSI, 0, "TTY", "TTY", NULL },
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{ UNIT_ANSI, UNIT_ANSI, "ANSI", "ANSI", NULL },
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{ 0 }
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};
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/* address width is set to 16 bits to use devices in 8086/8088 implementations */
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DEVICE i8272_dev = {
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"I8272", //name
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i8272_unit, //units
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i8272_reg, //registers
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i8272_mod, //modifiers
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1, //numunits
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16, //aradix
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16, //awidth
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1, //aincr
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16, //dradix
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8, //dwidth
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NULL, //examine
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NULL, //deposit
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// &i8272_reset, //reset
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NULL, //reset
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NULL, //boot
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NULL, //attach
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NULL, //detach
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NULL, //ctxt
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0, //flags
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0, //dctrl
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i8272_debug, //debflags
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NULL, //msize
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NULL //lname
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};
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/* Service routines to handle simulator functions */
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/* i8272_svc - actually gets char & places in buffer */
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t_stat i8272_svc(UNIT *uptr)
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{
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int32 temp;
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sim_activate(&i8272_unit[uptr->u6], i8272_unit[uptr->u6].wait); /* continue poll */
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if (uptr->u6 >= i8272_devnum) return SCPE_OK;
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if ((temp = sim_poll_kbd()) < SCPE_KFLAG)
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return temp; /* no char or error? */
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//sim_printf("i8272_svc: received character temp=%04X devnum=%d\n", temp, uptr->u6);
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i8272_unit[uptr->u6].buf = temp & 0xFF; /* Save char */
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i8272_unit[uptr->u6].u3 |= RXR; /* Set status */
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return SCPE_OK;
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}
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/* Reset routine */
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t_stat i8272_reset(DEVICE *dptr, uint16 base)
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{
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if (i8272_devnum >= i8272_NUM) {
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sim_printf("8251_reset: too many devices!\n");
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return 0;
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}
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i8272_reset1(i8272_devnum);
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sim_printf(" 8251-%d: Registered at %03X\n", i8272_devnum, base);
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i8272_port[i8272_devnum] = reg_dev(i8251d, base);
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reg_dev(i8251s, base + 1);
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i8272_unit[i8272_devnum].u6 = i8272_devnum;
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sim_activate(&i8272_unit[i8272_devnum], i8272_unit[i8272_devnum].wait); /* activate unit */
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i8272_devnum++;
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return SCPE_OK;
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}
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void i8272_reset1(uint8 devnum)
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{
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i8272_unit[devnum].u3 = TXR + TXE; /* status */
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i8272_unit[devnum].u4 = 0; /* mode instruction */
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i8272_unit[devnum].u5 = 0; /* command instruction */
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i8272_unit[devnum].buf = 0;
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i8272_unit[devnum].pos = 0;
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sim_printf(" 8251-%d: Reset\n", devnum);
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}
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uint8 i8272_get_dn(void)
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{
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int i;
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for (i=0; i<i8272_NUM; i++)
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if (port >=i8272_port[i] && port <= i8272_port[i] + 1)
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return i;
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sim_printf("i8272_get_dn: port %03X not in 8251 device table\n", port);
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return 0xFF;
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}
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/* I/O instruction handlers, called from the CPU module when an
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IN or OUT instruction is issued.
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*/
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uint8 i8251s(t_bool io, uint8 data)
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{
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uint8 devnum;
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if ((devnum = i8272_get_dn()) != 0xFF) {
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if (io == 0) { /* read status port */
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return i8272_unit[devnum].u3;
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} else { /* write status port */
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if (i8272_unit[devnum].u6) { /* if mode, set cmd */
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i8272_unit[devnum].u5 = data;
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sim_printf(" 8251-%d: Command Instruction=%02X\n", devnum, data);
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if (data & SD) /* reset port! */
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i8272_reset1(devnum);
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} else { /* set mode */
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i8272_unit[devnum].u4 = data;
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sim_printf(" 8251-%d: Mode Instruction=%02X\n", devnum, data);
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i8272_unit[devnum].u6 = 1; /* set cmd received */
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}
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}
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}
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return 0;
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}
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uint8 i8251d(t_bool io, uint8 data)
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{
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uint8 devnum;
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if ((devnum = i8272_get_dn()) != 0xFF) {
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if (io == 0) { /* read data port */
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i8272_unit[devnum].u3 &= ~RXR;
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return (i8272_unit[devnum].buf);
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} else { /* write data port */
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sim_putchar(data);
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}
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}
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return 0;
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}
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/* end of i8251.c */
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