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Notes For V2.10-2

Browse Source 
1. New Features in 2.10-2

The build procedures have changed.  There is only one UNIX makefile.
To compile without Ethernet support, simply type

	gmake {target|all}

To compile with Ethernet support, type

	gmake USE_NETWORK=1 {target|all}

The Mingw batch files require Mingw release 2 and invoke the Unix
makefile.  There are still separate batch files for compilation
with or without Ethernet support.

1.1 SCP and Libraries

- The EVAL command will evaluate a symbolic type-in and display
  it in numeric form.
- The ! command (with no arguments) will launch the host operating
  system command shell.  The ! command (with an argument) executes
  the argument as a host operating system command.  (Code from
  Mark Pizzolato)
- Telnet sessions now recognize BREAK.  How a BREAK is transmitted
  dependent on the particular Telnet client.  (Code from Mark
  Pizzolato)
- The sockets library includes code for active connections as
  well as listening connections.
- The RESTORE command will restore saved memory size, if the
  simulator supports dynamic memory resizing.

1.2 PDP-1

- The PDP-1 supports the Type 24 serial drum (based on recently
  discovered documents).

1.3 18b PDP's

- The PDP-4 supports the Type 24 serial drum (based on recently
  discovered documents).

1.4 PDP-11

- The PDP-11 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.5 PDP-10

- The PDP-10 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.6 HP 2100

- The IOP microinstruction set is supported for the 21MX as well
  as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).

1.7 VAX

- If the VAX console is attached to a Telnet session, BREAK is
  interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
  the most recently executed instructions.  (Code from Mark
  Pizzolato)

1.8 Terminals Multiplexors

- BREAK detection was added to the HP, DEC, and Interdata terminal
  multiplexors.

1.9 Interdata 16b and 32b

- First release.  UNIX is not yet working.

1.10 SDS 940

- First release.

2. Bugs Fixed in 2.10-2

- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
  read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
  (found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
  descriptors (found by Mark Pizzolato).

3. New Features in 2.10 vs prior releases

3.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

3.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

3.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

3.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

3.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

3.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

3.7 IBM 1620

- The IBM 1620 simulator has been released.

3.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

3.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

3.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

3.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

4. Bugs Fixed in 2.10 vs prior releases

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
  Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
  both input and output (found by Derek Peschel)

5. General Notes

WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
This commit is contained in:
Bob Supnik
2003-01-17 18:35:00 -08:00
committed by Mark Pizzolato
parent 4ea745b3ad
commit 2bcd1e7c4c
206 changed files with 30253 additions and 12114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

603
PDP18B/pdp18b_cpu.c
View File

@@ -519,18 +519,18 @@ extern UNIT clk_unit;
#if defined (PDP9)
#define CHECK_AUTO_INC \
if ((IR & 017770) == 010) { \
MA = MA & 017; \
M[MA] = (M[MA] + 1) & 0777777; }
MA = MA & 017; \
M[MA] = (M[MA] + 1) & 0777777; }
#define INDIRECT \
MA = memm? M[MA] & IAMASK: (MA & epcmask) | (M[MA] & damask)
#define CHECK_ADDR_R(x) \
if (usmd) { \
if (!MEM_ADDR_OK (x)) { \
nexm = prvn = trap_pending = 1; \
break; } \
if ((x) < BR) { \
prvn = trap_pending = 1; \
break; } } \
if (!MEM_ADDR_OK (x)) { \
nexm = prvn = trap_pending = 1; \
break; } \
if ((x) < BR) { \
prvn = trap_pending = 1; \
break; } } \
if (!MEM_ADDR_OK (x)) nexm = 1
#define CHECK_INDEX /* no indexing capability */
#define CHECK_ADDR_W(x) \
@@ -550,28 +550,28 @@ extern UNIT clk_unit;
#if defined (PDP15)
#define CHECK_AUTO_INC \
if ((IR & damask & ~07) == 00010) { \
MA = MA & 017; \
M[MA] = (M[MA] + 1) & 0777777; }
MA = MA & 017; \
M[MA] = (M[MA] + 1) & 0777777; }
#define INDIRECT \
if (rest_pending) { \
rest_pending = 0; \
LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777); \
memm = (M[MA] >> 16) & 1; \
usmd = (M[MA] >> 15) & 1; } \
rest_pending = 0; \
LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777); \
memm = (M[MA] >> 16) & 1; \
usmd = (M[MA] >> 15) & 1; } \
MA = ((IR & damask & ~07) != 00010)? \
(PC & BLKMASK) | (M[MA] & IAMASK): (M[MA] & ADDRMASK); \
(PC & BLKMASK) | (M[MA] & IAMASK): (M[MA] & ADDRMASK); \
damask = memm? 017777: 07777; \
epcmask = ADDRMASK & ~damask
#define CHECK_INDEX \
if ((IR & 0010000) && (memm == 0)) MA = (MA + XR) & ADDRMASK
#define CHECK_ADDR_R(x) \
if (usmd) { \
if (!MEM_ADDR_OK (x)) { \
nexm = prvn = trap_pending = 1; \
break; } \
if ((x) < BR) { \
prvn = trap_pending = 1; \
break; } } \
if (!MEM_ADDR_OK (x)) { \
nexm = prvn = trap_pending = 1; \
break; } \
if ((x) < BR) { \
prvn = trap_pending = 1; \
break; } } \
if (!MEM_ADDR_OK (x)) nexm = 1
#define CHECK_ADDR_W(x) \
CHECK_ADDR_R (x); \
@@ -644,16 +644,17 @@ if (api_int && !ion_defer) { /* API intr? */
int32 i, lvl = api_int - 1; /* get req level */
api_act = api_act | (0200 >> lvl); /* set level active */
if (lvl >= API_HLVL) { /* software req? */
MA = ACH_SWRE + lvl - API_HLVL; /* vec = 40:43 */
api_req = api_req & ~(0200 >> lvl); } /* remove request */
else { MA = 0; /* assume fails */
for (i = 0; i < 32; i++) { /* loop hi to lo */
if ((int_hwre[lvl] >> i) & 1) { /* int req set? */
MA = api_vec[lvl][i]; /* get vector */
break; } } } /* and stop */
MA = ACH_SWRE + lvl - API_HLVL; /* vec = 40:43 */
api_req = api_req & ~(0200 >> lvl); } /* remove request */
else {
MA = 0; /* assume fails */
for (i = 0; i < 32; i++) { /* loop hi to lo */
if ((int_hwre[lvl] >> i) & 1) { /* int req set? */
MA = api_vec[lvl][i]; /* get vector */
break; } } } /* and stop */
if (MA == 0) { /* bad channel? */
reason = STOP_API; /* API error */
break; }
reason = STOP_API; /* API error */
break; }
api_int = api_eval (&int_pend); /* no API int */
api_cycle = 1; /* in API cycle */
emir_pending = rest_pending = 0; /* emir, restore off */
@@ -687,11 +688,11 @@ if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
#if defined (PDP9) || defined (PDP15)
if (usmd) { /* user mode? */
if (!MEM_ADDR_OK (PC)) { /* nxm? */
nexm = prvn = trap_pending = 1; /* abort fetch */
continue; } \
nexm = prvn = trap_pending = 1; /* abort fetch */
continue; }
if (PC < BR) { /* bounds viol? */
prvn = trap_pending = 1; /* abort fetch */
continue; } }
prvn = trap_pending = 1; /* abort fetch */
continue; } }
else if (!MEM_ADDR_OK (PC)) nexm = 1; /* flag nxm */
if (!ion_defer) usmd = usmdbuf; /* no IOT? load usmd */
#endif
@@ -819,11 +820,11 @@ case 020: /* XCT, dir */
CHECK_INDEX;
CHECK_ADDR_R (MA);
if (usmd && (xct_count != 0)) { /* trap and chained? */
prvn = trap_pending = 1;
break; }
prvn = trap_pending = 1;
break; }
if (xct_count >= xct_max) { /* too many XCT's? */
reason = STOP_XCT;
break; }
reason = STOP_XCT;
break; }
xct_count = xct_count + 1; /* count XCT's */
#if defined (PDP9)
ion_defer = 1; /* defer intr */
@@ -848,8 +849,8 @@ case 001: case 000: /* CAL */
#if defined (PDP9) || defined (PDP15)
usmd = 0; /* clear user mode */
if ((cpu_unit.flags & UNIT_NOAPI) == 0) { /* if API, act lvl 4 */
api_act = api_act | 010;
api_int = api_eval (&int_pend); }
api_act = api_act | 010;
api_int = api_eval (&int_pend); }
#endif
if (IR & 0020000) { INDIRECT; } /* indirect? */
CHECK_ADDR_W (MA);
@@ -885,9 +886,9 @@ CHECK_AUTO_INC; /* check auto inc */
#endif
#if defined (PDP9)
if (rest_pending) { /* restore pending? */
LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777);
memm = (M[MA] >> 16) & 1;
usmd = (M[MA] >> 15) & 1; }
LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777);
memm = (M[MA] >> 16) & 1;
usmd = (M[MA] >> 15) & 1; }
#endif
INDIRECT; /* complete indirect */
emir_pending = rest_pending = 0;
@@ -907,147 +908,147 @@ case 036: /* OPR, dir */
skp = 0; /* assume no skip */
switch ((IR >> 6) & 017) { /* decode IR<8:11> */
case 0: /* nop */
break;
break;
case 1: /* SMA */
if ((LAC & 0400000) != 0) skp = 1;
break;
if ((LAC & 0400000) != 0) skp = 1;
break;
case 2: /* SZA */
if ((LAC & 0777777) == 0) skp = 1;
break;
if ((LAC & 0777777) == 0) skp = 1;
break;
case 3: /* SZA | SMA */
if (((LAC & 0777777) == 0) || ((LAC & 0400000) != 0))
skp = 1;
break;
if (((LAC & 0777777) == 0) || ((LAC & 0400000) != 0))
skp = 1;
break;
case 4: /* SNL */
if (LAC >= 01000000) skp = 1;
break;
if (LAC >= 01000000) skp = 1;
break;
case 5: /* SNL | SMA */
if (LAC >= 0400000) skp = 1;
break;
if (LAC >= 0400000) skp = 1;
break;
case 6: /* SNL | SZA */
if ((LAC >= 01000000) || (LAC == 0)) skp = 1;
break;
if ((LAC >= 01000000) || (LAC == 0)) skp = 1;
break;
case 7: /* SNL | SZA | SMA */
if ((LAC >= 0400000) || (LAC == 0)) skp = 1;
break;
if ((LAC >= 0400000) || (LAC == 0)) skp = 1;
break;
case 010: /* SKP */
skp = 1;
break;
skp = 1;
break;
case 011: /* SPA */
if ((LAC & 0400000) == 0) skp = 1;
break;
if ((LAC & 0400000) == 0) skp = 1;
break;
case 012: /* SNA */
if ((LAC & 0777777) != 0) skp = 1;
break;
if ((LAC & 0777777) != 0) skp = 1;
break;
case 013: /* SNA & SPA */
if (((LAC & 0777777) != 0) && ((LAC & 0400000) == 0))
skp = 1;
break;
if (((LAC & 0777777) != 0) && ((LAC & 0400000) == 0))
skp = 1;
break;
case 014: /* SZL */
if (LAC < 01000000) skp = 1;
break;
if (LAC < 01000000) skp = 1;
break;
case 015: /* SZL & SPA */
if (LAC < 0400000) skp = 1;
break;
if (LAC < 0400000) skp = 1;
break;
case 016: /* SZL & SNA */
if ((LAC < 01000000) && (LAC != 0)) skp = 1;
break;
if ((LAC < 01000000) && (LAC != 0)) skp = 1;
break;
case 017: /* SZL & SNA & SPA */
if ((LAC < 0400000) && (LAC != 0)) skp = 1;
break; } /* end switch skips */
if ((LAC < 0400000) && (LAC != 0)) skp = 1;
break; } /* end switch skips */
/* OPR, continued */
switch (((IR >> 9) & 014) | (IR & 03)) { /* IR<5:6,16:17> */
case 0: /* NOP */
break;
break;
case 1: /* CMA */
LAC = LAC ^ 0777777;
break;
LAC = LAC ^ 0777777;
break;
case 2: /* CML */
LAC = LAC ^ 01000000;
break;
LAC = LAC ^ 01000000;
break;
case 3: /* CML CMA */
LAC = LAC ^ 01777777;
break;
LAC = LAC ^ 01777777;
break;
case 4: /* CLL */
LAC = LAC & 0777777;
break;
LAC = LAC & 0777777;
break;
case 5: /* CLL CMA */
LAC = (LAC & 0777777) ^ 0777777;
break;
LAC = (LAC & 0777777) ^ 0777777;
break;
case 6: /* CLL CML = STL */
LAC = LAC | 01000000;
break;
LAC = LAC | 01000000;
break;
case 7: /* CLL CML CMA */
LAC = (LAC | 01000000) ^ 0777777;
break;
LAC = (LAC | 01000000) ^ 0777777;
break;
case 010: /* CLA */
LAC = LAC & 01000000;
break;
LAC = LAC & 01000000;
break;
case 011: /* CLA CMA = STA */
LAC = LAC | 0777777;
break;
LAC = LAC | 0777777;
break;
case 012: /* CLA CML */
LAC = (LAC & 01000000) ^ 01000000;
break;
LAC = (LAC & 01000000) ^ 01000000;
break;
case 013: /* CLA CML CMA */
LAC = (LAC | 0777777) ^ 01000000;
break;
LAC = (LAC | 0777777) ^ 01000000;
break;
case 014: /* CLA CLL */
LAC = 0;
break;
LAC = 0;
break;
case 015: /* CLA CLL CMA */
LAC = 0777777;
break;
LAC = 0777777;
break;
case 016: /* CLA CLL CML */
LAC = 01000000;
break;
LAC = 01000000;
break;
case 017: /* CLA CLL CML CMA */
LAC = 01777777;
break; } /* end decode */
LAC = 01777777;
break; } /* end decode */
/* OPR, continued */
if (IR & 0000004) { /* OAS */
#if defined (PDP9) || defined (PDP15)
if (usmd) prvn = trap_pending = 1;
else
if (usmd) prvn = trap_pending = 1;
else
#endif
LAC = LAC | SR; }
switch (((IR >> 8) & 04) | ((IR >> 3) & 03)) { /* decode IR<7,13:14> */
case 1: /* RAL */
LAC = ((LAC << 1) | (LAC >> 18)) & 01777777;
LAC = ((LAC << 1) | (LAC >> 18)) & 01777777;
break;
case 2: /* RAR */
LAC = ((LAC >> 1) | (LAC << 18)) & 01777777;
break;
LAC = ((LAC >> 1) | (LAC << 18)) & 01777777;
break;
case 3: /* RAL RAR */
#if defined (PDP15) /* PDP-15 */
LAC = (LAC + 1) & 01777777; /* IAC */
LAC = (LAC + 1) & 01777777; /* IAC */
#else /* PDP-4,-7,-9 */
reason = stop_inst; /* undefined */
reason = stop_inst; /* undefined */
#endif
break;
break;
case 5: /* RTL */
LAC = ((LAC << 2) | (LAC >> 17)) & 01777777;
break;
LAC = ((LAC << 2) | (LAC >> 17)) & 01777777;
break;
case 6: /* RTR */
LAC = ((LAC >> 2) | (LAC << 17)) & 01777777;
break;
LAC = ((LAC >> 2) | (LAC << 17)) & 01777777;
break;
case 7: /* RTL RTR */
#if defined (PDP15) /* PDP-15 */
LAC = ((LAC >> 9) & 0777) | ((LAC & 0777) << 9) |
(LAC & 01000000); /* BSW */
LAC = ((LAC >> 9) & 0777) | ((LAC & 0777) << 9) |
(LAC & 01000000); /* BSW */
#else /* PDP-4,-7,-9 */
reason = stop_inst; /* undefined */
reason = stop_inst; /* undefined */
#endif
break; } /* end switch rotate */
break; } /* end switch rotate */
if (IR & 0000040) { /* HLT */
if (usmd) prvn = trap_pending = 1;
else reason = STOP_HALT; }
if (usmd) prvn = trap_pending = 1;
else reason = STOP_HALT; }
if (skp && !prvn) PC = INCR_ADDR (PC); /* if skip, inc PC */
break; /* end OPR */
@@ -1065,10 +1066,10 @@ case 036: /* OPR, dir */
case 033: case 032: /* EAE */
if (cpu_unit.flags & UNIT_NOEAE) break; /* disabled? */
if (IR & 0020000) /* IR<4>? AC0 to L */
LAC = ((LAC << 1) & 01000000) | (LAC & 0777777);
LAC = ((LAC << 1) & 01000000) | (LAC & 0777777);
if (IR & 0010000) MQ = 0; /* IR<5>? clear MQ */
if ((IR & 0004000) && (LAC & 0400000)) /* IR<6> and minus? */
eae_ac_sign = 01000000; /* set eae_ac_sign */
eae_ac_sign = 01000000; /* set eae_ac_sign */
else eae_ac_sign = 0; /* if not, unsigned */
if (IR & 0002000) MQ = (MQ | LAC) & 0777777; /* IR<7>? or AC */
else if (eae_ac_sign) LAC = LAC ^ 0777777; /* if not, |AC| */
@@ -1079,25 +1080,25 @@ case 033: case 032: /* EAE */
switch ((IR >> 6) & 07) { /* case on IR<9:11> */
case 0: /* setup */
if (IR & 04) LAC = LAC ^ 0777777; /* IR<15>? ~AC */
if (IR & 02) LAC = LAC | MQ; /* IR<16>? or MQ */
if (IR & 01) LAC = LAC | ((-SC) & 077); /* IR<17>? or SC */
break;
if (IR & 04) LAC = LAC ^ 0777777; /* IR<15>? ~AC */
if (IR & 02) LAC = LAC | MQ; /* IR<16>? or MQ */
if (IR & 01) LAC = LAC | ((-SC) & 077); /* IR<17>? or SC */
break;
case 1: /* multiply */
CHECK_ADDR_R (PC); /* validate PC */
MA = M[PC]; /* get next word */
PC = INCR_ADDR (PC); /* increment PC */
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
LAC = LAC & 0777777; /* clear link */
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
if (MQ & 1) LAC = LAC + MA; /* MQ<17>? add */
MQ = (MQ >> 1) | ((LAC & 1) << 17);
LAC = LAC >> 1; } /* shift AC'MQ right */
if (eae_ac_sign ^ link_init) { /* result negative? */
LAC = LAC ^ 0777777;
MQ = MQ ^ 0777777; }
break;
CHECK_ADDR_R (PC); /* validate PC */
MA = M[PC]; /* get next word */
PC = INCR_ADDR (PC); /* increment PC */
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
LAC = LAC & 0777777; /* clear link */
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
if (MQ & 1) LAC = LAC + MA; /* MQ<17>? add */
MQ = (MQ >> 1) | ((LAC & 1) << 17);
LAC = LAC >> 1; } /* shift AC'MQ right */
if (eae_ac_sign ^ link_init) { /* result negative? */
LAC = LAC ^ 0777777;
MQ = MQ ^ 0777777; }
break;
/* EAE, continued
@@ -1111,26 +1112,26 @@ case 033: case 032: /* EAE */
*/
case 3: /* divide */
CHECK_ADDR_R (PC); /* validate PC */
MA = M[PC]; /* get next word */
PC = INCR_ADDR (PC); /* increment PC */
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
if ((LAC & 0777777) >= MA) { /* overflow? */
LAC = (LAC - MA) | 01000000; /* set link */
break; }
LAC = LAC & 0777777; /* clear link */
t = 0; /* init loop */
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
if (t) LAC = (LAC + MA) & 01777777;
else LAC = (LAC - MA) & 01777777;
t = (LAC >> 18) & 1; /* quotient bit */
if (SC > 1) LAC = /* skip if last */
((LAC << 1) | (MQ >> 17)) & 01777777;
MQ = ((MQ << 1) | t) & 0777777; }
CHECK_ADDR_R (PC); /* validate PC */
MA = M[PC]; /* get next word */
PC = INCR_ADDR (PC); /* increment PC */
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
if ((LAC & 0777777) >= MA) { /* overflow? */
LAC = (LAC - MA) | 01000000; /* set link */
break; }
LAC = LAC & 0777777; /* clear link */
t = 0; /* init loop */
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
if (t) LAC = (LAC + MA) & 01777777;
if (eae_ac_sign) LAC = LAC ^ 0777777; /* sgn rem = sgn divd */
if (eae_ac_sign ^ link_init ^ 1) MQ = MQ ^ 0777777;
break;
else LAC = (LAC - MA) & 01777777;
t = (LAC >> 18) & 1; /* quotient bit */
if (SC > 1) LAC = /* skip if last */
((LAC << 1) | (MQ >> 17)) & 01777777;
MQ = ((MQ << 1) | t) & 0777777; }
if (t) LAC = (LAC + MA) & 01777777;
if (eae_ac_sign) LAC = LAC ^ 0777777; /* sgn rem = sgn divd */
if (eae_ac_sign ^ link_init ^ 1) MQ = MQ ^ 0777777;
break;
/* EAE, continued
@@ -1141,43 +1142,45 @@ case 033: case 032: /* EAE */
case 4: /* normalize */
#if defined (PDP15)
if (!usmd) ion_defer = 2; /* free cycles */
if (!usmd) ion_defer = 2; /* free cycles */
#endif
for (SC = esc; (SC != 0) && ((LAC & 0400000) ==
((LAC << 1) & 0400000)); SC--) {
LAC = (LAC << 1) | ((MQ >> 17) & 1);
MQ = (MQ << 1) | (link_init >> 18); }
LAC = link_init | (LAC & 0777777); /* trim AC, restore L */
MQ = MQ & 0777777; /* trim MQ */
SC = SC & 077; /* trim SC */
break;
for (SC = esc; (SC != 0) && ((LAC & 0400000) ==
((LAC << 1) & 0400000)); SC--) {
LAC = (LAC << 1) | ((MQ >> 17) & 1);
MQ = (MQ << 1) | (link_init >> 18); }
LAC = link_init | (LAC & 0777777); /* trim AC, restore L */
MQ = MQ & 0777777; /* trim MQ */
SC = SC & 077; /* trim SC */
break;
case 5: /* long right shift */
if (esc < 18) {
MQ = ((LAC << (18 - esc)) | (MQ >> esc)) & 0777777;
LAC = ((fill << (18 - esc)) | (LAC >> esc)) & 01777777; }
else { if (esc < 36) MQ =
((fill << (36 - esc)) | (LAC >> (esc - 18))) & 0777777;
else MQ = fill;
LAC = link_init | fill; }
SC = 0; /* clear step count */
break;
if (esc < 18) {
MQ = ((LAC << (18 - esc)) | (MQ >> esc)) & 0777777;
LAC = ((fill << (18 - esc)) | (LAC >> esc)) & 01777777; }
else {
if (esc < 36) MQ =
((fill << (36 - esc)) | (LAC >> (esc - 18))) & 0777777;
else MQ = fill;
LAC = link_init | fill; }
SC = 0; /* clear step count */
break;
case 6: /* long left shift */
if (esc < 18) {
LAC = link_init |
(((LAC << esc) | (MQ >> (18 - esc))) & 0777777);
MQ = ((MQ << esc) | (fill >> (18 - esc))) & 0777777; }
else { if (esc < 36) LAC = link_init |
(((MQ << (esc - 18)) | (fill >> (36 - esc))) & 0777777);
else LAC = link_init | fill;
MQ = fill; }
SC = 0; /* clear step count */
break;
case 7: /* AC left shift */
if (esc < 18) LAC = link_init |
(((LAC << esc) | (fill >> (18 - esc))) & 0777777);
if (esc < 18) {
LAC = link_init |
(((LAC << esc) | (MQ >> (18 - esc))) & 0777777);
MQ = ((MQ << esc) | (fill >> (18 - esc))) & 0777777; }
else {
if (esc < 36) LAC = link_init |
(((MQ << (esc - 18)) | (fill >> (36 - esc))) & 0777777);
else LAC = link_init | fill;
SC = 0; /* clear step count */
break; } /* end switch IR */
MQ = fill; }
SC = 0; /* clear step count */
break;
case 7: /* AC left shift */
if (esc < 18) LAC = link_init |
(((LAC << esc) | (fill >> (18 - esc))) & 0777777);
else LAC = link_init | fill;
SC = 0; /* clear step count */
break; } /* end switch IR */
break; /* end case EAE */
/* PDP-15 index operates: opcode 72 */
@@ -1187,46 +1190,46 @@ case 035: /* index operates */
t = (IR & 0400)? IR | 0777000: IR & 0377; /* sext immediate */
switch ((IR >> 9) & 017) { /* case on IR<5:8> */
case 000: /* AAS */
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
if (SEXT (LAC & 0777777) >= SEXT (LR))
PC = INCR_ADDR (PC);
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
if (SEXT (LAC & 0777777) >= SEXT (LR))
PC = INCR_ADDR (PC);
case 001: /* PAX */
XR = LAC & 0777777;
break;
XR = LAC & 0777777;
break;
case 002: /* PAL */
LR = LAC & 0777777;
break;
LR = LAC & 0777777;
break;
case 003: /* AAC */
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
break;
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
break;
case 004: /* PXA */
LAC = (LAC & 01000000) | XR;
break;
LAC = (LAC & 01000000) | XR;
break;
case 005: /* AXS */
XR = (XR + t) & 0777777;
if (SEXT (XR) >= SEXT (LR)) PC = INCR_ADDR (PC);
break;
XR = (XR + t) & 0777777;
if (SEXT (XR) >= SEXT (LR)) PC = INCR_ADDR (PC);
break;
case 006: /* PXL */
LR = XR;
break;
LR = XR;
break;
case 010: /* PLA */
LAC = (LAC & 01000000) | LR;
break;
LAC = (LAC & 01000000) | LR;
break;
case 011: /* PLX */
XR = LR;
break;
XR = LR;
break;
case 014: /* CLAC */
LAC = LAC & 01000000;
break;
LAC = LAC & 01000000;
break;
case 015: /* CLX */
XR = 0;
break;
XR = 0;
break;
case 016: /* CLLR */
LR = 0;
break;
LR = 0;
break;
case 017: /* AXR */
XR = (XR + t) & 0777777;
break; } /* end switch IR */
XR = (XR + t) & 0777777;
break; } /* end switch IR */
break; /* end case */
#endif
@@ -1267,12 +1270,12 @@ case 035: /* index operates */
case 034: /* IOT */
#if defined (PDP15)
if (IR & 0010000) { /* floating point? */
/* PC = fp15 (PC, IR); /* process */
break; }
/* PC = fp15 (PC, IR); /* process */
break; }
#endif
if (usmd) { /* user mode? */
prvn = trap_pending = 1; /* trap */
break; }
prvn = trap_pending = 1; /* trap */
break; }
device = (IR >> 6) & 077; /* device = IR<6:11> */
pulse = IR & 067; /* pulse = IR<12:17> */
if (IR & 0000010) LAC = LAC & 01000000; /* clear AC? */
@@ -1283,10 +1286,10 @@ case 034: /* IOT */
#if defined (PDP4)
switch (device) { /* decode IR<6:11> */
case 0: /* CPU and clock */
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = ion_defer = 1; /* ION */
else iot_data = clk (pulse, iot_data);
break;
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = ion_defer = 1; /* ION */
else iot_data = clk (pulse, iot_data);
break;
#endif
/* PDP-7 system IOT's */
@@ -1294,23 +1297,23 @@ case 034: /* IOT */
#if defined (PDP7)
switch (device) { /* decode IR<6:11> */
case 0: /* CPU and clock */
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = ion_defer = 1; /* ION */
else if (pulse == 062) /* ITON */
usmd = ion = ion_defer = 1;
else iot_data = clk (pulse, iot_data);
break;
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = ion_defer = 1; /* ION */
else if (pulse == 062) /* ITON */
usmd = ion = ion_defer = 1;
else iot_data = clk (pulse, iot_data);
break;
case 033: /* CPU control */
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
else if (pulse == 002) reset_all (0); /* CAF */
break;
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
else if (pulse == 002) reset_all (0); /* CAF */
break;
case 077: /* extended memory */
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
else if (pulse == 002) memm = 1; /* EEM */
else if (pulse == 042) /* EMIR */
memm = emir_pending = 1; /* ext on, restore */
else if (pulse == 004) memm = 0; /* LEM */
break;
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
else if (pulse == 002) memm = 1; /* EEM */
else if (pulse == 042) /* EMIR */
memm = emir_pending = 1; /* ext on, restore */
else if (pulse == 004) memm = 0; /* LEM */
break;
#endif
/* PDP-9 and PDP-15 system IOT's */
@@ -1319,73 +1322,73 @@ case 034: /* IOT */
ion_defer = 1; /* delay interrupts */
switch (device) { /* decode IR<6:11> */
case 000: /* CPU and clock */
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = 1; /* ION */
else iot_data = clk (pulse, iot_data);
break;
if (pulse == 002) ion = 0; /* IOF */
else if (pulse == 042) ion = 1; /* ION */
else iot_data = clk (pulse, iot_data);
break;
case 017: /* mem protection */
if ((pulse == 001) && prvn) PC = INCR_ADDR (PC);
else if ((pulse == 041) && nexm) PC = INCR_ADDR (PC);
else if (pulse == 002) prvn = 0;
else if (pulse == 042) usmdbuf = 1;
else if (pulse == 004) BR = LAC & BRMASK;
else if (pulse == 044) nexm = 0;
break;
if ((pulse == 001) && prvn) PC = INCR_ADDR (PC);
else if ((pulse == 041) && nexm) PC = INCR_ADDR (PC);
else if (pulse == 002) prvn = 0;
else if (pulse == 042) usmdbuf = 1;
else if (pulse == 004) BR = LAC & BRMASK;
else if (pulse == 044) nexm = 0;
break;
case 032: /* power fail */
if ((pulse == 001) && (TST_INT (PWRFL)))
PC = INCR_ADDR (PC);
break;
if ((pulse == 001) && (TST_INT (PWRFL)))
PC = INCR_ADDR (PC);
break;
case 033: /* CPU control */
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
else if (pulse == 002) reset_all (0); /* CAF */
else if (pulse == 044) rest_pending = 1; /* DBR */
if (((cpu_unit.flags & UNIT_NOAPI) == 0) && (pulse & 004)) {
int32 t = api_ffo[api_act & 0377];
api_act = api_act & ~(0200 >> t); }
break;
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
else if (pulse == 002) reset_all (0); /* CAF */
else if (pulse == 044) rest_pending = 1; /* DBR */
if (((cpu_unit.flags & UNIT_NOAPI) == 0) && (pulse & 004)) {
int32 t = api_ffo[api_act & 0377];
api_act = api_act & ~(0200 >> t); }
break;
case 055: /* API control */
if (cpu_unit.flags & UNIT_NOAPI) reason = stop_inst;
else if (pulse == 001) { /* SPI */
if (((LAC & SIGN) && api_enb) ||
((LAC & 0377) > api_act))
iot_data = iot_data | IOT_SKP; }
else if (pulse == 002) { /* RPL */
iot_data = iot_data | (api_enb << 17) |
(api_req << 8) | api_act; }
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_act = api_act | (LAC & 0377); }
break;
if (cpu_unit.flags & UNIT_NOAPI) reason = stop_inst;
else if (pulse == 001) { /* SPI */
if (((LAC & SIGN) && api_enb) ||
((LAC & 0377) > api_act))
iot_data = iot_data | IOT_SKP; }
else if (pulse == 002) { /* RPL */
iot_data = iot_data | (api_enb << 17) |
(api_req << 8) | api_act; }
else if (pulse == 004) { /* ISA */
api_enb = (iot_data & SIGN)? 1: 0;
api_req = api_req | ((LAC >> 8) & 017);
api_act = api_act | (LAC & 0377); }
break;
#endif
#if defined (PDP9)
case 077: /* extended memory */
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
else if (pulse == 002) memm = 1; /* EEM */
else if (pulse == 042) /* EMIR */
memm = emir_pending = 1; /* ext on, restore */
else if (pulse == 004) memm = 0; /* LEM */
break;
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
else if (pulse == 002) memm = 1; /* EEM */
else if (pulse == 042) /* EMIR */
memm = emir_pending = 1; /* ext on, restore */
else if (pulse == 004) memm = 0; /* LEM */
break;
#endif
#if defined (PDP15)
case 077: /* bank addressing */
if ((pulse == 041) || ((pulse == 061) && memm))
PC = INCR_ADDR (PC); /* SKP15, SBA */
else if (pulse == 042) rest_pending = 1; /* RES */
else if (pulse == 062) memm = 0; /* DBA */
else if (pulse == 064) memm = 1; /* EBA */
damask = memm? 017777: 07777; /* set dir addr mask */
epcmask = ADDRMASK & ~damask; /* extended PC mask */
break;
if ((pulse == 041) || ((pulse == 061) && memm))
PC = INCR_ADDR (PC); /* SKP15, SBA */
else if (pulse == 042) rest_pending = 1; /* RES */
else if (pulse == 062) memm = 0; /* DBA */
else if (pulse == 064) memm = 1; /* EBA */
damask = memm? 017777: 07777; /* set dir addr mask */
epcmask = ADDRMASK & ~damask; /* extended PC mask */
break;
#endif
/* IOT, continued */
default: /* devices */
if (dev_tab[device]) /* defined? */
iot_data = dev_tab[device] (pulse, iot_data);
else reason = stop_inst; /* stop on flag */
break; } /* end switch device */
if (dev_tab[device]) /* defined? */
iot_data = dev_tab[device] (pulse, iot_data);
else reason = stop_inst; /* stop on flag */
break; } /* end switch device */
LAC = LAC | (iot_data & 0777777);
if (iot_data & IOT_SKP) PC = INCR_ADDR (PC);
if (iot_data >= IOT_REASON) reason = iot_data >> IOT_V_REASON;
@@ -1420,7 +1423,7 @@ if (api_enb == 0) return 0; /* off? no req */
api_req = api_req & ~0360; /* clr req<0:3> */
for (i = 0; i < API_HLVL; i++) { /* loop thru levels */
if (int_hwre[i]) /* req on level? */
api_req = api_req | (0200 >> i); } /* set api req */
api_req = api_req | (0200 >> i); } /* set api req */
hi = api_ffo[api_req & 0377]; /* find hi req */
if (hi < api_ffo[api_act & 0377]) return (hi + 1);
return 0;

5
PDP18B/pdp18b_defs.h
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
22-Nov-02 RMS Added PDP-4 drum support
05-Oct-02 RMS Added DIB structure
25-Jul-02 RMS Added PDP-4 DECtape support
10-Feb-02 RMS Added PDP-7 DECtape support
@@ -51,10 +52,11 @@
integral real time clock
Type 62 line printer (Hollerith)
Type 550/555 DECtape
Type 24 serial drum
PDP7 32K Type 177 EAE Type 649 KSR-33 Teletype
Type 148 mem extension Type 444 paper tape reader
Type 75 paper tape punch
??KA70A bounds control Type 75 paper tape punch
integral real time clock
Type 647B line printer (sixbit)
Type 550/555 DECtape
@@ -103,6 +105,7 @@
#define KSR28 0 /* Baudot terminal */
#define TYPE62 0 /* Hollerith printer */
#define TYPE550 0 /* DECtape */
#define DRM 0 /* drum */
#elif defined (PDP7)
#define ADDRSIZE 15
#define TYPE647 0 /* sixbit printer */

3
PDP18B/pdp18b_doc.txt
View File

@@ -81,6 +81,7 @@ PDP-4 CPU PDP-4 CPU with 8KW of memory
LPT Type 62 line printer (Hollerith code)
CLK integral real-time clock
DT Type 550/555 DECtape
DRM Type 24 serial drum
PDP-7 CPU PDP-7 CPU with 32KW of memory
- Type 177 extended arithmetic element (EAE)
@@ -500,7 +501,7 @@ The serial drum (DRM) implements these registers:
name size comments
DA 9 drum address (sector number)
MA 15 current memory address
MA 16 current memory address
INT 1 interrupt pending flag
DONE 1 device done flag
ERR 1 error flag

30
PDP18B/pdp18b_drm.c
View File

@@ -23,9 +23,10 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
drm (PDP-7) Type 24 serial drum
(PDP-9) RM09 serial drum
drm (PDP-4,PDP-7) Type 24 serial drum
05-Dec-02 RMS Updated from Type 24 documentation
22-Nov-02 RMS Added PDP-4 support
05-Feb-02 RMS Added DIB, device number support
03-Feb-02 RMS Fixed bug in reset routine (found by Robert Alan Byer)
06-Jan-02 RMS Revised enable/disable support
@@ -92,7 +93,7 @@ UNIT drm_unit =
REG drm_reg[] = {
{ ORDATA (DA, drm_da, 9) },
{ ORDATA (MA, drm_ma, 15) },
{ ORDATA (MA, drm_ma, 16) },
{ FLDATA (INT, int_hwre[API_DRM], INT_V_DRM) },
{ FLDATA (DONE, int_hwre[API_DRM], INT_V_DRM) },
{ FLDATA (ERR, drm_err, 0) },
@@ -118,8 +119,8 @@ DEVICE drm_dev = {
int32 drm60 (int32 pulse, int32 AC)
{
if ((pulse & 027) == 06) { /* DRLR, DRLW */
drm_ma = AC & ADDRMASK; /* load mem addr */
drm_unit.FUNC = pulse & 040; } /* save function */
drm_ma = AC & 0177777; /* load mem addr */
drm_unit.FUNC = pulse & DRM_WRITE; } /* save function */
return AC;
}
@@ -135,7 +136,7 @@ if (pulse & 002) { /* DRCF */
if (pulse & 004) { /* DRSS */
drm_da = AC & DRM_SMASK; /* load sector # */
t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
if (t < 0) t = t + DRM_NUMWDT; /* wrap around? */
if (t <= 0) t = t + DRM_NUMWDT; /* wrap around? */
sim_activate (&drm_unit, t * drm_time); } /* schedule op */
return AC;
}
@@ -150,7 +151,7 @@ if (pulse & 004) { /* DRCS */
CLR_INT (DRM); /* clear done */
drm_err = 0; /* clear error */
t = ((drm_da % DRM_NUMSC) * DRM_NUMWDS) - GET_POS (drm_time);
if (t < 0) t = t + DRM_NUMWDT; /* wrap around? */
if (t <= 0) t = t + DRM_NUMWDT; /* wrap around? */
sim_activate (&drm_unit, t * drm_time); } /* schedule op */
return AC;
}
@@ -173,13 +174,14 @@ if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
da = drm_da * DRM_NUMWDS; /* compute dev addr */
for (i = 0; i < DRM_NUMWDS; i++, da++) { /* do transfer */
if (uptr->FUNC == DRM_READ) {
if (MEM_ADDR_OK (drm_ma)) /* read, check nxm */
M[drm_ma] = *(((int32 *) uptr->filebuf) + da); }
else { if ((drm_wlk >> (drm_da >> 4)) & 1) drm_err = 1;
else { *(((int32 *) uptr->filebuf) + da) = M[drm_ma];
if (da >= uptr->hwmark)
uptr->hwmark = da + 1; } }
drm_ma = (drm_ma + 1) & ADDRMASK; } /* incr mem addr */
if (MEM_ADDR_OK (drm_ma)) /* read, check nxm */
M[drm_ma] = *(((int32 *) uptr->filebuf) + da); }
else {
if ((drm_wlk >> (drm_da >> 4)) & 1) drm_err = 1;
else {
*(((int32 *) uptr->filebuf) + da) = M[drm_ma];
if (da >= uptr->hwmark) uptr->hwmark = da + 1; } }
drm_ma = (drm_ma + 1) & 0177777; } /* incr mem addr */
drm_da = (drm_da + 1) & DRM_SMASK; /* incr dev addr */
SET_INT (DRM); /* set done */
return SCPE_OK;

356
PDP18B/pdp18b_dt.c
View File

@@ -430,9 +430,9 @@ if (((pulse & 060) == 040) && (pulse & 05)) { /* select */
if (pulse & 01) dtsa = 0; /* DTCA */
if (pulse & 02) AC = dtsa; /* DTRA!... */
if (pulse & 04) { /* DTXA */
if ((AC & DTA_CERF) == 0) dtsb = dtsb & ~DTB_ALLERR;
if ((AC & DTA_CDTF) == 0) dtsb = dtsb & ~DTB_DTF;
dtsa = dtsa ^ (AC & DTA_RW); }
if ((AC & DTA_CERF) == 0) dtsb = dtsb & ~DTB_ALLERR;
if ((AC & DTA_CDTF) == 0) dtsb = dtsb & ~DTB_DTF;
dtsa = dtsa ^ (AC & DTA_RW); }
if ((old_dtsa ^ dtsa) & DTA_UNIT) dt_deselect (old_dtsa);
uptr = dt_dev.units + DTA_GETUNIT (dtsa); /* get unit */
fnc = DTA_GETFNC (dtsa); /* get fnc */
@@ -440,7 +440,7 @@ if (((pulse & 060) == 040) && (pulse & 05)) { /* select */
(fnc >= FNC_WMRK) || /* write mark? */
((fnc == FNC_WRIT) && (uptr->flags & UNIT_WPRT)) ||
((fnc == FNC_WALL) && (uptr->flags & UNIT_WPRT)))
dt_seterr (uptr, DTB_SEL); /* select err */
dt_seterr (uptr, DTB_SEL); /* select err */
else dt_newsa (dtsa); /* new func */
DT_UPDINT;
return AC; }
@@ -489,10 +489,10 @@ if ((pulse & 001) && (dtsb & DTB_BEF)) /* MMBF */
if (pulse & 002) { /* MMRS */
dtsb = dtsb & ~(DTB_REV | DTB_GO); /* clr rev, go */
if (uptr) { /* valid unit? */
mot = DTS_GETMOT (uptr->STATE); /* get motion */
if (mot & DTS_DIR) dtsb = dtsb | DTB_REV; /* rev? set */
if ((mot >= DTS_ACCF) || (uptr->STATE & 0777700))
dtsb = dtsb | DTB_GO; } /* accel? go */
mot = DTS_GETMOT (uptr->STATE); /* get motion */
if (mot & DTS_DIR) dtsb = dtsb | DTB_REV; /* rev? set */
if ((mot >= DTS_ACCF) || (uptr->STATE & 0777700))
dtsb = dtsb | DTB_GO; } /* accel? go */
AC = (AC & ~DMASK) | dtsb; }
if ((pulse & 044) == 044) { /* MMSE */
if ((dtsa ^ AC) & DTA_UNIT) dt_deselect (dtsa); /* new unit? */
@@ -507,7 +507,7 @@ else if ((pulse & 044) == 004) { /* MMLC */
(fnc >= FNC_WMRK) || /* write mark? */
((fnc == FNC_WRIT) && (uptr->flags & UNIT_WLK)) ||
((fnc == FNC_WALL) && (uptr->flags & UNIT_WLK)))
dt_seterr (uptr, DTB_SEL); /* select err */
dt_seterr (uptr, DTB_SEL); /* select err */
else dt_newsa (dtsa); }
DT_UPDINT;
return AC;
@@ -584,17 +584,17 @@ if (new_mving & ~prev_mving) { /* start? */
if (prev_mving & ~new_mving) { /* stop? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
return; }
if (prev_dir ^ new_dir) { /* dir chg? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
DTS_SET2ND (DTS_ACCF | new_dir, 0); /* next = accel */
DTS_SET3RD (DTS_ATSF | new_dir, new_fnc); /* next next = fnc */
@@ -656,45 +656,46 @@ case DTS_OFR: /* off reel */
case FNC_MOVE: /* move */
dt_schedez (uptr, dir); /* sched end zone */
if (dt_log & LOG_MS) printf ("[DT%d: moving %s]\n", unum, (dir?
"backward": "forward"));
"backward": "forward"));
return; /* done */
case FNC_SRCH: /* search */
if (dir) newpos = DT_BLK2LN ((DT_QFEZ (uptr)?
DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
else newpos = DT_BLK2LN ((DT_QREZ (uptr)?
0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
if (dt_log & LOG_MS) printf ("[DT%d: searching %s]\n", unum,
(dir? "backward": "forward"));
(dir? "backward": "forward"));
break;
case FNC_WRIT: /* write */
case FNC_READ: /* read */
#if defined (TC02) /* TC02/TC15 */
if (DT_QEZ (uptr)) { /* in "ok" end zone? */
if (dir) newpos = DTU_FWDEZ (uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_EZLIN + DT_HTLIN + (DT_WSIZE - 1);
break; }
if (dir) newpos = DTU_FWDEZ (uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_EZLIN + DT_HTLIN + (DT_WSIZE - 1);
break; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dt_seterr (uptr, DTB_SEL);
return; }
dt_seterr (uptr, DTB_SEL);
return; }
if (dir) newpos = DT_BLK2LN (((relpos >= (DTU_LPERB (uptr) - DT_HTLIN))?
blk + 1: blk), uptr) - DT_HTLIN - DT_WSIZE;
blk + 1: blk), uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_BLK2LN (((relpos < DT_HTLIN)?
blk: blk + 1), uptr) + DT_HTLIN + (DT_WSIZE - 1);
blk: blk + 1), uptr) + DT_HTLIN + (DT_WSIZE - 1);
break;
#endif
case FNC_RALL: /* read all */
case FNC_WALL: /* write all */
if (DT_QEZ (uptr)) { /* in "ok" end zone? */
if (dir) newpos = DTU_FWDEZ (uptr) - DT_WSIZE;
else newpos = DT_EZLIN + (DT_WSIZE - 1); }
else { newpos = ((uptr->pos) / DT_WSIZE) * DT_WSIZE;
if (!dir) newpos = newpos + (DT_WSIZE - 1); }
if (dir) newpos = DTU_FWDEZ (uptr) - DT_WSIZE;
else newpos = DT_EZLIN + (DT_WSIZE - 1); }
else {
newpos = ((uptr->pos) / DT_WSIZE) * DT_WSIZE;
if (!dir) newpos = newpos + (DT_WSIZE - 1); }
if ((dt_log & LOG_RA) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: read all block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
printf ("[DT%d: read all block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
break;
default:
dt_seterr (uptr, DTB_SEL); /* bad state */
@@ -759,7 +760,7 @@ if (((int32) uptr->pos < 0) ||
uptr->STATE = uptr->pos = 0;
unum = uptr - dt_dev.units;
if (unum == DTA_GETUNIT (dtsa)) /* if selected, */
dt_seterr (uptr, DTB_SEL); /* error */
dt_seterr (uptr, DTB_SEL); /* error */
return TRUE; }
return FALSE;
}
@@ -789,9 +790,9 @@ t_addr ba;
switch (mot) {
case DTS_DECF: case DTS_DECR: /* decelerating */
if (dt_setpos (uptr)) return SCPE_OK; /* update pos */
uptr->STATE = DTS_NXTSTA (uptr->STATE); /* advance state */
uptr->STATE = DTS_NXTSTA (uptr->STATE); /* advance state */
if (uptr->STATE) /* not stopped? */
sim_activate (uptr, dt_actime); /* must be reversing */
sim_activate (uptr, dt_actime); /* must be reversing */
return SCPE_OK;
case DTS_ACCF: case DTS_ACCR: /* accelerating */
dt_newfnc (uptr, DTS_NXTSTA (uptr->STATE)); /* adv state, sched */
@@ -829,8 +830,8 @@ case DTS_OFR: /* off reel */
#if defined (TC02) /* TC02/TC15 */
case FNC_SRCH: /* search */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DTU_LPERB (uptr) * dt_ltime);/* sched next block */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* inc WC */
ma = M[DT_CA] & ADDRMASK; /* get mem addr */
@@ -856,34 +857,35 @@ case FNC_READ: /* read */
wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
switch (dt_substate) { /* case on substate */
case DTO_SOB: /* start of block */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: reading block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: reading block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
case 0: /* normal read */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dtdb = bptr[ba]; /* get tape word */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
if (MEM_ADDR_OK (ma)) M[ma] = dtdb; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO; /* wc ovf? */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dtdb = bptr[ba]; /* get tape word */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
if (MEM_ADDR_OK (ma)) M[ma] = dtdb; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO; /* wc ovf? */
case DTO_WCO: /* wc ovf, not sob */
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else { dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else {
dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
break;
case DTO_WCO | DTO_SOB: /* next block */
if (wrd == (dir? 0: DTU_BSIZE (uptr))) /* end of block? */
dt_seterr (uptr, DTB_TIM); /* timing error */
dt_seterr (uptr, DTB_TIM); /* timing error */
else sim_activate (uptr, DT_WSIZE * dt_ltime);
break; }
break;
@@ -904,31 +906,32 @@ case FNC_WRIT: /* write */
wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
switch (dt_substate) { /* case on substate */
case DTO_SOB: /* start block */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: writing block %d %s%s\n", unum, blk,
(dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: writing block %d %s%s\n", unum, blk,
(dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
case 0: /* normal write */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
case DTO_WCO: /* wc ovflo */
ma = M[DT_CA] & ADDRMASK; /* mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dtdb = dt_substate? 0: M[ma]; /* get word */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
bptr[ba] = dtdb; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else { dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
ma = M[DT_CA] & ADDRMASK; /* mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dtdb = dt_substate? 0: M[ma]; /* get word */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
bptr[ba] = dtdb; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else {
dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
break;
case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
@@ -944,29 +947,29 @@ case FNC_WRIT: /* write */
case FNC_RALL:
switch (dt_substate) { /* case on substate */
case 0: case DTO_SOB: /* read in progress */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dtdb = bptr[ba]; } /* get tape word */
else dtdb = dt_gethdr (uptr, blk, relpos); /* get hdr */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (MEM_ADDR_OK (ma)) M[ma] = dtdb; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dtdb = bptr[ba]; } /* get tape word */
else dtdb = dt_gethdr (uptr, blk, relpos); /* get hdr */
if (dir) dtdb = dt_comobv (dtdb); /* rev? comp obv */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (MEM_ADDR_OK (ma)) M[ma] = dtdb; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
case DTO_WCO: case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
break;
/* Write all has two subcases
@@ -978,30 +981,30 @@ case FNC_RALL:
case FNC_WALL:
switch (dt_substate) { /* case on substate */
case 0: case DTO_SOB: /* read in progress */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dtdb = M[ma]; /* get mem word */
if (dir) dtdb = dt_comobv (dtdb);
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
bptr[ba] = dtdb; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1; }
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & DMASK; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & DMASK;
ma = M[DT_CA] & ADDRMASK; /* mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dtdb = M[ma]; /* get mem word */
if (dir) dtdb = dt_comobv (dtdb);
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
bptr[ba] = dtdb; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1; }
/* /* ignore hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
case DTO_WCO: case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
break;
/* Type 550 service */
@@ -1010,8 +1013,8 @@ case FNC_WALL:
#else /* Type 550 */
case FNC_SRCH: /* search */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DTU_LPERB (uptr) * dt_ltime);/* sched next block */
dtdb = blk; /* store block # */
dtsb = dtsb | DTB_DTF; /* set DTF */
@@ -1021,27 +1024,28 @@ case FNC_SRCH: /* search */
case FNC_READ: case FNC_RALL:
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DT_WSIZE * dt_ltime); /* sched next word */
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dtdb = bptr[ba]; /* get tape word */
dtsb = dtsb | DTB_DTF; } /* set flag */
else { ma = (2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1;
wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_READ) && /* read, skip if not */
(wrd != DT_CSMWD) && /* fwd, rev cksum */
(wrd != ma)) break;
dtdb = dt_gethdr (uptr, blk, relpos);
if (wrd == (dir? DT_CSMWD: ma)) /* at end csum? */
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dtdb = bptr[ba]; /* get tape word */
dtsb = dtsb | DTB_DTF; } /* set flag */
else {
ma = (2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1;
wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_READ) && /* read, skip if not */
(wrd != DT_CSMWD) && /* fwd, rev cksum */
(wrd != ma)) break;
dtdb = dt_gethdr (uptr, blk, relpos);
if (wrd == (dir? DT_CSMWD: ma)) /* at end csum? */
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
if (dir) dtdb = dt_comobv (dtdb);
break;
@@ -1049,27 +1053,28 @@ case FNC_READ: case FNC_RALL:
case FNC_WRIT: case FNC_WALL:
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DT_WSIZE * dt_ltime); /* sched next word */
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
if (dir) bptr[ba] = dt_comobv (dtdb); /* get data word */
else bptr[ba] = dtdb;
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (wrd == (dir? 0: DTU_BSIZE (uptr) - 1))
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
else { wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_WRIT) && /* wr, skip if !csm */
(wrd != ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1)))
break;
dtsb = dtsb | DTB_DTF; } /* set flag */
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
if (dir) bptr[ba] = dt_comobv (dtdb); /* get data word */
else bptr[ba] = dtdb;
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (wrd == (dir? 0: DTU_BSIZE (uptr) - 1))
dtsb = dtsb | DTB_BEF; /* end block */
else dtsb = dtsb | DTB_DTF; } /* else next word */
else {
wrd = relpos / DT_WSIZE; /* hdr start = wd 0 */
if ((wrd == 0) || /* skip 1st, last */
(wrd == ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - 1))) break;
if ((fnc == FNC_WRIT) && /* wr, skip if !csm */
(wrd != ((2 * DT_HTWRD) + DTU_BSIZE (uptr) - DT_CSMWD - 1)))
break;
dtsb = dtsb | DTB_DTF; } /* set flag */
break;
#endif
@@ -1176,16 +1181,17 @@ UNIT *uptr;
for (i = 0; i < DT_NUMDR; i++) { /* stop all drives */
uptr = dt_dev.units + i;
if (sim_is_running) { /* CAF? */
prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
if (dt_setpos (uptr)) continue; /* update pos */
sim_cancel (uptr);
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
} }
else { sim_cancel (uptr); /* sim reset */
uptr->STATE = 0;
uptr->LASTT = sim_grtime (); } }
prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
if (dt_setpos (uptr)) continue; /* update pos */
sim_cancel (uptr);
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
} }
else {
sim_cancel (uptr); /* sim reset */
uptr->STATE = 0;
uptr->LASTT = sim_grtime (); } }
dtsa = dtsb = 0; /* clear status */
DT_UPDINT; /* reset interrupt */
return SCPE_OK;
@@ -1292,8 +1298,8 @@ if (!(uptr->flags & UNIT_ATT)) return SCPE_OK;
if (sim_is_active (uptr)) {
sim_cancel (uptr);
if ((unum == DTA_GETUNIT (dtsa)) && (dtsa & DTA_STSTP)) {
dtsb = dtsb | DTB_ERF | DTB_SEL | DTB_DTF;
DT_UPDINT; }
dtsb = dtsb | DTB_ERF | DTB_SEL | DTB_DTF;
DT_UPDINT; }
uptr->STATE = uptr->pos = 0; }
bptr = uptr->filebuf; /* file buffer */
if (uptr->hwmark && ((uptr->flags & UNIT_RO) == 0)) { /* any data? */

124
PDP18B/pdp18b_lp.c
View File

@@ -154,22 +154,22 @@ static const char *lpt_cc[] = {
if (lpt_iot & 020) { /* space? */
SET_INT (LPTSPC); /* set flag */
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT);
return IORETURN (lpt_stopioe, SCPE_UNATT);
fputs (lpt_cc[lpt_iot & 07], lpt_unit.fileref); /* print cctl */
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
lpt_iot = 0; } /* clear state */
else { SET_INT (LPT); /* print */
if ((lpt_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT);
return IORETURN (lpt_stopioe, SCPE_UNATT);
if (lpt_iot & 010) fputc ('\r', lpt_unit.fileref);
fputs (lpt_buf, lpt_unit.fileref); /* print buffer */
if (ferror (lpt_unit.fileref)) { /* test error */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; }
bptr = 0;
for (i = 0; i <= LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
lpt_iot = 010; } /* set state */
@@ -253,33 +253,33 @@ if (pulse & 002) { /* pulse 02 */
lpt_done = 0; /* clear done */
CLR_INT (LPT); /* clear int req */
if (subp == 0) { /* LPCB */
for (i = 0; i < LPT_BSIZE; i++) lpt_buf[i] = 0;
bptr = 0; /* reset buf ptr */
lpt_done = 1; /* set done */
if (lpt_ie) SET_INT (LPT); } } /* set int */
for (i = 0; i < LPT_BSIZE; i++) lpt_buf[i] = 0;
bptr = 0; /* reset buf ptr */
lpt_done = 1; /* set done */
if (lpt_ie) SET_INT (LPT); } } /* set int */
if (pulse & 004) { /* LPDI */
switch (subp) { /* case on subcode */
case 0: /* LPDI */
#if defined (PDP9)
lpt_ie = 0; /* clear int enable */
CLR_INT (LPT); /* clear int req */
lpt_ie = 0; /* clear int enable */
CLR_INT (LPT); /* clear int req */
#endif
break;
break;
case 2: /* LPB3 */
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | ((AC >> 12) & 077);
bptr = bptr + 1; }
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | ((AC >> 12) & 077);
bptr = bptr + 1; }
case 1: /* LPB2 */
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | ((AC >> 6) & 077);
bptr = bptr + 1; }
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | ((AC >> 6) & 077);
bptr = bptr + 1; }
case 3: /* LPB1 */
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | (AC & 077);
bptr = bptr + 1; }
lpt_done = 1; /* set done */
if (lpt_ie) SET_INT (LPT); /* set int */
break; } /* end case */
if (bptr < LPT_BSIZE) {
lpt_buf[bptr] = lpt_buf[bptr] | (AC & 077);
bptr = bptr + 1; }
lpt_done = 1; /* set done */
if (lpt_ie) SET_INT (LPT); /* set int */
break; } /* end case */
} /* end if pulse 4 */
return AC;
}
@@ -293,12 +293,12 @@ if (pulse & 002) { /* LPCF */
if (pulse & 004) {
int32 subp = (pulse >> 4) & 03; /* get subpulse */
if (subp < 3) { /* LPLS, LPPB, LPPS */
lpt_iot = (pulse & 060) | (AC & 07); /* save parameters */
sim_activate (&lpt_unit, lpt_unit.wait); } /* activate */
lpt_iot = (pulse & 060) | (AC & 07); /* save parameters */
sim_activate (&lpt_unit, lpt_unit.wait); } /* activate */
#if defined (PDP9)
else { /* LPEI */
lpt_ie = 1; /* set int enable */
if (lpt_done) SET_INT (LPT); }
lpt_ie = 1; /* set int enable */
if (lpt_done) SET_INT (LPT); }
#endif
} /* end if pulse 4 */
return AC;
@@ -332,22 +332,22 @@ if ((lpt_unit.flags & UNIT_ATT) == 0) { /* not attached? */
return IORETURN (lpt_stopioe, SCPE_UNATT); }
if ((lpt_iot & 020) == 0) { /* print? */
for (i = 0; i < bptr; i++) /* translate buffer */
pbuf[i] = lpt_buf[i] | ((lpt_buf[i] >= 040)? 0: 0100);
pbuf[i] = lpt_buf[i] | ((lpt_buf[i] >= 040)? 0: 0100);
if ((lpt_iot & 060) == 0) pbuf[bptr++] = '\r';
for (i = 0; i < LPT_BSIZE; i++) lpt_buf[i] = 0; /* clear buffer */
fwrite (pbuf, 1, bptr, lpt_unit.fileref); /* print buffer */
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
bptr = 0;
return SCPE_IOERR; }
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
bptr = 0;
return SCPE_IOERR; }
bptr = 0; } /* clear buffer ptr */
if (lpt_iot & 060) { /* space? */
fputs (lpt_cc[lpt_iot & 07], lpt_unit.fileref); /* write cctl */
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; } }
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
return SCPE_IOERR; } }
lpt_unit.pos = ftell (lpt_unit.fileref); /* update position */
return SCPE_OK;
}
@@ -505,29 +505,31 @@ for (more = 1; more != 0; ) { /* loop until ctrl */
w1 = M[(M[LPT_CA] + 2) & ADDRMASK]; /* get second word */
M[LPT_CA] = (M[LPT_CA] + 2) & 0777777; /* advance mem addr */
if (mode) { /* unpacked? */
c[0] = w0 & 0177;
c[1] = w1 & 0177;
ccnt = 2; }
else { c[0] = (w0 >> 11) & 0177; /* packed */
c[1] = (w0 >> 4) & 0177;
c[2] = (((w0 << 3) | (w1 >> 15))) & 0177;
c[3] = (w1 >> 8) & 0177;
c[4] = (w1 >> 1) & 0177;
ccnt = 5; }
c[0] = w0 & 0177;
c[1] = w1 & 0177;
ccnt = 2; }
else {
c[0] = (w0 >> 11) & 0177; /* packed */
c[1] = (w0 >> 4) & 0177;
c[2] = (((w0 << 3) | (w1 >> 15))) & 0177;
c[3] = (w1 >> 8) & 0177;
c[4] = (w1 >> 1) & 0177;
ccnt = 5; }
for (i = 0; i < ccnt; i++) { /* loop through */
if ((c[i] <= 037) && ctrl[c[i]]) { /* control char? */
fwrite (lpt_buf, 1, bptr, lpt_unit.fileref);
fputs (ctrl[c[i]], lpt_unit.fileref);
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
bptr = 0;
lpt_updsta (STA_DON | STA_ALM);
return SCPE_IOERR; }
lpt_unit.pos = ftell (lpt_unit.fileref);
bptr = more = 0; }
else { if (bptr < LPT_BSIZE) lpt_buf[bptr++] = c[i];
else lpt_sta = lpt_sta | STA_OVF; } } }
if ((c[i] <= 037) && ctrl[c[i]]) { /* control char? */
fwrite (lpt_buf, 1, bptr, lpt_unit.fileref);
fputs (ctrl[c[i]], lpt_unit.fileref);
if (ferror (lpt_unit.fileref)) { /* error? */
perror ("LPT I/O error");
clearerr (lpt_unit.fileref);
bptr = 0;
lpt_updsta (STA_DON | STA_ALM);
return SCPE_IOERR; }
lpt_unit.pos = ftell (lpt_unit.fileref);
bptr = more = 0; }
else {
if (bptr < LPT_BSIZE) lpt_buf[bptr++] = c[i];
else lpt_sta = lpt_sta | STA_OVF; } } }
lcnt = lcnt - 1; /* decr line count */
if (lcnt) sim_activate (&lpt_unit, lpt_unit.wait); /* more to do? */

96
PDP18B/pdp18b_mt.c
View File

@@ -216,10 +216,11 @@ if (pulse == 004) { /* MTGO */
(((f == FN_SPACER) || (f == FN_REWIND)) & (uptr->USTAT & STA_BOT)) ||
(((f == FN_WRITE) || (f == FN_WREOF)) && (uptr->flags & UNIT_WPRT))
|| ((uptr->flags & UNIT_ATT) == 0) || (f == FN_NOP))
mt_sta = mt_sta | STA_ILL; /* illegal op flag */
else { if (f == FN_REWIND) uptr->USTAT = STA_REW; /* rewind? */
else mt_sta = uptr->USTAT = 0; /* no, clear status */
sim_activate (uptr, mt_time); } } /* start io */
mt_sta = mt_sta | STA_ILL; /* illegal op flag */
else {
if (f == FN_REWIND) uptr->USTAT = STA_REW; /* rewind? */
else mt_sta = uptr->USTAT = 0; /* no, clear status */
sim_activate (uptr, mt_time); } } /* start io */
mt_updcsta (mt_dev.units + GET_UNIT (mt_cu), 0); /* update status */
return AC;
}
@@ -257,8 +258,8 @@ if ((uptr->flags & UNIT_ATT) == 0) { /* if not attached */
if ((f == FN_WRITE) || (f == FN_WREOF)) { /* write? */
if (uptr->flags & UNIT_WPRT) { /* write locked? */
mt_updcsta (uptr, STA_ILL); /* illegal operation */
return SCPE_OK; }
mt_updcsta (uptr, STA_ILL); /* illegal operation */
return SCPE_OK; }
mt_cu = mt_cu & ~CU_ERASE; } /* clear erase flag */
switch (f) { /* case on function */
@@ -268,39 +269,40 @@ switch (f) { /* case on function */
case FN_READ: /* read */
case FN_CMPARE: /* read/compare */
if (mt_rdlntf (uptr, &tbc, &err)) { /* read rec lnt, err? */
mt_updcsta (uptr, STA_RLE); /* set RLE flag */
break; }
mt_updcsta (uptr, STA_RLE); /* set RLE flag */
break; }
if (tbc > MT_MAXFR) return SCPE_MTRLNT; /* record too long? */
wc = DBSIZE - (M[MT_WC] & DBMASK); /* get word count */
cbc = PACKED (mt_cu)? wc * 3: wc * 2; /* expected bc */
if (tbc != cbc) mt_sta = mt_sta | STA_RLE; /* wrong size? */
if (tbc < cbc) { /* record small? */
cbc = tbc; /* use smaller */
wc = PACKED (mt_cu)? ((tbc + 2) / 3): ((tbc + 1) / 2); }
cbc = tbc; /* use smaller */
wc = PACKED (mt_cu)? ((tbc + 2) / 3): ((tbc + 1) / 2); }
abc = fxread (dbuf, sizeof (int8), cbc, uptr->fileref);
if (err = ferror (uptr->fileref)) { /* error */
MT_SET_PNU (uptr); /* pos not upd */
break; }
MT_SET_PNU (uptr); /* pos not upd */
break; }
for ( ; abc < cbc; abc++) dbuf[abc] = 0; /* fill with 0's */
for (i = p = 0; i < wc; i++) { /* copy buffer */
M[MT_WC] = (M[MT_WC] + 1) & 0777777; /* inc WC, CA */
M[MT_CA] = (M[MT_CA] + 1) & 0777777;
xma = M[MT_CA] & ADDRMASK;
if (PACKED (mt_cu)) { /* packed? */
c1 = dbuf[p++] & 077;
c2 = dbuf[p++] & 077;
c3 = dbuf[p++] & 077;
c = (c1 << 12) | (c2 << 6) | c3; }
else { c1 = dbuf[p++];
c2 = dbuf[p++];
c = (c1 << 8) | c2; }
if ((f == FN_READ) && MEM_ADDR_OK (xma)) M[xma] = c;
else if ((f == FN_CMPARE) && (c != (M[xma] &
(PACKED (mt_cu)? 0777777: 0177777)))) {
mt_updcsta (uptr, STA_CPE);
break; } }
M[MT_WC] = (M[MT_WC] + 1) & 0777777; /* inc WC, CA */
M[MT_CA] = (M[MT_CA] + 1) & 0777777;
xma = M[MT_CA] & ADDRMASK;
if (PACKED (mt_cu)) { /* packed? */
c1 = dbuf[p++] & 077;
c2 = dbuf[p++] & 077;
c3 = dbuf[p++] & 077;
c = (c1 << 12) | (c2 << 6) | c3; }
else {
c1 = dbuf[p++];
c2 = dbuf[p++];
c = (c1 << 8) | c2; }
if ((f == FN_READ) && MEM_ADDR_OK (xma)) M[xma] = c;
else if ((f == FN_CMPARE) && (c != (M[xma] &
(PACKED (mt_cu)? 0777777: 0177777)))) {
mt_updcsta (uptr, STA_CPE);
break; } }
uptr->pos = uptr->pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt));
(2 * sizeof (t_mtrlnt));
break;
case FN_WRITE: /* write */
@@ -309,15 +311,16 @@ case FN_WRITE: /* write */
tbc = PACKED (mt_cu)? wc * 3: wc * 2;
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
for (i = p = 0; i < wc; i++) { /* copy buf to tape */
M[MT_WC] = (M[MT_WC] + 1) & 0777777; /* inc WC, CA */
M[MT_CA] = (M[MT_CA] + 1) & 0777777;
xma = M[MT_CA] & ADDRMASK;
if (PACKED (mt_cu)) { /* packed? */
dbuf[p++] = (M[xma] >> 12) & 077;
dbuf[p++] = (M[xma] >> 6) & 077;
dbuf[p++] = M[xma] & 077; }
else { dbuf[p++] = (M[xma] >> 8) & 0377;
dbuf[p++] = M[xma] & 0377; } }
M[MT_WC] = (M[MT_WC] + 1) & 0777777; /* inc WC, CA */
M[MT_CA] = (M[MT_CA] + 1) & 0777777;
xma = M[MT_CA] & ADDRMASK;
if (PACKED (mt_cu)) { /* packed? */
dbuf[p++] = (M[xma] >> 12) & 077;
dbuf[p++] = (M[xma] >> 6) & 077;
dbuf[p++] = M[xma] & 077; }
else {
dbuf[p++] = (M[xma] >> 8) & 0377;
dbuf[p++] = M[xma] & 0377; } }
fxwrite (dbuf, sizeof (char), (tbc + 1) & ~1, uptr->fileref);
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr); /* error? */
@@ -336,17 +339,20 @@ case FN_WREOF:
break;
case FN_SPACEF: /* space forward */
do { if (mt_rdlntf (uptr, &tbc, &err)) break;/* read rec lnt, err? */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt)); }
do {
if (mt_rdlntf (uptr, &tbc, &err)) break; /* read rec lnt, err? */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt)); }
while ((M[MT_WC] = (M[MT_WC] + 1) & 0777777) != 0);
break;
case FN_SPACER: /* space reverse */
do { if (pnu) pnu = 0; /* pos not upd? */
else { if (mt_rdlntf (uptr, &tbc, &err)) break;
uptr->pos = uptr->pos - ((tbc + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); } }
do {
if (pnu) pnu = 0; /* pos not upd? */
else {
if (mt_rdlntf (uptr, &tbc, &err)) break;
uptr->pos = uptr->pos - ((tbc + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); } }
while ((M[MT_WC] = (M[MT_WC] + 1) & 0777777) != 0);
break; } /* end case */

34
PDP18B/pdp18b_rf.c
View File

@@ -182,9 +182,9 @@ if (pulse == 064) { /* DLAH */
if ((pulse & 064) == 044) { /* DSCN */
if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy inhibits */
else if (GET_FNC (rf_sta) != FN_NOP) {
t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new */
if (t < 0) t = t + RF_NUMWD; /* wrap around? */
sim_activate (&rf_unit, t * rf_time); } } /* schedule op */
t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new */
if (t < 0) t = t + RF_NUMWD; /* wrap around? */
sim_activate (&rf_unit, t * rf_time); } } /* schedule op */
rf_updsta (0); /* update status */
return AC;
}
@@ -220,25 +220,25 @@ f = GET_FNC (rf_sta); /* get function */
do { M[RF_WC] = (M[RF_WC] + 1) & 0777777; /* incr word count */
pa = M[RF_CA] = (M[RF_CA] + 1) & ADDRMASK; /* incr mem addr */
if ((f == FN_READ) && MEM_ADDR_OK (pa)) /* read? */
M[pa] = *(((int32 *) uptr->filebuf) + rf_da);
M[pa] = *(((int32 *) uptr->filebuf) + rf_da);
if ((f == FN_WCHK) && /* write check? */
(M[pa] != *(((int32 *) uptr->filebuf) + rf_da))) {
rf_updsta (RFS_WCE); /* flag error */
break; }
rf_updsta (RFS_WCE); /* flag error */
break; }
if (f == FN_WRITE) { /* write? */
d = (rf_da >> 18) & 07; /* disk */
t = (rf_da >> 14) & 017; /* track groups */
if ((rf_wlk[d] >> t) & 1) { /* write locked? */
rf_updsta (RFS_WLO);
break; }
else { *(((int32 *) uptr->filebuf) + rf_da) = M[pa];
if (((t_addr) rf_da) >= uptr->hwmark)
uptr->hwmark = rf_da + 1; } }
d = (rf_da >> 18) & 07; /* disk */
t = (rf_da >> 14) & 017; /* track groups */
if ((rf_wlk[d] >> t) & 1) { /* write locked? */
rf_updsta (RFS_WLO);
break; }
else {
*(((int32 *) uptr->filebuf) + rf_da) = M[pa];
if (((t_addr) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1; } }
rf_da = rf_da + 1; /* incr disk addr */
if (rf_da > RF_SIZE) { /* disk overflow? */
rf_da = 0;
rf_updsta (RFS_NED); /* nx disk error */
break; } }
rf_da = 0;
rf_updsta (RFS_NED); /* nx disk error */
break; } }
while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */

25
PDP18B/pdp18b_rp.c
View File

@@ -226,7 +226,7 @@ if (pulse == 004) { /* DPLA */
if (pulse == 024) { /* DPCS */
rp_sta = rp_sta & ~(STA_HNF | STA_DON);
rp_stb = rp_stb & ~(STB_FME | STB_WPE | STB_LON | STB_WCE |
STB_TME | STB_PGE | STB_EOP);
STB_TME | STB_PGE | STB_EOP);
rp_updsta (0, 0); }
if (pulse == 044) rp_ma = AC; /* DPCA */
if (pulse == 064) rp_wc = AC; /* DPWC */
@@ -261,13 +261,14 @@ if (rp_sta & STA_GO) {
rp_busy = 1; /* set ctrl busy */
rp_sta = rp_sta & ~(STA_HNF | STA_DON); /* clear flags */
rp_stb = rp_stb & ~(STB_FME | STB_WPE | STB_LON | STB_WCE |
STB_TME | STB_PGE | STB_EOP | (1 << (STB_V_ATT0 - u)));
STB_TME | STB_PGE | STB_EOP | (1 << (STB_V_ATT0 - u)));
if (((uptr->flags & UNIT_ATT) == 0) || (f == FN_IDLE) ||
(f == FN_SEEK) || (f == FN_RECAL))
sim_activate (uptr, RP_MIN); /* short delay */
else { c = GET_CYL (rp_da);
c = abs (c - uptr->CYL) * rp_swait; /* seek time */
sim_activate (uptr, MAX (RP_MIN, c + rp_rwait)); } }
sim_activate (uptr, RP_MIN); /* short delay */
else {
c = GET_CYL (rp_da);
c = abs (c - uptr->CYL) * rp_swait; /* seek time */
sim_activate (uptr, MAX (RP_MIN, c + rp_rwait)); } }
rp_updsta (0, 0);
return AC;
}
@@ -346,14 +347,14 @@ if ((f == FN_WRITE) && (err == 0)) { /* write? */
fxwrite (&M[pa], sizeof (int32), wc, uptr->fileref);
err = ferror (uptr->fileref);
if ((err == 0) && (i = (wc & (RP_NUMWD - 1)))) {
fxwrite (fill, sizeof (int), i, uptr->fileref);
err = ferror (uptr->fileref); } }
fxwrite (fill, sizeof (int), i, uptr->fileref);
err = ferror (uptr->fileref); } }
if ((f == FN_WRCHK) && (err == 0)) { /* write check? */
for (i = 0; (err == 0) && (i < wc); i++) {
awc = fxread (&comp, sizeof (int32), 1, uptr->fileref);
if (awc == 0) comp = 0;
if (comp != M[pa + i]) rp_updsta (0, STB_WCE); }
awc = fxread (&comp, sizeof (int32), 1, uptr->fileref);
if (awc == 0) comp = 0;
if (comp != M[pa + i]) rp_updsta (0, STB_WCE); }
err = ferror (uptr->fileref); }
rp_wc = (rp_wc + wc) & 0777777; /* final word count */
@@ -389,7 +390,7 @@ if ((uptr->flags & UNIT_ATT) == 0) rp_stb = rp_stb | STB_SUFU | STB_SUNR;
else if (sim_is_active (uptr)) {
f = (uptr->FUNC) & STA_M_FUNC;
if ((f == FN_SEEK) || (f == FN_RECAL))
rp_stb = rp_stb | STB_SUSU | STB_SUNR; }
rp_stb = rp_stb | STB_SUSU | STB_SUNR; }
else if (uptr->CYL >= RP_NUMCY) rp_sta = rp_sta | STA_SUSI;
if ((rp_sta & STA_EFLGS) || (rp_stb & STB_EFLGS)) rp_sta = rp_sta | STA_ERR;
if (((rp_sta & (STA_ERR | STA_DON)) && (rp_sta & STA_IED)) ||

31
PDP18B/pdp18b_stddev.c
View File

@@ -29,6 +29,7 @@
tto teleprinter
clk clock
22-Dec-02 RMS Added break support
01-Nov-02 RMS Added 7B/8B support to terminal
05-Oct-02 RMS Added DIBs, device number support, IORS call
14-Jul-02 RMS Added ASCII reader/punch support (from Hans Pufal)
@@ -350,11 +351,11 @@ if (pulse & 001) { /* CLSF */
if (TST_INT (CLK)) AC = AC | IOT_SKP; }
if (pulse & 004) { /* CLON/CLOF */
if (pulse & 040) { /* CLON */
CLR_INT (CLK); /* clear flag */
clk_state = 1; /* clock on */
if (!sim_is_active (&clk_unit)) /* already on? */
sim_activate (&clk_unit, /* start, calibr */
sim_rtc_init (clk_unit.wait)); }
CLR_INT (CLK); /* clear flag */
clk_state = 1; /* clock on */
if (!sim_is_active (&clk_unit)) /* already on? */
sim_activate (&clk_unit, /* start, calibr */
sim_rtc_init (clk_unit.wait)); }
else clk_reset (&clk_dev); } /* CLOF */
return AC;
}
@@ -427,8 +428,8 @@ if ((temp = getc (ptr_unit.fileref)) == EOF) { /* end of file? */
ptr_err = 1;
#endif
if (feof (ptr_unit.fileref)) {
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
else perror ("PTR I/O error");
clearerr (ptr_unit.fileref);
return SCPE_IOERR; }
@@ -671,7 +672,7 @@ if (pulse & 002) CLR_INT (PTP); /* PCF */
if (pulse & 004) { /* PSA, PSB, PLS */
CLR_INT (PTP); /* clear flag */
ptp_unit.buf = (pulse & 040)? /* load punch buf */
(AC & 077) | 0200: AC & 0377; /* bin or alpha */
(AC & 077) | 0200: AC & 0377; /* bin or alpha */
sim_activate (&ptp_unit, ptp_unit.wait); } /* activate unit */
return AC;
}
@@ -687,7 +688,7 @@ if ((ptp_unit.flags & UNIT_ATT) == 0) { /* not attached? */
if (ptp_unit.flags & UNIT_PASCII) { /* ASCII mode? */
ptp_unit.buf = ptp_unit.buf & 0177; /* force 7b */
if ((ptp_unit.buf == 0) || (ptp_unit.buf == 0177))
return SCPE_OK; } /* skip null, del */
return SCPE_OK; } /* skip null, del */
if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* I/O error? */
ptp_err = 1; /* set error */
perror ("PTP I/O error");
@@ -771,9 +772,10 @@ else { if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c;
if (c == 0) return SCPE_OK; /* untranslatable? */
if (((c & TTI_FIGURES) == (tti_state & TTI_FIGURES)) ||
(c & TTI_BOTH)) tti_unit.buf = c & TTI_MASK;
else { tti_unit.buf = (c & TTI_FIGURES)?
BAUDOT_FIGURES: BAUDOT_LETTERS;
tti_state = c | TTI_2ND; } } /* set 2nd waiting */
else {
tti_unit.buf = (c & TTI_FIGURES)?
BAUDOT_FIGURES: BAUDOT_LETTERS;
tti_state = c | TTI_2ND; } } /* set 2nd waiting */
#else /* ASCII... */
int32 c, out;
@@ -781,11 +783,12 @@ int32 c, out;
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
out = c & 0177; /* mask echo to 7b */
if (tti_unit.flags & UNIT_KSR) { /* KSR? */
if (c & SCPE_BREAK) c = 0; /* break? */
else if (tti_unit.flags & UNIT_KSR) { /* KSR? */
if (islower (out)) out = toupper (out); /* convert to UC */
c = out | 0200; } /* set TTY bit */
else c = c & ((tti_unit.flags & UNIT_8B)? 0377: 0177); /* no, 7b/8b */
if ((tti_unit.flags & UNIT_HDX) && /* half duplex and */
if ((tti_unit.flags & UNIT_HDX) && out && /* half duplex and */
(!(tto_unit.flags & UNIT_KSR) || /* 7b/8b or */
((out >= 007) && (out <= 0137)))) { /* in range? */
sim_putchar (out); /* echo */

168
PDP18B/pdp18b_sys.c
View File

@@ -136,9 +136,9 @@ int32 word, bits, st, ch;
word = st = bits = 0;
do { if ((ch = getc (fileref)) == EOF) return -1;
if (ch & 0200) {
word = (word << 6) | (ch & 077);
bits = (bits << 1) | ((ch >> 6) & 1);
st++; } }
word = (word << 6) | (ch & 077);
bits = (bits << 1) | ((ch >> 6) & 1);
st++; } }
while (st < 3);
if (hi != NULL) *hi = bits;
return word;
@@ -165,12 +165,12 @@ if ((*cptr != 0) || (flag != 0)) return SCPE_ARG;
for (;;) {
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
if ((val & 0760000) == 0040000) { /* DAC? */
origin = val & 017777;
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
origin = val & 017777;
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
else if ((val & 0760000) == OP_JMP) { /* JMP? */
saved_PC = ((origin - 1) & 060000) | (val & 017777);
return SCPE_OK; }
saved_PC = ((origin - 1) & 060000) | (val & 017777);
return SCPE_OK; }
else if (val == OP_HLT) return SCPE_OK; /* HLT? */
else return SCPE_FMT; } /* error */
return SCPE_FMT; /* error */
@@ -211,20 +211,20 @@ extern t_bool match_ext (char *fnm, char *ext);
if ((sim_switches & SWMASK ('R')) || /* RIM format? */
(match_ext (fnam, "RIM") && !(sim_switches & SWMASK ('B')))) {
if (*cptr != 0) { /* more input? */
cptr = get_glyph (cptr, gbuf, 0); /* get origin */
origin = get_uint (gbuf, 8, ADDRMASK, &r);
if (r != SCPE_OK) return r;
if (*cptr != 0) return SCPE_ARG; } /* no more */
cptr = get_glyph (cptr, gbuf, 0); /* get origin */
origin = get_uint (gbuf, 8, ADDRMASK, &r);
if (r != SCPE_OK) return r;
if (*cptr != 0) return SCPE_ARG; } /* no more */
else origin = 0200; /* default 200 */
for (;;) { /* word loop */
if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;
if (bits & 1) { /* end of tape? */
if ((val & 0760000) == OP_JMP) saved_PC =
((origin - 1) & 060000) | (val & 017777);
else if (val != OP_HLT) return SCPE_FMT;
break; }
else if (MEM_ADDR_OK (origin)) M[origin++] = val; }
if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;
if (bits & 1) { /* end of tape? */
if ((val & 0760000) == OP_JMP) saved_PC =
((origin - 1) & 060000) | (val & 017777);
else if (val != OP_HLT) return SCPE_FMT;
break; }
else if (MEM_ADDR_OK (origin)) M[origin++] = val; }
return SCPE_OK; }
/* Binary loader */
@@ -236,8 +236,8 @@ if (val == EOF) rewind (fileref); /* no RIM? rewind */
for (;;) { /* block loop */
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
if (val & SIGN) {
if (val != DMASK) saved_PC = val & 077777;
break; }
if (val != DMASK) saved_PC = val & 077777;
break; }
cksum = origin = val; /* save origin */
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
cksum = cksum + val; /* add to cksum */
@@ -245,9 +245,9 @@ for (;;) { /* block loop */
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
cksum = cksum + val; /* add to cksum */
for (i = 0; i < count; i++) {
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
cksum = cksum + val;
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;
cksum = cksum + val;
if (MEM_ADDR_OK (origin)) M[origin++] = val; }
if ((cksum & DMASK) != 0) return SCPE_CSUM; }
return SCPE_OK;
}
@@ -607,9 +607,9 @@ int32 i, j;
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
return sp;
}
@@ -665,58 +665,57 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
switch (j) { /* case on class */
case I_V_NPN: /* no operands */
case I_V_XR: /* index no opers */
fprintf (of, "%s", opcode[i]); /* opcode */
break;
fprintf (of, "%s", opcode[i]); /* opcode */
break;
case I_V_NPI: /* IOT no operand */
fprintf (of, "%s", opcode[i]); /* opcode */
if (inst & 010) fprintf (of, " +10");
break;
fprintf (of, "%s", opcode[i]); /* opcode */
if (inst & 010) fprintf (of, " +10");
break;
case I_V_IOT: /* IOT or EAE */
fprintf (of, "%s %-o", opcode[i], inst & 037777);
break;
fprintf (of, "%s %-o", opcode[i], inst & 037777);
break;
case I_V_MRF: /* mem ref */
#if defined (PDP15)
if (memm) {
disp = inst & 017777;
ma = (addr & 0760000) | disp; }
else { disp = inst & 007777;
ma = (addr & 0770000) | disp; }
fprintf (of, "%s %-o", opcode[i],
(cflag? ma & ADDRMASK: disp));
if (!memm && (inst & 0010000)) fprintf (of, ",X");
if (memm) {
disp = inst & 017777;
ma = (addr & 0760000) | disp; }
else {
disp = inst & 007777;
ma = (addr & 0770000) | disp; }
fprintf (of, "%s %-o", opcode[i], (cflag? ma & ADDRMASK: disp));
if (!memm && (inst & 0010000)) fprintf (of, ",X");
#else
disp = inst & 017777;
ma = (addr & 0760000) | disp;
fprintf (of, "%s %-o", opcode[i],
(cflag? ma & ADDRMASK: disp));
disp = inst & 017777;
ma = (addr & 0760000) | disp;
fprintf (of, "%s %-o", opcode[i], (cflag? ma & ADDRMASK: disp));
#endif
break;
case I_V_OPR: /* operate */
if (sp = (inst & 03730)) fprintf (of, "%s", opcode[i]);
fprint_opr (of, inst & 014047, I_V_OPR, sp);
break;
if (sp = (inst & 03730)) fprintf (of, "%s", opcode[i]);
fprint_opr (of, inst & 014047, I_V_OPR, sp);
break;
case I_V_LAW: /* LAW */
fprintf (of, "%s %-o", opcode[i], inst & 017777);
break;
fprintf (of, "%s %-o", opcode[i], inst & 017777);
break;
case I_V_XR9: /* index with lit */
disp = inst & 0777;
if (disp & 0400) fprintf (of, "%s -%-o", opcode[i], 01000 - disp);
else fprintf (of, "%s %-o", opcode[i], disp);
break;
disp = inst & 0777;
if (disp & 0400) fprintf (of, "%s -%-o", opcode[i], 01000 - disp);
else fprintf (of, "%s %-o", opcode[i], disp);
break;
case I_V_EST: /* EAE setup */
fprint_opr (of, inst & 037007, I_V_EST, 0);
break;
fprint_opr (of, inst & 037007, I_V_EST, 0);
break;
case I_V_ESH: /* EAE shift */
sp = fprint_opr (of, inst & 017000, I_V_EST, 0);
fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);
break;
sp = fprint_opr (of, inst & 017000, I_V_EST, 0);
fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);
break;
case I_V_EMD: /* EAE mul-div */
disp = inst & 077; /* get actual val */
k = (opc_val[i] >> I_V_DC) & 077; /* get default val */
if (disp == k) fprintf (of, "%s", opcode[i]);
else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);
else fprintf (of, "%s +%-o", opcode[i], disp - k);
break; } /* end case */
disp = inst & 077; /* get actual val */
k = (opc_val[i] >> I_V_DC) & 077; /* get default val */
if (disp == k) fprintf (of, "%s", opcode[i]);
else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);
else fprintf (of, "%s +%-o", opcode[i], disp - k);
break; } /* end case */
return SCPE_OK; } /* end if */
} /* end for */
return SCPE_ARG;
@@ -804,7 +803,7 @@ case I_V_XR9: /* index literal */
d = get_sint (gbuf, &sign, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (((sign >= 0) && (d > 0377)) || ((sign < 0) && (d > 0400)))
return SCPE_ARG;
return SCPE_ARG;
val[0] = val[0] | ((sign >= 0)? d: (01000 - d));
break;
case I_V_LAW: /* law */
@@ -824,22 +823,22 @@ case I_V_MRF: /* mem ref */
#endif
#if defined (PDP4) || defined (PDP7)
if (strcmp (gbuf, "I") == 0) { /* indirect? */
val[0] = val[0] | 020000;
cptr = get_glyph (cptr, gbuf, 0); }
val[0] = val[0] | 020000;
cptr = get_glyph (cptr, gbuf, 0); }
#endif
epcmask = ADDRMASK & ~dmask; /* get ePC */
d = get_uint (gbuf, 8, ADDRMASK, &r); /* get addr */
if (r != SCPE_OK) return SCPE_ARG;
if (d <= dmask) val[0] = val[0] | d; /* fit in 12/13b? */
else if (cflag && (((addr ^ d) & epcmask) == 0))
val[0] = val[0] | (d & dmask); /* hi bits = ePC? */
val[0] = val[0] | (d & dmask); /* hi bits = ePC? */
else return SCPE_ARG;
#if defined (PDP15)
if (!memm) {
cptr = get_glyph (cptr, gbuf, 0);
if (gbuf[0] != 0) {
if (strcmp (gbuf, "X") != 0) return SCPE_ARG;
val[0] = val[0] | 010000; } }
cptr = get_glyph (cptr, gbuf, 0);
if (gbuf[0] != 0) {
if (strcmp (gbuf, "X") != 0) return SCPE_ARG;
val[0] = val[0] | 010000; } }
#endif
break;
case I_V_EMD: /* or'able */
@@ -848,17 +847,18 @@ case I_V_EST: case I_V_ESH:
case I_V_NPN: case I_V_NPI: case I_V_IOT: case I_V_OPR:
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] != NULL) {
k = opc_val[i] & DMASK;
if (((k ^ val[0]) & 0740000) != 0) return SCPE_ARG;
val[0] = val[0] | k; }
else { d = get_sint (gbuf, & sign, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (sign > 0) val[0] = val[0] + d;
else if (sign < 0) val[0] = val[0] - d;
else val[0] = val[0] | d; } }
if (opcode[i] != NULL) {
k = opc_val[i] & DMASK;
if (((k ^ val[0]) & 0740000) != 0) return SCPE_ARG;
val[0] = val[0] | k; }
else {
d = get_sint (gbuf, & sign, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (sign > 0) val[0] = val[0] + d;
else if (sign < 0) val[0] = val[0] - d;
else val[0] = val[0] | d; } }
break; } /* end case */
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
return SCPE_OK;

8
PDP18B/pdp18b_tt1.c
View File

@@ -26,6 +26,7 @@
tti1 keyboard
tto1 teleprinter
22-Dec-02 RMS Added break support
02-Nov-02 RMS Added 7B/8B support
05-Oct-02 RMS Added DIB, device number support
22-Aug-02 RMS Updated for changes to sim_tmxr
@@ -167,11 +168,12 @@ int32 c, newln;
if (tt1_ldsc.conn) { /* connected? */
tmxr_poll_rx (&tt_desc); /* poll for input */
if (c = tmxr_getc_ln (&tt1_ldsc)) { /* get char */
if (uptr->flags & UNIT_KSR) { /* KSR? */
if (c & SCPE_BREAK) uptr->buf = 0; /* break? */
else if (uptr->flags & UNIT_KSR) { /* KSR? */
c = c & 0177;
if (islower (c)) c = toupper (c);
uptr->buf = c | 0200; } /* got char */
else c = c & ((tti1_unit.flags & UNIT_8B)? 0377: 0177);
else uptr->buf = c & ((tti1_unit.flags & UNIT_8B)? 0377: 0177);
SET_INT (TTI1); } /* set flag */
sim_activate (uptr, uptr->wait); } /* continue poll */
if (uptr->flags & UNIT_ATT) { /* attached? */
@@ -306,4 +308,4 @@ t_stat tt1_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)
tti1_unit.flags = (tti1_unit.flags & ~(UNIT_KSR | UNIT_8B)) | val;
tto1_unit.flags = (tto1_unit.flags & ~(UNIT_KSR | UNIT_8B)) | val;
return SCPE_OK;
}
}