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Notes For V2.10-2
1. New Features in 2.10-2
The build procedures have changed. There is only one UNIX makefile.
To compile without Ethernet support, simply type
gmake {target|all}
To compile with Ethernet support, type
gmake USE_NETWORK=1 {target|all}
The Mingw batch files require Mingw release 2 and invoke the Unix
makefile. There are still separate batch files for compilation
with or without Ethernet support.
1.1 SCP and Libraries
- The EVAL command will evaluate a symbolic type-in and display
it in numeric form.
- The ! command (with no arguments) will launch the host operating
system command shell. The ! command (with an argument) executes
the argument as a host operating system command. (Code from
Mark Pizzolato)
- Telnet sessions now recognize BREAK. How a BREAK is transmitted
dependent on the particular Telnet client. (Code from Mark
Pizzolato)
- The sockets library includes code for active connections as
well as listening connections.
- The RESTORE command will restore saved memory size, if the
simulator supports dynamic memory resizing.
1.2 PDP-1
- The PDP-1 supports the Type 24 serial drum (based on recently
discovered documents).
1.3 18b PDP's
- The PDP-4 supports the Type 24 serial drum (based on recently
discovered documents).
1.4 PDP-11
- The PDP-11 implements a stub DEUNA/DELUA (XU). The real XU
module will be included in a later release.
1.5 PDP-10
- The PDP-10 implements a stub DEUNA/DELUA (XU). The real XU
module will be included in a later release.
1.6 HP 2100
- The IOP microinstruction set is supported for the 21MX as well
as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).
1.7 VAX
- If the VAX console is attached to a Telnet session, BREAK is
interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
the most recently executed instructions. (Code from Mark
Pizzolato)
1.8 Terminals Multiplexors
- BREAK detection was added to the HP, DEC, and Interdata terminal
multiplexors.
1.9 Interdata 16b and 32b
- First release. UNIX is not yet working.
1.10 SDS 940
- First release.
2. Bugs Fixed in 2.10-2
- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
(found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
descriptors (found by Mark Pizzolato).
3. New Features in 2.10 vs prior releases
3.1 SCP and Libraries
- The VT emulation package has been replaced by the capability
to remote the console to a Telnet session. Telnet clients
typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
in addition to dynamically allocated buffers or disk-based
data stores.
- The DO command now takes substitutable arguments (max 9).
In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
name and substitutable arguments for a DO command. This is
backward compatible to prior versions.
- The initial command line parses switches. -Q is interpreted
as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument. HELP <cmd>
types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
as well as simulator-specific command extensions. A few
internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
been added to sim_tmxr.c. The calling sequence for
sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.
3.2 VAX
- Non-volatile RAM (NVR) can behave either like a memory or like
a disk-based peripheral. If unattached, it behaves like memory
and is saved and restored by SAVE and RESTORE, respectively.
If attached, its contents are loaded from disk by ATTACH and
written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
A few devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
the CPU.
- Device address conflicts are not detected until simulation starts.
3.3 PDP-11
- SHOW <device> VECTOR displays the device's interrupt vector.
Most devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
RX211 (double density floppy), and KW11P programmable clock
have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
SET ADDRESS command, rather than just the default CSR. Note
that PDP-11 operating systems may NOT support booting with
non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
configuration, causes all peripherals that are not compatible
with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.
3.4 PDP-10
- SHOW <device> VECTOR displays the device's interrupt vector.
A few devices allow the vector to be changed with SET
<device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
by default.
- The paper tape now references a common implementation file,
dec_pt.h.
- Device address conflicts are not detected until simulation starts.
3.5 PDP-1
- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.
3.6 PDP-8
- The RX28 (double density floppy) has been added as an option to
the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number. Most
devices allow the device number to be changed with SET <device>
DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.
3.7 IBM 1620
- The IBM 1620 simulator has been released.
3.8 AltairZ80
- A hard drive has been added for increased storage.
- Several bugs have been fixed.
3.9 HP 2100
- The 12845A has been added and made the default line printer (LPT).
The 12653A has been renamed LPS and is off by default. It also
supports the diagnostic functions needed to run the DCPC and DMS
diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
instructions for the 2116. These instructions are standard on
the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
instructions for the 21MX.
- The 12539 timebase generator autocalibrates.
3.10 Simulated Magtapes
- Simulated magtapes recognize end of file and the marker
0xFFFFFFFF as end of medium. Only the TMSCP tape simulator
can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
consistent through all simulators.
3.11 Simulated DECtapes
- Added support for RT11 image file format (256 x 16b) to DECtapes.
4. Bugs Fixed in 2.10 vs prior releases
- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
under VMS. In addition, two of the CTL options were coded
interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
load mode reads. This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
21MX, DMS, and IOP instructions were fixed. Bugs were also fixed
in the memory protect and DMS functions. The moving head disks
(DP, DQ) were revised to simulate the hardware more accurately.
Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
both input and output (found by Derek Peschel)
5. General Notes
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX. Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.
WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.
WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.
WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file. Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
4ea745b3ad
commit
2bcd1e7c4c
@@ -519,18 +519,18 @@ extern UNIT clk_unit;
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#if defined (PDP9)
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#define CHECK_AUTO_INC \
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if ((IR & 017770) == 010) { \
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MA = MA & 017; \
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M[MA] = (M[MA] + 1) & 0777777; }
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MA = MA & 017; \
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M[MA] = (M[MA] + 1) & 0777777; }
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#define INDIRECT \
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MA = memm? M[MA] & IAMASK: (MA & epcmask) | (M[MA] & damask)
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#define CHECK_ADDR_R(x) \
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if (usmd) { \
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if (!MEM_ADDR_OK (x)) { \
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nexm = prvn = trap_pending = 1; \
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break; } \
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if ((x) < BR) { \
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prvn = trap_pending = 1; \
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break; } } \
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if (!MEM_ADDR_OK (x)) { \
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nexm = prvn = trap_pending = 1; \
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break; } \
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if ((x) < BR) { \
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prvn = trap_pending = 1; \
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break; } } \
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if (!MEM_ADDR_OK (x)) nexm = 1
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#define CHECK_INDEX /* no indexing capability */
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#define CHECK_ADDR_W(x) \
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@@ -550,28 +550,28 @@ extern UNIT clk_unit;
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#if defined (PDP15)
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#define CHECK_AUTO_INC \
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if ((IR & damask & ~07) == 00010) { \
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MA = MA & 017; \
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M[MA] = (M[MA] + 1) & 0777777; }
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MA = MA & 017; \
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M[MA] = (M[MA] + 1) & 0777777; }
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#define INDIRECT \
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if (rest_pending) { \
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rest_pending = 0; \
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LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777); \
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memm = (M[MA] >> 16) & 1; \
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usmd = (M[MA] >> 15) & 1; } \
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rest_pending = 0; \
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LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777); \
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memm = (M[MA] >> 16) & 1; \
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usmd = (M[MA] >> 15) & 1; } \
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MA = ((IR & damask & ~07) != 00010)? \
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(PC & BLKMASK) | (M[MA] & IAMASK): (M[MA] & ADDRMASK); \
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(PC & BLKMASK) | (M[MA] & IAMASK): (M[MA] & ADDRMASK); \
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damask = memm? 017777: 07777; \
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epcmask = ADDRMASK & ~damask
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#define CHECK_INDEX \
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if ((IR & 0010000) && (memm == 0)) MA = (MA + XR) & ADDRMASK
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#define CHECK_ADDR_R(x) \
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if (usmd) { \
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if (!MEM_ADDR_OK (x)) { \
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nexm = prvn = trap_pending = 1; \
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break; } \
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if ((x) < BR) { \
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prvn = trap_pending = 1; \
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break; } } \
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if (!MEM_ADDR_OK (x)) { \
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nexm = prvn = trap_pending = 1; \
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break; } \
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if ((x) < BR) { \
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prvn = trap_pending = 1; \
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break; } } \
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if (!MEM_ADDR_OK (x)) nexm = 1
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#define CHECK_ADDR_W(x) \
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CHECK_ADDR_R (x); \
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@@ -644,16 +644,17 @@ if (api_int && !ion_defer) { /* API intr? */
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int32 i, lvl = api_int - 1; /* get req level */
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api_act = api_act | (0200 >> lvl); /* set level active */
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if (lvl >= API_HLVL) { /* software req? */
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MA = ACH_SWRE + lvl - API_HLVL; /* vec = 40:43 */
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api_req = api_req & ~(0200 >> lvl); } /* remove request */
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else { MA = 0; /* assume fails */
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for (i = 0; i < 32; i++) { /* loop hi to lo */
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if ((int_hwre[lvl] >> i) & 1) { /* int req set? */
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MA = api_vec[lvl][i]; /* get vector */
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break; } } } /* and stop */
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MA = ACH_SWRE + lvl - API_HLVL; /* vec = 40:43 */
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api_req = api_req & ~(0200 >> lvl); } /* remove request */
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else {
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MA = 0; /* assume fails */
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for (i = 0; i < 32; i++) { /* loop hi to lo */
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if ((int_hwre[lvl] >> i) & 1) { /* int req set? */
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MA = api_vec[lvl][i]; /* get vector */
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break; } } } /* and stop */
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if (MA == 0) { /* bad channel? */
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reason = STOP_API; /* API error */
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break; }
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reason = STOP_API; /* API error */
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break; }
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api_int = api_eval (&int_pend); /* no API int */
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api_cycle = 1; /* in API cycle */
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emir_pending = rest_pending = 0; /* emir, restore off */
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@@ -687,11 +688,11 @@ if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */
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#if defined (PDP9) || defined (PDP15)
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if (usmd) { /* user mode? */
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if (!MEM_ADDR_OK (PC)) { /* nxm? */
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nexm = prvn = trap_pending = 1; /* abort fetch */
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continue; } \
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nexm = prvn = trap_pending = 1; /* abort fetch */
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continue; }
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if (PC < BR) { /* bounds viol? */
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prvn = trap_pending = 1; /* abort fetch */
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continue; } }
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prvn = trap_pending = 1; /* abort fetch */
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continue; } }
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else if (!MEM_ADDR_OK (PC)) nexm = 1; /* flag nxm */
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if (!ion_defer) usmd = usmdbuf; /* no IOT? load usmd */
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#endif
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@@ -819,11 +820,11 @@ case 020: /* XCT, dir */
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CHECK_INDEX;
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CHECK_ADDR_R (MA);
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if (usmd && (xct_count != 0)) { /* trap and chained? */
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prvn = trap_pending = 1;
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break; }
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prvn = trap_pending = 1;
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break; }
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if (xct_count >= xct_max) { /* too many XCT's? */
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reason = STOP_XCT;
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break; }
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reason = STOP_XCT;
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break; }
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xct_count = xct_count + 1; /* count XCT's */
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#if defined (PDP9)
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ion_defer = 1; /* defer intr */
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@@ -848,8 +849,8 @@ case 001: case 000: /* CAL */
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#if defined (PDP9) || defined (PDP15)
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usmd = 0; /* clear user mode */
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if ((cpu_unit.flags & UNIT_NOAPI) == 0) { /* if API, act lvl 4 */
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api_act = api_act | 010;
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api_int = api_eval (&int_pend); }
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api_act = api_act | 010;
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api_int = api_eval (&int_pend); }
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#endif
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if (IR & 0020000) { INDIRECT; } /* indirect? */
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CHECK_ADDR_W (MA);
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@@ -885,9 +886,9 @@ CHECK_AUTO_INC; /* check auto inc */
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#endif
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#if defined (PDP9)
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if (rest_pending) { /* restore pending? */
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LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777);
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memm = (M[MA] >> 16) & 1;
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usmd = (M[MA] >> 15) & 1; }
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LAC = ((M[MA] << 1) & 01000000) | (LAC & 0777777);
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memm = (M[MA] >> 16) & 1;
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usmd = (M[MA] >> 15) & 1; }
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#endif
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INDIRECT; /* complete indirect */
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emir_pending = rest_pending = 0;
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@@ -907,147 +908,147 @@ case 036: /* OPR, dir */
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skp = 0; /* assume no skip */
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switch ((IR >> 6) & 017) { /* decode IR<8:11> */
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case 0: /* nop */
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break;
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break;
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case 1: /* SMA */
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if ((LAC & 0400000) != 0) skp = 1;
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break;
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if ((LAC & 0400000) != 0) skp = 1;
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break;
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case 2: /* SZA */
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if ((LAC & 0777777) == 0) skp = 1;
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break;
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if ((LAC & 0777777) == 0) skp = 1;
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break;
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case 3: /* SZA | SMA */
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if (((LAC & 0777777) == 0) || ((LAC & 0400000) != 0))
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skp = 1;
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break;
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if (((LAC & 0777777) == 0) || ((LAC & 0400000) != 0))
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skp = 1;
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break;
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case 4: /* SNL */
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if (LAC >= 01000000) skp = 1;
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break;
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if (LAC >= 01000000) skp = 1;
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break;
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case 5: /* SNL | SMA */
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if (LAC >= 0400000) skp = 1;
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break;
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if (LAC >= 0400000) skp = 1;
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break;
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case 6: /* SNL | SZA */
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if ((LAC >= 01000000) || (LAC == 0)) skp = 1;
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break;
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if ((LAC >= 01000000) || (LAC == 0)) skp = 1;
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break;
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case 7: /* SNL | SZA | SMA */
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if ((LAC >= 0400000) || (LAC == 0)) skp = 1;
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break;
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if ((LAC >= 0400000) || (LAC == 0)) skp = 1;
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break;
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case 010: /* SKP */
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skp = 1;
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break;
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skp = 1;
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break;
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case 011: /* SPA */
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if ((LAC & 0400000) == 0) skp = 1;
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break;
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if ((LAC & 0400000) == 0) skp = 1;
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break;
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case 012: /* SNA */
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if ((LAC & 0777777) != 0) skp = 1;
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break;
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if ((LAC & 0777777) != 0) skp = 1;
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break;
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case 013: /* SNA & SPA */
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if (((LAC & 0777777) != 0) && ((LAC & 0400000) == 0))
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skp = 1;
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break;
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if (((LAC & 0777777) != 0) && ((LAC & 0400000) == 0))
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skp = 1;
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break;
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case 014: /* SZL */
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if (LAC < 01000000) skp = 1;
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break;
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if (LAC < 01000000) skp = 1;
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break;
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case 015: /* SZL & SPA */
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if (LAC < 0400000) skp = 1;
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break;
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if (LAC < 0400000) skp = 1;
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break;
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case 016: /* SZL & SNA */
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if ((LAC < 01000000) && (LAC != 0)) skp = 1;
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break;
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if ((LAC < 01000000) && (LAC != 0)) skp = 1;
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break;
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case 017: /* SZL & SNA & SPA */
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if ((LAC < 0400000) && (LAC != 0)) skp = 1;
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break; } /* end switch skips */
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if ((LAC < 0400000) && (LAC != 0)) skp = 1;
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break; } /* end switch skips */
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/* OPR, continued */
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switch (((IR >> 9) & 014) | (IR & 03)) { /* IR<5:6,16:17> */
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case 0: /* NOP */
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break;
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break;
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case 1: /* CMA */
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LAC = LAC ^ 0777777;
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break;
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LAC = LAC ^ 0777777;
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break;
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case 2: /* CML */
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LAC = LAC ^ 01000000;
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break;
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LAC = LAC ^ 01000000;
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break;
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case 3: /* CML CMA */
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LAC = LAC ^ 01777777;
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break;
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LAC = LAC ^ 01777777;
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break;
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case 4: /* CLL */
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LAC = LAC & 0777777;
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break;
|
||||
LAC = LAC & 0777777;
|
||||
break;
|
||||
case 5: /* CLL CMA */
|
||||
LAC = (LAC & 0777777) ^ 0777777;
|
||||
break;
|
||||
LAC = (LAC & 0777777) ^ 0777777;
|
||||
break;
|
||||
case 6: /* CLL CML = STL */
|
||||
LAC = LAC | 01000000;
|
||||
break;
|
||||
LAC = LAC | 01000000;
|
||||
break;
|
||||
case 7: /* CLL CML CMA */
|
||||
LAC = (LAC | 01000000) ^ 0777777;
|
||||
break;
|
||||
LAC = (LAC | 01000000) ^ 0777777;
|
||||
break;
|
||||
case 010: /* CLA */
|
||||
LAC = LAC & 01000000;
|
||||
break;
|
||||
LAC = LAC & 01000000;
|
||||
break;
|
||||
case 011: /* CLA CMA = STA */
|
||||
LAC = LAC | 0777777;
|
||||
break;
|
||||
LAC = LAC | 0777777;
|
||||
break;
|
||||
case 012: /* CLA CML */
|
||||
LAC = (LAC & 01000000) ^ 01000000;
|
||||
break;
|
||||
LAC = (LAC & 01000000) ^ 01000000;
|
||||
break;
|
||||
case 013: /* CLA CML CMA */
|
||||
LAC = (LAC | 0777777) ^ 01000000;
|
||||
break;
|
||||
LAC = (LAC | 0777777) ^ 01000000;
|
||||
break;
|
||||
case 014: /* CLA CLL */
|
||||
LAC = 0;
|
||||
break;
|
||||
LAC = 0;
|
||||
break;
|
||||
case 015: /* CLA CLL CMA */
|
||||
LAC = 0777777;
|
||||
break;
|
||||
LAC = 0777777;
|
||||
break;
|
||||
case 016: /* CLA CLL CML */
|
||||
LAC = 01000000;
|
||||
break;
|
||||
LAC = 01000000;
|
||||
break;
|
||||
case 017: /* CLA CLL CML CMA */
|
||||
LAC = 01777777;
|
||||
break; } /* end decode */
|
||||
LAC = 01777777;
|
||||
break; } /* end decode */
|
||||
|
||||
/* OPR, continued */
|
||||
|
||||
if (IR & 0000004) { /* OAS */
|
||||
#if defined (PDP9) || defined (PDP15)
|
||||
if (usmd) prvn = trap_pending = 1;
|
||||
else
|
||||
if (usmd) prvn = trap_pending = 1;
|
||||
else
|
||||
#endif
|
||||
LAC = LAC | SR; }
|
||||
|
||||
switch (((IR >> 8) & 04) | ((IR >> 3) & 03)) { /* decode IR<7,13:14> */
|
||||
case 1: /* RAL */
|
||||
LAC = ((LAC << 1) | (LAC >> 18)) & 01777777;
|
||||
LAC = ((LAC << 1) | (LAC >> 18)) & 01777777;
|
||||
break;
|
||||
case 2: /* RAR */
|
||||
LAC = ((LAC >> 1) | (LAC << 18)) & 01777777;
|
||||
break;
|
||||
LAC = ((LAC >> 1) | (LAC << 18)) & 01777777;
|
||||
break;
|
||||
case 3: /* RAL RAR */
|
||||
#if defined (PDP15) /* PDP-15 */
|
||||
LAC = (LAC + 1) & 01777777; /* IAC */
|
||||
LAC = (LAC + 1) & 01777777; /* IAC */
|
||||
#else /* PDP-4,-7,-9 */
|
||||
reason = stop_inst; /* undefined */
|
||||
reason = stop_inst; /* undefined */
|
||||
#endif
|
||||
break;
|
||||
break;
|
||||
case 5: /* RTL */
|
||||
LAC = ((LAC << 2) | (LAC >> 17)) & 01777777;
|
||||
break;
|
||||
LAC = ((LAC << 2) | (LAC >> 17)) & 01777777;
|
||||
break;
|
||||
case 6: /* RTR */
|
||||
LAC = ((LAC >> 2) | (LAC << 17)) & 01777777;
|
||||
break;
|
||||
LAC = ((LAC >> 2) | (LAC << 17)) & 01777777;
|
||||
break;
|
||||
case 7: /* RTL RTR */
|
||||
#if defined (PDP15) /* PDP-15 */
|
||||
LAC = ((LAC >> 9) & 0777) | ((LAC & 0777) << 9) |
|
||||
(LAC & 01000000); /* BSW */
|
||||
LAC = ((LAC >> 9) & 0777) | ((LAC & 0777) << 9) |
|
||||
(LAC & 01000000); /* BSW */
|
||||
#else /* PDP-4,-7,-9 */
|
||||
reason = stop_inst; /* undefined */
|
||||
reason = stop_inst; /* undefined */
|
||||
#endif
|
||||
break; } /* end switch rotate */
|
||||
break; } /* end switch rotate */
|
||||
|
||||
if (IR & 0000040) { /* HLT */
|
||||
if (usmd) prvn = trap_pending = 1;
|
||||
else reason = STOP_HALT; }
|
||||
if (usmd) prvn = trap_pending = 1;
|
||||
else reason = STOP_HALT; }
|
||||
if (skp && !prvn) PC = INCR_ADDR (PC); /* if skip, inc PC */
|
||||
break; /* end OPR */
|
||||
|
||||
@@ -1065,10 +1066,10 @@ case 036: /* OPR, dir */
|
||||
case 033: case 032: /* EAE */
|
||||
if (cpu_unit.flags & UNIT_NOEAE) break; /* disabled? */
|
||||
if (IR & 0020000) /* IR<4>? AC0 to L */
|
||||
LAC = ((LAC << 1) & 01000000) | (LAC & 0777777);
|
||||
LAC = ((LAC << 1) & 01000000) | (LAC & 0777777);
|
||||
if (IR & 0010000) MQ = 0; /* IR<5>? clear MQ */
|
||||
if ((IR & 0004000) && (LAC & 0400000)) /* IR<6> and minus? */
|
||||
eae_ac_sign = 01000000; /* set eae_ac_sign */
|
||||
eae_ac_sign = 01000000; /* set eae_ac_sign */
|
||||
else eae_ac_sign = 0; /* if not, unsigned */
|
||||
if (IR & 0002000) MQ = (MQ | LAC) & 0777777; /* IR<7>? or AC */
|
||||
else if (eae_ac_sign) LAC = LAC ^ 0777777; /* if not, |AC| */
|
||||
@@ -1079,25 +1080,25 @@ case 033: case 032: /* EAE */
|
||||
|
||||
switch ((IR >> 6) & 07) { /* case on IR<9:11> */
|
||||
case 0: /* setup */
|
||||
if (IR & 04) LAC = LAC ^ 0777777; /* IR<15>? ~AC */
|
||||
if (IR & 02) LAC = LAC | MQ; /* IR<16>? or MQ */
|
||||
if (IR & 01) LAC = LAC | ((-SC) & 077); /* IR<17>? or SC */
|
||||
break;
|
||||
if (IR & 04) LAC = LAC ^ 0777777; /* IR<15>? ~AC */
|
||||
if (IR & 02) LAC = LAC | MQ; /* IR<16>? or MQ */
|
||||
if (IR & 01) LAC = LAC | ((-SC) & 077); /* IR<17>? or SC */
|
||||
break;
|
||||
|
||||
case 1: /* multiply */
|
||||
CHECK_ADDR_R (PC); /* validate PC */
|
||||
MA = M[PC]; /* get next word */
|
||||
PC = INCR_ADDR (PC); /* increment PC */
|
||||
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
|
||||
LAC = LAC & 0777777; /* clear link */
|
||||
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
|
||||
if (MQ & 1) LAC = LAC + MA; /* MQ<17>? add */
|
||||
MQ = (MQ >> 1) | ((LAC & 1) << 17);
|
||||
LAC = LAC >> 1; } /* shift AC'MQ right */
|
||||
if (eae_ac_sign ^ link_init) { /* result negative? */
|
||||
LAC = LAC ^ 0777777;
|
||||
MQ = MQ ^ 0777777; }
|
||||
break;
|
||||
CHECK_ADDR_R (PC); /* validate PC */
|
||||
MA = M[PC]; /* get next word */
|
||||
PC = INCR_ADDR (PC); /* increment PC */
|
||||
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
|
||||
LAC = LAC & 0777777; /* clear link */
|
||||
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
|
||||
if (MQ & 1) LAC = LAC + MA; /* MQ<17>? add */
|
||||
MQ = (MQ >> 1) | ((LAC & 1) << 17);
|
||||
LAC = LAC >> 1; } /* shift AC'MQ right */
|
||||
if (eae_ac_sign ^ link_init) { /* result negative? */
|
||||
LAC = LAC ^ 0777777;
|
||||
MQ = MQ ^ 0777777; }
|
||||
break;
|
||||
|
||||
/* EAE, continued
|
||||
|
||||
@@ -1111,26 +1112,26 @@ case 033: case 032: /* EAE */
|
||||
*/
|
||||
|
||||
case 3: /* divide */
|
||||
CHECK_ADDR_R (PC); /* validate PC */
|
||||
MA = M[PC]; /* get next word */
|
||||
PC = INCR_ADDR (PC); /* increment PC */
|
||||
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
|
||||
if ((LAC & 0777777) >= MA) { /* overflow? */
|
||||
LAC = (LAC - MA) | 01000000; /* set link */
|
||||
break; }
|
||||
LAC = LAC & 0777777; /* clear link */
|
||||
t = 0; /* init loop */
|
||||
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
|
||||
if (t) LAC = (LAC + MA) & 01777777;
|
||||
else LAC = (LAC - MA) & 01777777;
|
||||
t = (LAC >> 18) & 1; /* quotient bit */
|
||||
if (SC > 1) LAC = /* skip if last */
|
||||
((LAC << 1) | (MQ >> 17)) & 01777777;
|
||||
MQ = ((MQ << 1) | t) & 0777777; }
|
||||
CHECK_ADDR_R (PC); /* validate PC */
|
||||
MA = M[PC]; /* get next word */
|
||||
PC = INCR_ADDR (PC); /* increment PC */
|
||||
if (eae_ac_sign) MQ = MQ ^ 0777777; /* EAE AC sign? ~MQ */
|
||||
if ((LAC & 0777777) >= MA) { /* overflow? */
|
||||
LAC = (LAC - MA) | 01000000; /* set link */
|
||||
break; }
|
||||
LAC = LAC & 0777777; /* clear link */
|
||||
t = 0; /* init loop */
|
||||
for (SC = esc; SC != 0; SC--) { /* loop per step cnt */
|
||||
if (t) LAC = (LAC + MA) & 01777777;
|
||||
if (eae_ac_sign) LAC = LAC ^ 0777777; /* sgn rem = sgn divd */
|
||||
if (eae_ac_sign ^ link_init ^ 1) MQ = MQ ^ 0777777;
|
||||
break;
|
||||
else LAC = (LAC - MA) & 01777777;
|
||||
t = (LAC >> 18) & 1; /* quotient bit */
|
||||
if (SC > 1) LAC = /* skip if last */
|
||||
((LAC << 1) | (MQ >> 17)) & 01777777;
|
||||
MQ = ((MQ << 1) | t) & 0777777; }
|
||||
if (t) LAC = (LAC + MA) & 01777777;
|
||||
if (eae_ac_sign) LAC = LAC ^ 0777777; /* sgn rem = sgn divd */
|
||||
if (eae_ac_sign ^ link_init ^ 1) MQ = MQ ^ 0777777;
|
||||
break;
|
||||
|
||||
/* EAE, continued
|
||||
|
||||
@@ -1141,43 +1142,45 @@ case 033: case 032: /* EAE */
|
||||
|
||||
case 4: /* normalize */
|
||||
#if defined (PDP15)
|
||||
if (!usmd) ion_defer = 2; /* free cycles */
|
||||
if (!usmd) ion_defer = 2; /* free cycles */
|
||||
#endif
|
||||
for (SC = esc; (SC != 0) && ((LAC & 0400000) ==
|
||||
((LAC << 1) & 0400000)); SC--) {
|
||||
LAC = (LAC << 1) | ((MQ >> 17) & 1);
|
||||
MQ = (MQ << 1) | (link_init >> 18); }
|
||||
LAC = link_init | (LAC & 0777777); /* trim AC, restore L */
|
||||
MQ = MQ & 0777777; /* trim MQ */
|
||||
SC = SC & 077; /* trim SC */
|
||||
break;
|
||||
for (SC = esc; (SC != 0) && ((LAC & 0400000) ==
|
||||
((LAC << 1) & 0400000)); SC--) {
|
||||
LAC = (LAC << 1) | ((MQ >> 17) & 1);
|
||||
MQ = (MQ << 1) | (link_init >> 18); }
|
||||
LAC = link_init | (LAC & 0777777); /* trim AC, restore L */
|
||||
MQ = MQ & 0777777; /* trim MQ */
|
||||
SC = SC & 077; /* trim SC */
|
||||
break;
|
||||
case 5: /* long right shift */
|
||||
if (esc < 18) {
|
||||
MQ = ((LAC << (18 - esc)) | (MQ >> esc)) & 0777777;
|
||||
LAC = ((fill << (18 - esc)) | (LAC >> esc)) & 01777777; }
|
||||
else { if (esc < 36) MQ =
|
||||
((fill << (36 - esc)) | (LAC >> (esc - 18))) & 0777777;
|
||||
else MQ = fill;
|
||||
LAC = link_init | fill; }
|
||||
SC = 0; /* clear step count */
|
||||
break;
|
||||
if (esc < 18) {
|
||||
MQ = ((LAC << (18 - esc)) | (MQ >> esc)) & 0777777;
|
||||
LAC = ((fill << (18 - esc)) | (LAC >> esc)) & 01777777; }
|
||||
else {
|
||||
if (esc < 36) MQ =
|
||||
((fill << (36 - esc)) | (LAC >> (esc - 18))) & 0777777;
|
||||
else MQ = fill;
|
||||
LAC = link_init | fill; }
|
||||
SC = 0; /* clear step count */
|
||||
break;
|
||||
case 6: /* long left shift */
|
||||
if (esc < 18) {
|
||||
LAC = link_init |
|
||||
(((LAC << esc) | (MQ >> (18 - esc))) & 0777777);
|
||||
MQ = ((MQ << esc) | (fill >> (18 - esc))) & 0777777; }
|
||||
else { if (esc < 36) LAC = link_init |
|
||||
(((MQ << (esc - 18)) | (fill >> (36 - esc))) & 0777777);
|
||||
else LAC = link_init | fill;
|
||||
MQ = fill; }
|
||||
SC = 0; /* clear step count */
|
||||
break;
|
||||
case 7: /* AC left shift */
|
||||
if (esc < 18) LAC = link_init |
|
||||
(((LAC << esc) | (fill >> (18 - esc))) & 0777777);
|
||||
if (esc < 18) {
|
||||
LAC = link_init |
|
||||
(((LAC << esc) | (MQ >> (18 - esc))) & 0777777);
|
||||
MQ = ((MQ << esc) | (fill >> (18 - esc))) & 0777777; }
|
||||
else {
|
||||
if (esc < 36) LAC = link_init |
|
||||
(((MQ << (esc - 18)) | (fill >> (36 - esc))) & 0777777);
|
||||
else LAC = link_init | fill;
|
||||
SC = 0; /* clear step count */
|
||||
break; } /* end switch IR */
|
||||
MQ = fill; }
|
||||
SC = 0; /* clear step count */
|
||||
break;
|
||||
case 7: /* AC left shift */
|
||||
if (esc < 18) LAC = link_init |
|
||||
(((LAC << esc) | (fill >> (18 - esc))) & 0777777);
|
||||
else LAC = link_init | fill;
|
||||
SC = 0; /* clear step count */
|
||||
break; } /* end switch IR */
|
||||
break; /* end case EAE */
|
||||
|
||||
/* PDP-15 index operates: opcode 72 */
|
||||
@@ -1187,46 +1190,46 @@ case 035: /* index operates */
|
||||
t = (IR & 0400)? IR | 0777000: IR & 0377; /* sext immediate */
|
||||
switch ((IR >> 9) & 017) { /* case on IR<5:8> */
|
||||
case 000: /* AAS */
|
||||
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
|
||||
if (SEXT (LAC & 0777777) >= SEXT (LR))
|
||||
PC = INCR_ADDR (PC);
|
||||
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
|
||||
if (SEXT (LAC & 0777777) >= SEXT (LR))
|
||||
PC = INCR_ADDR (PC);
|
||||
case 001: /* PAX */
|
||||
XR = LAC & 0777777;
|
||||
break;
|
||||
XR = LAC & 0777777;
|
||||
break;
|
||||
case 002: /* PAL */
|
||||
LR = LAC & 0777777;
|
||||
break;
|
||||
LR = LAC & 0777777;
|
||||
break;
|
||||
case 003: /* AAC */
|
||||
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
|
||||
break;
|
||||
LAC = (LAC & 01000000) | ((LAC + t) & 0777777);
|
||||
break;
|
||||
case 004: /* PXA */
|
||||
LAC = (LAC & 01000000) | XR;
|
||||
break;
|
||||
LAC = (LAC & 01000000) | XR;
|
||||
break;
|
||||
case 005: /* AXS */
|
||||
XR = (XR + t) & 0777777;
|
||||
if (SEXT (XR) >= SEXT (LR)) PC = INCR_ADDR (PC);
|
||||
break;
|
||||
XR = (XR + t) & 0777777;
|
||||
if (SEXT (XR) >= SEXT (LR)) PC = INCR_ADDR (PC);
|
||||
break;
|
||||
case 006: /* PXL */
|
||||
LR = XR;
|
||||
break;
|
||||
LR = XR;
|
||||
break;
|
||||
case 010: /* PLA */
|
||||
LAC = (LAC & 01000000) | LR;
|
||||
break;
|
||||
LAC = (LAC & 01000000) | LR;
|
||||
break;
|
||||
case 011: /* PLX */
|
||||
XR = LR;
|
||||
break;
|
||||
XR = LR;
|
||||
break;
|
||||
case 014: /* CLAC */
|
||||
LAC = LAC & 01000000;
|
||||
break;
|
||||
LAC = LAC & 01000000;
|
||||
break;
|
||||
case 015: /* CLX */
|
||||
XR = 0;
|
||||
break;
|
||||
XR = 0;
|
||||
break;
|
||||
case 016: /* CLLR */
|
||||
LR = 0;
|
||||
break;
|
||||
LR = 0;
|
||||
break;
|
||||
case 017: /* AXR */
|
||||
XR = (XR + t) & 0777777;
|
||||
break; } /* end switch IR */
|
||||
XR = (XR + t) & 0777777;
|
||||
break; } /* end switch IR */
|
||||
break; /* end case */
|
||||
#endif
|
||||
|
||||
@@ -1267,12 +1270,12 @@ case 035: /* index operates */
|
||||
case 034: /* IOT */
|
||||
#if defined (PDP15)
|
||||
if (IR & 0010000) { /* floating point? */
|
||||
/* PC = fp15 (PC, IR); /* process */
|
||||
break; }
|
||||
/* PC = fp15 (PC, IR); /* process */
|
||||
break; }
|
||||
#endif
|
||||
if (usmd) { /* user mode? */
|
||||
prvn = trap_pending = 1; /* trap */
|
||||
break; }
|
||||
prvn = trap_pending = 1; /* trap */
|
||||
break; }
|
||||
device = (IR >> 6) & 077; /* device = IR<6:11> */
|
||||
pulse = IR & 067; /* pulse = IR<12:17> */
|
||||
if (IR & 0000010) LAC = LAC & 01000000; /* clear AC? */
|
||||
@@ -1283,10 +1286,10 @@ case 034: /* IOT */
|
||||
#if defined (PDP4)
|
||||
switch (device) { /* decode IR<6:11> */
|
||||
case 0: /* CPU and clock */
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = ion_defer = 1; /* ION */
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = ion_defer = 1; /* ION */
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
#endif
|
||||
|
||||
/* PDP-7 system IOT's */
|
||||
@@ -1294,23 +1297,23 @@ case 034: /* IOT */
|
||||
#if defined (PDP7)
|
||||
switch (device) { /* decode IR<6:11> */
|
||||
case 0: /* CPU and clock */
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = ion_defer = 1; /* ION */
|
||||
else if (pulse == 062) /* ITON */
|
||||
usmd = ion = ion_defer = 1;
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = ion_defer = 1; /* ION */
|
||||
else if (pulse == 062) /* ITON */
|
||||
usmd = ion = ion_defer = 1;
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
case 033: /* CPU control */
|
||||
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) reset_all (0); /* CAF */
|
||||
break;
|
||||
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) reset_all (0); /* CAF */
|
||||
break;
|
||||
case 077: /* extended memory */
|
||||
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) memm = 1; /* EEM */
|
||||
else if (pulse == 042) /* EMIR */
|
||||
memm = emir_pending = 1; /* ext on, restore */
|
||||
else if (pulse == 004) memm = 0; /* LEM */
|
||||
break;
|
||||
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) memm = 1; /* EEM */
|
||||
else if (pulse == 042) /* EMIR */
|
||||
memm = emir_pending = 1; /* ext on, restore */
|
||||
else if (pulse == 004) memm = 0; /* LEM */
|
||||
break;
|
||||
#endif
|
||||
|
||||
/* PDP-9 and PDP-15 system IOT's */
|
||||
@@ -1319,73 +1322,73 @@ case 034: /* IOT */
|
||||
ion_defer = 1; /* delay interrupts */
|
||||
switch (device) { /* decode IR<6:11> */
|
||||
case 000: /* CPU and clock */
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = 1; /* ION */
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
if (pulse == 002) ion = 0; /* IOF */
|
||||
else if (pulse == 042) ion = 1; /* ION */
|
||||
else iot_data = clk (pulse, iot_data);
|
||||
break;
|
||||
case 017: /* mem protection */
|
||||
if ((pulse == 001) && prvn) PC = INCR_ADDR (PC);
|
||||
else if ((pulse == 041) && nexm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) prvn = 0;
|
||||
else if (pulse == 042) usmdbuf = 1;
|
||||
else if (pulse == 004) BR = LAC & BRMASK;
|
||||
else if (pulse == 044) nexm = 0;
|
||||
break;
|
||||
if ((pulse == 001) && prvn) PC = INCR_ADDR (PC);
|
||||
else if ((pulse == 041) && nexm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) prvn = 0;
|
||||
else if (pulse == 042) usmdbuf = 1;
|
||||
else if (pulse == 004) BR = LAC & BRMASK;
|
||||
else if (pulse == 044) nexm = 0;
|
||||
break;
|
||||
case 032: /* power fail */
|
||||
if ((pulse == 001) && (TST_INT (PWRFL)))
|
||||
PC = INCR_ADDR (PC);
|
||||
break;
|
||||
if ((pulse == 001) && (TST_INT (PWRFL)))
|
||||
PC = INCR_ADDR (PC);
|
||||
break;
|
||||
case 033: /* CPU control */
|
||||
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) reset_all (0); /* CAF */
|
||||
else if (pulse == 044) rest_pending = 1; /* DBR */
|
||||
if (((cpu_unit.flags & UNIT_NOAPI) == 0) && (pulse & 004)) {
|
||||
int32 t = api_ffo[api_act & 0377];
|
||||
api_act = api_act & ~(0200 >> t); }
|
||||
break;
|
||||
if ((pulse == 001) || (pulse == 041)) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) reset_all (0); /* CAF */
|
||||
else if (pulse == 044) rest_pending = 1; /* DBR */
|
||||
if (((cpu_unit.flags & UNIT_NOAPI) == 0) && (pulse & 004)) {
|
||||
int32 t = api_ffo[api_act & 0377];
|
||||
api_act = api_act & ~(0200 >> t); }
|
||||
break;
|
||||
case 055: /* API control */
|
||||
if (cpu_unit.flags & UNIT_NOAPI) reason = stop_inst;
|
||||
else if (pulse == 001) { /* SPI */
|
||||
if (((LAC & SIGN) && api_enb) ||
|
||||
((LAC & 0377) > api_act))
|
||||
iot_data = iot_data | IOT_SKP; }
|
||||
else if (pulse == 002) { /* RPL */
|
||||
iot_data = iot_data | (api_enb << 17) |
|
||||
(api_req << 8) | api_act; }
|
||||
else if (pulse == 004) { /* ISA */
|
||||
api_enb = (iot_data & SIGN)? 1: 0;
|
||||
api_req = api_req | ((LAC >> 8) & 017);
|
||||
api_act = api_act | (LAC & 0377); }
|
||||
break;
|
||||
if (cpu_unit.flags & UNIT_NOAPI) reason = stop_inst;
|
||||
else if (pulse == 001) { /* SPI */
|
||||
if (((LAC & SIGN) && api_enb) ||
|
||||
((LAC & 0377) > api_act))
|
||||
iot_data = iot_data | IOT_SKP; }
|
||||
else if (pulse == 002) { /* RPL */
|
||||
iot_data = iot_data | (api_enb << 17) |
|
||||
(api_req << 8) | api_act; }
|
||||
else if (pulse == 004) { /* ISA */
|
||||
api_enb = (iot_data & SIGN)? 1: 0;
|
||||
api_req = api_req | ((LAC >> 8) & 017);
|
||||
api_act = api_act | (LAC & 0377); }
|
||||
break;
|
||||
#endif
|
||||
#if defined (PDP9)
|
||||
case 077: /* extended memory */
|
||||
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) memm = 1; /* EEM */
|
||||
else if (pulse == 042) /* EMIR */
|
||||
memm = emir_pending = 1; /* ext on, restore */
|
||||
else if (pulse == 004) memm = 0; /* LEM */
|
||||
break;
|
||||
if ((pulse == 001) && memm) PC = INCR_ADDR (PC);
|
||||
else if (pulse == 002) memm = 1; /* EEM */
|
||||
else if (pulse == 042) /* EMIR */
|
||||
memm = emir_pending = 1; /* ext on, restore */
|
||||
else if (pulse == 004) memm = 0; /* LEM */
|
||||
break;
|
||||
#endif
|
||||
#if defined (PDP15)
|
||||
case 077: /* bank addressing */
|
||||
if ((pulse == 041) || ((pulse == 061) && memm))
|
||||
PC = INCR_ADDR (PC); /* SKP15, SBA */
|
||||
else if (pulse == 042) rest_pending = 1; /* RES */
|
||||
else if (pulse == 062) memm = 0; /* DBA */
|
||||
else if (pulse == 064) memm = 1; /* EBA */
|
||||
damask = memm? 017777: 07777; /* set dir addr mask */
|
||||
epcmask = ADDRMASK & ~damask; /* extended PC mask */
|
||||
break;
|
||||
if ((pulse == 041) || ((pulse == 061) && memm))
|
||||
PC = INCR_ADDR (PC); /* SKP15, SBA */
|
||||
else if (pulse == 042) rest_pending = 1; /* RES */
|
||||
else if (pulse == 062) memm = 0; /* DBA */
|
||||
else if (pulse == 064) memm = 1; /* EBA */
|
||||
damask = memm? 017777: 07777; /* set dir addr mask */
|
||||
epcmask = ADDRMASK & ~damask; /* extended PC mask */
|
||||
break;
|
||||
#endif
|
||||
|
||||
/* IOT, continued */
|
||||
|
||||
default: /* devices */
|
||||
if (dev_tab[device]) /* defined? */
|
||||
iot_data = dev_tab[device] (pulse, iot_data);
|
||||
else reason = stop_inst; /* stop on flag */
|
||||
break; } /* end switch device */
|
||||
if (dev_tab[device]) /* defined? */
|
||||
iot_data = dev_tab[device] (pulse, iot_data);
|
||||
else reason = stop_inst; /* stop on flag */
|
||||
break; } /* end switch device */
|
||||
LAC = LAC | (iot_data & 0777777);
|
||||
if (iot_data & IOT_SKP) PC = INCR_ADDR (PC);
|
||||
if (iot_data >= IOT_REASON) reason = iot_data >> IOT_V_REASON;
|
||||
@@ -1420,7 +1423,7 @@ if (api_enb == 0) return 0; /* off? no req */
|
||||
api_req = api_req & ~0360; /* clr req<0:3> */
|
||||
for (i = 0; i < API_HLVL; i++) { /* loop thru levels */
|
||||
if (int_hwre[i]) /* req on level? */
|
||||
api_req = api_req | (0200 >> i); } /* set api req */
|
||||
api_req = api_req | (0200 >> i); } /* set api req */
|
||||
hi = api_ffo[api_req & 0377]; /* find hi req */
|
||||
if (hi < api_ffo[api_act & 0377]) return (hi + 1);
|
||||
return 0;
|
||||
|
||||
Reference in New Issue
Block a user