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Notes For V2.10-2

Browse Source 
1. New Features in 2.10-2

The build procedures have changed.  There is only one UNIX makefile.
To compile without Ethernet support, simply type

	gmake {target|all}

To compile with Ethernet support, type

	gmake USE_NETWORK=1 {target|all}

The Mingw batch files require Mingw release 2 and invoke the Unix
makefile.  There are still separate batch files for compilation
with or without Ethernet support.

1.1 SCP and Libraries

- The EVAL command will evaluate a symbolic type-in and display
  it in numeric form.
- The ! command (with no arguments) will launch the host operating
  system command shell.  The ! command (with an argument) executes
  the argument as a host operating system command.  (Code from
  Mark Pizzolato)
- Telnet sessions now recognize BREAK.  How a BREAK is transmitted
  dependent on the particular Telnet client.  (Code from Mark
  Pizzolato)
- The sockets library includes code for active connections as
  well as listening connections.
- The RESTORE command will restore saved memory size, if the
  simulator supports dynamic memory resizing.

1.2 PDP-1

- The PDP-1 supports the Type 24 serial drum (based on recently
  discovered documents).

1.3 18b PDP's

- The PDP-4 supports the Type 24 serial drum (based on recently
  discovered documents).

1.4 PDP-11

- The PDP-11 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.5 PDP-10

- The PDP-10 implements a stub DEUNA/DELUA (XU).  The real XU
  module will be included in a later release.

1.6 HP 2100

- The IOP microinstruction set is supported for the 21MX as well
  as the 2100.
- The HP2100 supports the Access Interprocessor Link (IPL).

1.7 VAX

- If the VAX console is attached to a Telnet session, BREAK is
  interpreted as console halt.
- The SET/SHOW HISTORY commands enable and display a history of
  the most recently executed instructions.  (Code from Mark
  Pizzolato)

1.8 Terminals Multiplexors

- BREAK detection was added to the HP, DEC, and Interdata terminal
  multiplexors.

1.9 Interdata 16b and 32b

- First release.  UNIX is not yet working.

1.10 SDS 940

- First release.

2. Bugs Fixed in 2.10-2

- PDP-11 console must default to 7b for early UNIX compatibility.
- PDP-11/VAX TMSCP emulator was using the wrong packet length for
  read/write end packets.
- Telnet IAC+IAC processing was fixed, both for input and output
  (found by Mark Pizzolato).
- PDP-11/VAX Ethernet setting flag bits wrong for chained
  descriptors (found by Mark Pizzolato).

3. New Features in 2.10 vs prior releases

3.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

3.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

3.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

3.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

3.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

3.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

3.7 IBM 1620

- The IBM 1620 simulator has been released.

3.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

3.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

3.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

3.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

4. Bugs Fixed in 2.10 vs prior releases

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.
- PDP-10 tape wouldn't boot, and then wouldn't read (reported by
  Michael Thompson and Harris Newman, respectively)
- PDP-1 typewriter is half duplex, with only one shift state for
  both input and output (found by Derek Peschel)

5. General Notes

WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.
This commit is contained in:
Bob Supnik
2003-01-17 18:35:00 -08:00
committed by Mark Pizzolato
parent 4ea745b3ad
commit 2bcd1e7c4c
206 changed files with 30253 additions and 12114 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
PDP8/pdp8_clk.c
View File

@@ -94,9 +94,9 @@ case 2: /* CLDI */
return AC;
case 3: /* CLSC */
if (dev_done & INT_CLK) { /* flag set? */
dev_done = dev_done & ~INT_CLK; /* clear flag */
int_req = int_req & ~INT_CLK; /* clear int req */
return IOT_SKP + AC; }
dev_done = dev_done & ~INT_CLK; /* clear flag */
int_req = int_req & ~INT_CLK; /* clear int req */
return IOT_SKP + AC; }
return AC;
case 5: /* CLLE */
if (AC & 1) int_enable = int_enable | INT_CLK; /* test AC<11> */

669
PDP8/pdp8_cpu.c
View File

@@ -524,142 +524,143 @@ case 027: /* JMP, indir, curr */
case 034:case 035: /* OPR, group 1 */
switch ((IR >> 4) & 017) { /* decode IR<4:7> */
case 0: /* nop */
break;
break;
case 1: /* CML */
LAC = LAC ^ 010000;
break;
LAC = LAC ^ 010000;
break;
case 2: /* CMA */
LAC = LAC ^ 07777;
break;
LAC = LAC ^ 07777;
break;
case 3: /* CMA CML */
LAC = LAC ^ 017777;
break;
LAC = LAC ^ 017777;
break;
case 4: /* CLL */
LAC = LAC & 07777;
break;
LAC = LAC & 07777;
break;
case 5: /* CLL CML = STL */
LAC = LAC | 010000;
break;
LAC = LAC | 010000;
break;
case 6: /* CLL CMA */
LAC = (LAC ^ 07777) & 07777;
break;
LAC = (LAC ^ 07777) & 07777;
break;
case 7: /* CLL CMA CML */
LAC = (LAC ^ 07777) | 010000;
break;
LAC = (LAC ^ 07777) | 010000;
break;
case 010: /* CLA */
LAC = LAC & 010000;
break;
LAC = LAC & 010000;
break;
case 011: /* CLA CML */
LAC = (LAC & 010000) ^ 010000;
break;
LAC = (LAC & 010000) ^ 010000;
break;
case 012: /* CLA CMA = STA */
LAC = LAC | 07777;
break;
LAC = LAC | 07777;
break;
case 013: /* CLA CMA CML */
LAC = (LAC | 07777) ^ 010000;
break;
LAC = (LAC | 07777) ^ 010000;
break;
case 014: /* CLA CLL */
LAC = 0;
break;
LAC = 0;
break;
case 015: /* CLA CLL CML */
LAC = 010000;
break;
LAC = 010000;
break;
case 016: /* CLA CLL CMA */
LAC = 07777;
break;
LAC = 07777;
break;
case 017: /* CLA CLL CMA CML */
LAC = 017777;
break; } /* end switch opers */
LAC = 017777;
break; } /* end switch opers */
/* OPR group 1, continued */
if (IR & 01) LAC = (LAC + 1) & 017777; /* IAC */
switch ((IR >> 1) & 07) { /* decode IR<8:10> */
case 0: /* nop */
break;
break;
case 1: /* BSW */
LAC = (LAC & 010000) | ((LAC >> 6) & 077) | ((LAC & 077) << 6);
break;
LAC = (LAC & 010000) | ((LAC >> 6) & 077) | ((LAC & 077) << 6);
break;
case 2: /* RAL */
LAC = ((LAC << 1) | (LAC >> 12)) & 017777;
break;
LAC = ((LAC << 1) | (LAC >> 12)) & 017777;
break;
case 3: /* RTL */
LAC = ((LAC << 2) | (LAC >> 11)) & 017777;
break;
LAC = ((LAC << 2) | (LAC >> 11)) & 017777;
break;
case 4: /* RAR */
LAC = ((LAC >> 1) | (LAC << 12)) & 017777;
break;
LAC = ((LAC >> 1) | (LAC << 12)) & 017777;
break;
case 5: /* RTR */
LAC = ((LAC >> 2) | (LAC << 11)) & 017777;
break;
LAC = ((LAC >> 2) | (LAC << 11)) & 017777;
break;
case 6: /* RAL RAR - undef */
LAC = LAC & (IR | 010000); /* uses AND path */
break;
LAC = LAC & (IR | 010000); /* uses AND path */
break;
case 7: /* RTL RTR - undef */
LAC = (LAC & 010000) | (MA & 07600) | (IR & 0177);
break; } /* uses address path */
LAC = (LAC & 010000) | (MA & 07600) | (IR & 0177);
break; } /* uses address path */
break; /* end group 1 */
/* OPR group 2 */
case 036:case 037: /* OPR, groups 2, 3 */
if ((IR & 01) == 0) { /* group 2 */
switch ((IR >> 3) & 017) { /* decode IR<6:8> */
case 0: /* nop */
break;
case 1: /* SKP */
switch ((IR >> 3) & 017) { /* decode IR<6:8> */
case 0: /* nop */
break;
case 1: /* SKP */
PC = (PC + 1) & 07777;
break;
case 2: /* SNL */
if (LAC >= 010000) PC = (PC + 1) & 07777;
break;
case 3: /* SZL */
if (LAC < 010000) PC = (PC + 1) & 07777;
break;
case 4: /* SZA */
if ((LAC & 07777) == 0) PC = (PC + 1) & 07777;
break;
case 5: /* SNA */
if ((LAC & 07777) != 0) PC = (PC + 1) & 07777;
break;
case 6: /* SZA | SNL */
if ((LAC == 0) || (LAC >= 010000))
PC = (PC + 1) & 07777;
break;
case 7: /* SNA & SZL */
if ((LAC != 0) && (LAC < 010000)) PC = (PC + 1) & 07777;
break;
case 010: /* SMA */
if ((LAC & 04000) != 0) PC = (PC + 1) & 07777;
break;
case 011: /* SPA */
if ((LAC & 04000) == 0) PC = (PC + 1) & 07777;
break;
case 012: /* SMA | SNL */
if (LAC >= 04000) PC = (PC + 1) & 07777;
break;
case 013: /* SPA & SZL */
if (LAC < 04000) PC = (PC + 1) & 07777;
break;
case 014: /* SMA | SZA */
if (((LAC & 04000) != 0) || ((LAC & 07777) == 0))
PC = (PC + 1) & 07777;
break;
case 015: /* SPA & SNA */
if (((LAC & 04000) == 0) && ((LAC & 07777) != 0))
PC = (PC + 1) & 07777;
break;
case 2: /* SNL */
if (LAC >= 010000) PC = (PC + 1) & 07777;
break;
case 3: /* SZL */
if (LAC < 010000) PC = (PC + 1) & 07777;
break;
case 4: /* SZA */
if ((LAC & 07777) == 0) PC = (PC + 1) & 07777;
break;
case 5: /* SNA */
if ((LAC & 07777) != 0) PC = (PC + 1) & 07777;
break;
case 6: /* SZA | SNL */
if ((LAC == 0) || (LAC >= 010000))
PC = (PC + 1) & 07777;
break;
case 7: /* SNA & SZL */
if ((LAC != 0) && (LAC < 010000)) PC = (PC + 1) & 07777;
break;
case 010: /* SMA */
if ((LAC & 04000) != 0) PC = (PC + 1) & 07777;
break;
case 011: /* SPA */
if ((LAC & 04000) == 0) PC = (PC + 1) & 07777;
break;
case 012: /* SMA | SNL */
if (LAC >= 04000) PC = (PC + 1) & 07777;
break;
case 013: /* SPA & SZL */
if (LAC < 04000) PC = (PC + 1) & 07777;
break;
case 014: /* SMA | SZA */
if (((LAC & 04000) != 0) || ((LAC & 07777) == 0))
PC = (PC + 1) & 07777;
break;
case 015: /* SPA & SNA */
if (((LAC & 04000) == 0) && ((LAC & 07777) != 0))
PC = (PC + 1) & 07777;
break;
case 016: /* SMA | SZA | SNL */
if ((LAC >= 04000) || (LAC == 0)) PC = (PC + 1) & 07777;
break;
case 017: /* SPA & SNA & SZL */
if ((LAC < 04000) && (LAC != 0)) PC = (PC + 1) & 07777;
break; } /* end switch skips */
if (IR & 0200) LAC = LAC & 010000; /* CLA */
if ((IR & 06) && UF) int_req = int_req | INT_UF;
else { if (IR & 04) LAC = LAC | OSR; /* OSR */
if (IR & 02) reason = STOP_HALT; } /* HLT */
break; } /* end group 2 */
break;
case 016: /* SMA | SZA | SNL */
if ((LAC >= 04000) || (LAC == 0)) PC = (PC + 1) & 07777;
break;
case 017: /* SPA & SNA & SZL */
if ((LAC < 04000) && (LAC != 0)) PC = (PC + 1) & 07777;
break; } /* end switch skips */
if (IR & 0200) LAC = LAC & 010000; /* CLA */
if ((IR & 06) && UF) int_req = int_req | INT_UF;
else {
if (IR & 04) LAC = LAC | OSR; /* OSR */
if (IR & 02) reason = STOP_HALT; } /* HLT */
break; } /* end group 2 */
/* OPR group 3 standard
@@ -673,12 +674,12 @@ case 036:case 037: /* OPR, groups 2, 3 */
temp = MQ; /* group 3 */
if (IR & 0200) LAC = LAC & 010000; /* CLA */
if (IR & 0020) { /* MQL */
MQ = LAC & 07777;
LAC = LAC & 010000; }
MQ = LAC & 07777;
LAC = LAC & 010000; }
if (IR & 0100) LAC = LAC | temp; /* MQA */
if ((IR & 0056) && (cpu_unit.flags & UNIT_NOEAE)) {
reason = stop_inst; /* EAE not present */
break; }
reason = stop_inst; /* EAE not present */
break; }
/* OPR group 3 EAE
@@ -697,11 +698,11 @@ case 036:case 037: /* OPR, groups 2, 3 */
*/
if (IR == 07431) { /* SWAB */
emode = 1; /* set mode flag */
break; }
emode = 1; /* set mode flag */
break; }
if (IR == 07447) { /* SWBA */
emode = gtf = 0; /* clear mode, gtf */
break; }
emode = gtf = 0; /* clear mode, gtf */
break; }
/* If not switching modes, the EAE operation is determined by the mode
and IR<6,8:10>:
@@ -736,271 +737,273 @@ case 036:case 037: /* OPR, groups 2, 3 */
if (emode == 0) gtf = 0; /* mode A? clr gtf */
switch ((IR >> 1) & 027) { /* decode IR<6,8:10> */
case 020: /* mode A, B: SCA */
LAC = LAC | SC;
break;
LAC = LAC | SC;
break;
case 0: /* mode A, B: NOP */
break;
break;
case 021: /* mode B: DAD */
if (emode) {
MA = IF | PC;
INDIRECT; /* defer state */
MQ = MQ + M[MA];
MA = DF | ((MA + 1) & 07777);
LAC = (LAC & 07777) + M[MA] + (MQ >> 12);
MQ = MQ & 07777;
PC = (PC + 1) & 07777;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 1: /* mode B: ACS */
if (emode) {
SC = LAC & 037;
LAC = LAC & 010000;
break; }
SC = (~M[IF | PC]) & 037; /* mode A: SCL */
PC = (PC + 1) & 07777;
break;
case 022: /* mode B: DST */
if (emode) {
MA = IF | PC;
INDIRECT; /* defer state */
if (MEM_ADDR_OK (MA)) M[MA] = MQ & 07777;
MA = DF | ((MA + 1) & 07777);
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
PC = (PC + 1) & 07777;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 2: /* MUY */
if (emode) {
MA = IF | PC;
if (emode) { INDIRECT; } /* mode B: defer */
temp = (MQ * M[MA]) + (LAC & 07777);
LAC = (temp >> 12) & 07777;
MQ = temp & 07777;
INDIRECT; /* defer state */
MQ = MQ + M[MA];
MA = DF | ((MA + 1) & 07777);
LAC = (LAC & 07777) + M[MA] + (MQ >> 12);
MQ = MQ & 07777;
PC = (PC + 1) & 07777;
SC = 014; /* 12 shifts */
break;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 1: /* mode B: ACS */
if (emode) {
SC = LAC & 037;
LAC = LAC & 010000;
break; }
SC = (~M[IF | PC]) & 037; /* mode A: SCL */
PC = (PC + 1) & 07777;
break;
case 022: /* mode B: DST */
if (emode) {
MA = IF | PC;
INDIRECT; /* defer state */
if (MEM_ADDR_OK (MA)) M[MA] = MQ & 07777;
MA = DF | ((MA + 1) & 07777);
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
PC = (PC + 1) & 07777;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 2: /* MUY */
MA = IF | PC;
if (emode) { INDIRECT; } /* mode B: defer */
temp = (MQ * M[MA]) + (LAC & 07777);
LAC = (temp >> 12) & 07777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = 014; /* 12 shifts */
break;
/* EAE continued */
case 023: /* mode B: SWBA */
if (emode) break;
LAC = LAC | SC; /* mode A: SCA then */
if (emode) break;
LAC = LAC | SC; /* mode A: SCA then */
case 3: /* DVI */
MA = IF | PC;
if (emode) { INDIRECT; } /* mode B: defer */
if ((LAC & 07777) >= M[MA]) { /* overflow? */
LAC = LAC | 010000; /* set link */
MQ = ((MQ << 1) + 1) & 07777; /* rotate MQ */
SC = 01; } /* 1 shift */
else { temp = ((LAC & 07777) << 12) | MQ;
MQ = temp / M[MA];
LAC = temp % M[MA];
SC = 015; } /* 13 shifts */
PC = (PC + 1) & 07777;
break;
MA = IF | PC;
if (emode) { INDIRECT; } /* mode B: defer */
if ((LAC & 07777) >= M[MA]) { /* overflow? */
LAC = LAC | 010000; /* set link */
MQ = ((MQ << 1) + 1) & 07777; /* rotate MQ */
SC = 01; } /* 1 shift */
else {
temp = ((LAC & 07777) << 12) | MQ;
MQ = temp / M[MA];
LAC = temp % M[MA];
SC = 015; } /* 13 shifts */
PC = (PC + 1) & 07777;
break;
case 024: /* mode B: DPSZ */
if (emode) {
if (((LAC | MQ) & 07777) == 0) PC = (PC + 1) & 07777;
break; }
LAC = LAC | SC; /* mode A: SCA then */
if (emode) {
if (((LAC | MQ) & 07777) == 0) PC = (PC + 1) & 07777;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 4: /* NMI */
temp = (LAC << 12) | MQ; /* preserve link */
for (SC = 0; ((temp & 017777777) != 0) &&
(temp & 040000000) == ((temp << 1) & 040000000); SC++)
temp = temp << 1;
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
if (emode && ((LAC & 07777) == 04000) && (MQ == 0))
LAC = LAC & 010000; /* clr if 4000'0000 */
break;
temp = (LAC << 12) | MQ; /* preserve link */
for (SC = 0; ((temp & 017777777) != 0) &&
(temp & 040000000) == ((temp << 1) & 040000000); SC++)
temp = temp << 1;
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
if (emode && ((LAC & 07777) == 04000) && (MQ == 0))
LAC = LAC & 010000; /* clr if 4000'0000 */
break;
case 025: /* mode B: DPIC */
if (emode) {
temp = (LAC + 1) & 07777; /* SWP already done! */
LAC = MQ + (temp == 0);
MQ = temp;
break; }
LAC = LAC | SC; /* mode A: SCA then */
if (emode) {
temp = (LAC + 1) & 07777; /* SWP already done! */
LAC = MQ + (temp == 0);
MQ = temp;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 5: /* SHL */
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
if (SC > 25) temp = 0; /* >25? result = 0 */
else temp = ((LAC << 12) | MQ) << SC; /* <=25? shift LAC:MQ */
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break;
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
if (SC > 25) temp = 0; /* >25? result = 0 */
else temp = ((LAC << 12) | MQ) << SC; /* <=25? shift LAC:MQ */
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break;
/* EAE continued */
case 026: /* mode B: DCM */
if (emode) {
temp = (-LAC) & 07777; /* SWP already done! */
LAC = (MQ ^ 07777) + (temp == 0);
MQ = temp;
break; }
LAC = LAC | SC; /* mode A: SCA then */
if (emode) {
temp = (-LAC) & 07777; /* SWP already done! */
LAC = (MQ ^ 07777) + (temp == 0);
MQ = temp;
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 6: /* ASR */
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
temp = ((LAC & 07777) << 12) | MQ; /* sext from AC0 */
if (LAC & 04000) temp = temp | ~037777777;
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
if (SC > 25) temp = (LAC & 04000)? -1: 0;
else temp = temp >> SC;
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break;
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
temp = ((LAC & 07777) << 12) | MQ; /* sext from AC0 */
if (LAC & 04000) temp = temp | ~037777777;
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
if (SC > 25) temp = (LAC & 04000)? -1: 0;
else temp = temp >> SC;
LAC = (temp >> 12) & 017777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break;
case 027: /* mode B: SAM */
if (emode) {
temp = LAC & 07777;
LAC = MQ + (temp ^ 07777) + 1; /* L'AC = MQ - AC */
gtf = (temp <= MQ) ^ ((temp ^ MQ) >> 11);
break; }
LAC = LAC | SC; /* mode A: SCA then */
if (emode) {
temp = LAC & 07777;
LAC = MQ + (temp ^ 07777) + 1; /* L'AC = MQ - AC */
gtf = (temp <= MQ) ^ ((temp ^ MQ) >> 11);
break; }
LAC = LAC | SC; /* mode A: SCA then */
case 7: /* LSR */
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
temp = ((LAC & 07777) << 12) | MQ; /* clear link */
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
if (SC > 24) temp = 0; /* >24? result = 0 */
else temp = temp >> SC; /* <=24? shift AC:MQ */
LAC = (temp >> 12) & 07777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break; } /* end switch */
SC = (M[IF | PC] & 037) + (emode ^ 1); /* shift+1 if mode A */
temp = ((LAC & 07777) << 12) | MQ; /* clear link */
if (emode && (SC != 0)) gtf = (temp >> (SC - 1)) & 1;
if (SC > 24) temp = 0; /* >24? result = 0 */
else temp = temp >> SC; /* <=24? shift AC:MQ */
LAC = (temp >> 12) & 07777;
MQ = temp & 07777;
PC = (PC + 1) & 07777;
SC = emode? 037: 0; /* SC = 0 if mode A */
break; } /* end switch */
break; /* end case 7 */
/* Opcode 6, IOT */
case 030:case 031:case 032:case 033: /* IOT */
if (UF) { /* privileged? */
int_req = int_req | INT_UF;
break; }
int_req = int_req | INT_UF;
break; }
device = (IR >> 3) & 077; /* device = IR<3:8> */
pulse = IR & 07; /* pulse = IR<9:11> */
iot_data = LAC & 07777; /* AC unchanged */
switch (device) { /* decode IR<3:8> */
case 0: /* CPU control */
switch (pulse) { /* decode IR<9:11> */
case 0: /* SKON */
if (int_req & INT_ION) PC = (PC + 1) & 07777;
int_req = int_req & ~INT_ION;
break;
case 1: /* ION */
int_req = (int_req | INT_ION) & ~INT_NO_ION_PENDING;
break;
case 2: /* IOF */
int_req = int_req & ~INT_ION;
break;
case 3: /* SRQ */
if (int_req & INT_ALL) PC = (PC + 1) & 07777;
break;
case 4: /* GTF */
LAC = (LAC & 010000) |
((LAC & 010000) >> 1) | (gtf << 10) |
(((int_req & INT_ALL) != 0) << 9) |
(((int_req & INT_ION) != 0) << 7) | SF;
break;
case 5: /* RTF */
gtf = ((LAC & 02000) >> 10);
UB = (LAC & 0100) >> 6;
IB = (LAC & 0070) << 9;
DF = (LAC & 0007) << 12;
LAC = ((LAC & 04000) << 1) | iot_data;
int_req = (int_req | INT_ION) & ~INT_NO_CIF_PENDING;
break;
case 6: /* SGT */
if (gtf) PC = (PC + 1) & 07777;
break;
case 7: /* CAF */
gtf = 0;
emode = 0;
int_req = int_req & INT_NO_CIF_PENDING;
dev_done = 0;
int_enable = INT_INIT_ENABLE;
LAC = 0;
break; } /* end switch pulse */
break; /* end case 0 */
switch (pulse) { /* decode IR<9:11> */
case 0: /* SKON */
if (int_req & INT_ION) PC = (PC + 1) & 07777;
int_req = int_req & ~INT_ION;
break;
case 1: /* ION */
int_req = (int_req | INT_ION) & ~INT_NO_ION_PENDING;
break;
case 2: /* IOF */
int_req = int_req & ~INT_ION;
break;
case 3: /* SRQ */
if (int_req & INT_ALL) PC = (PC + 1) & 07777;
break;
case 4: /* GTF */
LAC = (LAC & 010000) |
((LAC & 010000) >> 1) | (gtf << 10) |
(((int_req & INT_ALL) != 0) << 9) |
(((int_req & INT_ION) != 0) << 7) | SF;
break;
case 5: /* RTF */
gtf = ((LAC & 02000) >> 10);
UB = (LAC & 0100) >> 6;
IB = (LAC & 0070) << 9;
DF = (LAC & 0007) << 12;
LAC = ((LAC & 04000) << 1) | iot_data;
int_req = (int_req | INT_ION) & ~INT_NO_CIF_PENDING;
break;
case 6: /* SGT */
if (gtf) PC = (PC + 1) & 07777;
break;
case 7: /* CAF */
gtf = 0;
emode = 0;
int_req = int_req & INT_NO_CIF_PENDING;
dev_done = 0;
int_enable = INT_INIT_ENABLE;
LAC = 0;
break; } /* end switch pulse */
break; /* end case 0 */
/* IOT, continued: memory extension */
case 020:case 021:case 022:case 023:
case 024:case 025:case 026:case 027: /* memory extension */
switch (pulse) { /* decode IR<9:11> */
case 1: /* CDF */
DF = (IR & 0070) << 9;
break;
case 2: /* CIF */
IB = (IR & 0070) << 9;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 3: /* CDF CIF */
DF = IB = (IR & 0070) << 9;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 4:
switch (device & 07) { /* decode IR<6:8> */
case 0: /* CINT */
int_req = int_req & ~INT_UF;
break;
case 1: /* RDF */
LAC = LAC | (DF >> 9);
break;
case 2: /* RIF */
LAC = LAC | (IF >> 9);
break;
case 3: /* RIB */
LAC = LAC | SF;
break;
case 4: /* RMF */
UB = (SF & 0100) >> 6;
IB = (SF & 0070) << 9;
DF = (SF & 0007) << 12;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 5: /* SINT */
if (int_req & INT_UF) PC = (PC + 1) & 07777;
break;
case 6: /* CUF */
UB = 0;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 7: /* SUF */
UB = 1;
int_req = int_req & ~INT_NO_CIF_PENDING;
break; } /* end switch device */
break;
default:
reason = stop_inst;
break; } /* end switch pulse */
break; /* end case 20-27 */
switch (pulse) { /* decode IR<9:11> */
case 1: /* CDF */
DF = (IR & 0070) << 9;
break;
case 2: /* CIF */
IB = (IR & 0070) << 9;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 3: /* CDF CIF */
DF = IB = (IR & 0070) << 9;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 4:
switch (device & 07) { /* decode IR<6:8> */
case 0: /* CINT */
int_req = int_req & ~INT_UF;
break;
case 1: /* RDF */
LAC = LAC | (DF >> 9);
break;
case 2: /* RIF */
LAC = LAC | (IF >> 9);
break;
case 3: /* RIB */
LAC = LAC | SF;
break;
case 4: /* RMF */
UB = (SF & 0100) >> 6;
IB = (SF & 0070) << 9;
DF = (SF & 0007) << 12;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 5: /* SINT */
if (int_req & INT_UF) PC = (PC + 1) & 07777;
break;
case 6: /* CUF */
UB = 0;
int_req = int_req & ~INT_NO_CIF_PENDING;
break;
case 7: /* SUF */
UB = 1;
int_req = int_req & ~INT_NO_CIF_PENDING;
break; } /* end switch device */
break;
default:
reason = stop_inst;
break; } /* end switch pulse */
break; /* end case 20-27 */
/* IOT, continued: other special cases */
case 010: /* power fail */
switch (pulse) { /* decode IR<9:11> */
case 1: /* SBE */
break;
case 2: /* SPL */
if (int_req & INT_PWR) PC = (PC + 1) & 07777;
break;
case 3: /* CAL */
int_req = int_req & ~INT_PWR;
break;
default:
reason = stop_inst;
break; } /* end switch pulse */
break; /* end case 10 */
switch (pulse) { /* decode IR<9:11> */
case 1: /* SBE */
break;
case 2: /* SPL */
if (int_req & INT_PWR) PC = (PC + 1) & 07777;
break;
case 3: /* CAL */
int_req = int_req & ~INT_PWR;
break;
default:
reason = stop_inst;
break; } /* end switch pulse */
break; /* end case 10 */
default: /* I/O device */
if (dev_tab[device]) { /* dev present? */
iot_data = dev_tab[device] (IR, iot_data);
LAC = (LAC & 010000) | (iot_data & 07777);
if (iot_data & IOT_SKP) PC = (PC + 1) & 07777;
if (iot_data >= IOT_REASON)
reason = iot_data >> IOT_V_REASON; }
else reason = stop_inst; /* stop on flag */
break; } /* end switch device */
break; } /* end switch opcode */
if (dev_tab[device]) { /* dev present? */
iot_data = dev_tab[device] (IR, iot_data);
LAC = (LAC & 010000) | (iot_data & 07777);
if (iot_data & IOT_SKP) PC = (PC + 1) & 07777;
if (iot_data >= IOT_REASON)
reason = iot_data >> IOT_V_REASON; }
else reason = stop_inst; /* stop on flag */
break; } /* end switch device */
break; /* end case IOT */
} /* end switch opcode */
} /* end while */
/* Simulation halted */

21
PDP8/pdp8_df.c
View File

@@ -223,14 +223,15 @@ da = GET_DEX (df_sta) | df_da; /* form disk addr */
do { M[DF_WC] = (M[DF_WC] + 1) & 07777; /* incr word count */
M[DF_MA] = (M[DF_MA] + 1) & 07777; /* incr mem addr */
pa = mex | M[DF_MA]; /* add extension */
if (uptr->FUNC == DF_READ) {
if (MEM_ADDR_OK (pa)) /* read, check nxm */
M[pa] = *(((int16 *) uptr->filebuf) + da); }
else { t = (da >> 14) & 07;
if ((df_wlk >> t) & 1) df_sta = df_sta | DFS_WLS;
else { *(((int16 *) uptr->filebuf) + da) = M[pa];
if (da >= uptr->hwmark)
uptr->hwmark = da + 1; } }
if (uptr->FUNC == DF_READ) { /* read? */
if (MEM_ADDR_OK (pa)) /* check nxm */
M[pa] = *(((int16 *) uptr->filebuf) + da); }
else { /* write */
t = (da >> 14) & 07; /* check wr lock */
if ((df_wlk >> t) & 1) df_sta = df_sta | DFS_WLS;
else { /* not locked */
*(((int16 *) uptr->filebuf) + da) = M[pa];
if (da >= uptr->hwmark) uptr->hwmark = da + 1; } }
da = (da + 1) & 0377777; } /* incr disk addr */
while ((M[DF_WC] != 0) && (df_burst != 0)); /* brk if wc, no brst */
@@ -287,10 +288,10 @@ extern int32 sim_switches, saved_PC;
if (sim_switches & SWMASK ('D')) {
for (i = 0; i < DM4_LEN; i = i + 2)
M[dm4_rom[i]] = dm4_rom[i + 1];
M[dm4_rom[i]] = dm4_rom[i + 1];
saved_PC = DM4_START; }
else { for (i = 0; i < OS8_LEN; i++)
M[OS8_START + i] = os8_rom[i];
M[OS8_START + i] = os8_rom[i];
saved_PC = OS8_START; }
return SCPE_OK;
}

287
PDP8/pdp8_dt.c
View File

@@ -361,10 +361,10 @@ if (pulse & 01) AC = AC | dtsa; /* DTRA */
if (pulse & 06) { /* select */
if (pulse & 02) dtsa = 0; /* DTCA */
if (pulse & 04) { /* DTXA */
if ((AC & DTA_CERF) == 0) dtsb = dtsb & ~DTB_ALLERR;
if ((AC & DTA_CDTF) == 0) dtsb = dtsb & ~DTB_DTF;
dtsa = dtsa ^ (AC & DTA_RW);
AC = 0; } /* clr AC */
if ((AC & DTA_CERF) == 0) dtsb = dtsb & ~DTB_ALLERR;
if ((AC & DTA_CDTF) == 0) dtsb = dtsb & ~DTB_DTF;
dtsa = dtsa ^ (AC & DTA_RW);
AC = 0; } /* clr AC */
if ((old_dtsa ^ dtsa) & DTA_UNIT) dt_deselect (old_dtsa);
uptr = dt_dev.units + DTA_GETUNIT (dtsa); /* get unit */
fnc = DTA_GETFNC (dtsa); /* get fnc */
@@ -372,7 +372,7 @@ if (pulse & 06) { /* select */
(fnc >= FNC_WMRK) || /* write mark? */
((fnc == FNC_WALL) && (uptr->flags & UNIT_WPRT)) ||
((fnc == FNC_WRIT) && (uptr->flags & UNIT_WPRT)))
dt_seterr (uptr, DTB_SEL); /* select err */
dt_seterr (uptr, DTB_SEL); /* select err */
else dt_newsa (dtsa);
DT_UPDINT; }
return AC;
@@ -456,17 +456,17 @@ if (new_mving & ~prev_mving) { /* start? */
if (prev_mving & ~new_mving) { /* stop? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
return; }
if (prev_dir ^ new_dir) { /* dir chg? */
if ((prev_mot & ~DTS_DIR) != DTS_DECF) { /* !already stopping? */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
if (dt_setpos (uptr)) return; /* update pos */
sim_cancel (uptr); /* stop current */
sim_activate (uptr, dt_dctime); } /* schedule decel */
DTS_SETSTA (DTS_DECF | prev_dir, 0); /* state = decel */
DTS_SET2ND (DTS_ACCF | new_dir, 0); /* next = accel */
DTS_SET3RD (DTS_ATSF | new_dir, new_fnc); /* next next = fnc */
@@ -528,33 +528,33 @@ case DTS_OFR: /* off reel */
case FNC_MOVE: /* move */
dt_schedez (uptr, dir); /* sched end zone */
if (dt_log & LOG_MS) printf ("[DT%d: moving %s]\n", unum, (dir?
"backward": "forward"));
"backward": "forward"));
return; /* done */
case FNC_SRCH: /* search */
if (dir) newpos = DT_BLK2LN ((DT_QFEZ (uptr)?
DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
DTU_TSIZE (uptr): blk), uptr) - DT_BLKLN - DT_WSIZE;
else newpos = DT_BLK2LN ((DT_QREZ (uptr)?
0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
0: blk + 1), uptr) + DT_BLKLN + (DT_WSIZE - 1);
if (dt_log & LOG_MS) printf ("[DT%d: searching %s]\n", unum,
(dir? "backward": "forward"));
(dir? "backward": "forward"));
break;
case FNC_WRIT: /* write */
case FNC_READ: /* read */
case FNC_RALL: /* read all */
case FNC_WALL: /* write all */
if (DT_QEZ (uptr)) { /* in "ok" end zone? */
if (dir) newpos = DTU_FWDEZ (uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_EZLIN + DT_HTLIN + (DT_WSIZE - 1);
break; }
if (dir) newpos = DTU_FWDEZ (uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_EZLIN + DT_HTLIN + (DT_WSIZE - 1);
break; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dt_seterr (uptr, DTB_SEL);
return; }
dt_seterr (uptr, DTB_SEL);
return; }
if (dir) newpos = DT_BLK2LN (((relpos >= (DTU_LPERB (uptr) - DT_HTLIN))?
blk + 1: blk), uptr) - DT_HTLIN - DT_WSIZE;
blk + 1: blk), uptr) - DT_HTLIN - DT_WSIZE;
else newpos = DT_BLK2LN (((relpos < DT_HTLIN)?
blk: blk + 1), uptr) + DT_HTLIN + (DT_WSIZE - 1);
blk: blk + 1), uptr) + DT_HTLIN + (DT_WSIZE - 1);
break;
default:
dt_seterr (uptr, DTB_SEL); /* bad state */
@@ -614,7 +614,7 @@ if (((int32) uptr->pos < 0) ||
uptr->STATE = uptr->pos = 0;
unum = uptr - dt_dev.units;
if (unum == DTA_GETUNIT (dtsa)) /* if selected, */
dt_seterr (uptr, DTB_SEL); /* error */
dt_seterr (uptr, DTB_SEL); /* error */
return TRUE; }
return FALSE;
}
@@ -646,7 +646,7 @@ case DTS_DECF: case DTS_DECR: /* decelerating */
if (dt_setpos (uptr)) return SCPE_OK; /* update pos */
uptr->STATE = DTS_NXTSTA (uptr->STATE); /* advance state */
if (uptr->STATE) /* not stopped? */
sim_activate (uptr, dt_actime); /* must be reversing */
sim_activate (uptr, dt_actime); /* must be reversing */
return SCPE_OK;
case DTS_ACCF: case DTS_ACCR: /* accelerating */
dt_newfnc (uptr, DTS_NXTSTA (uptr->STATE)); /* adv state, sched */
@@ -675,14 +675,14 @@ case FNC_MOVE: /* move */
return SCPE_OK;
case FNC_SRCH: /* search */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
sim_activate (uptr, DTU_LPERB (uptr) * dt_ltime);/* sched next block */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr word cnt */
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
if (MEM_ADDR_OK (ma)) M[ma] = blk & 07777; /* store block # */
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
case DTS_OFR: /* off reel */
detach_unit (uptr); /* must be deselected */
@@ -706,36 +706,37 @@ case FNC_READ: /* read */
wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
switch (dt_substate) { /* case on substate */
case DTO_SOB: /* start of block */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: reading block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: reading block %d %s%s\n",
unum, blk, (dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
case 0: /* normal read */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dat = bptr[ba]; /* get tape word */
if (dir) dat = dt_comobv (dat); /* rev? comp obv */
if (MEM_ADDR_OK (ma)) M[ma] = dat; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO; /* wc ovf? */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dat = bptr[ba]; /* get tape word */
if (dir) dat = dt_comobv (dat); /* rev? comp obv */
if (MEM_ADDR_OK (ma)) M[ma] = dat; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO; /* wc ovf? */
case DTO_WCO: /* wc ovf, not sob */
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else { dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
break;
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else {
dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
break;
case DTO_WCO | DTO_SOB: /* next block */
if (wrd == (dir? 0: DTU_BSIZE (uptr))) /* end of block? */
dt_seterr (uptr, DTB_TIM); /* timing error */
else sim_activate (uptr, DT_WSIZE * dt_ltime);
break; }
if (wrd == (dir? 0: DTU_BSIZE (uptr))) /* end of block? */
dt_seterr (uptr, DTB_TIM); /* timing error */
else sim_activate (uptr, DT_WSIZE * dt_ltime);
break; }
break;
/* Write has four subcases
@@ -754,31 +755,32 @@ case FNC_WRIT: /* write */
wrd = DT_LIN2WD (uptr->pos, uptr); /* get word # */
switch (dt_substate) { /* case on substate */
case DTO_SOB: /* start block */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: writing block %d %s%s\n", unum, blk,
(dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
if ((dt_log & LOG_RW) || ((dt_log & LOG_BL) && (blk == dt_logblk)))
printf ("[DT%d: writing block %d %s%s\n", unum, blk,
(dir? "backward": "forward"),
((dtsa & DTA_MODE)? " continuous]": "]"));
dt_substate = 0; /* fall through */
case 0: /* normal write */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
case DTO_WCO: /* wc ovflo */
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dat = dt_substate? 0: M[ma]; /* get word */
if (dir) dat = dt_comobv (dat); /* rev? comp obv */
bptr[ba] = dat; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else { dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
ba = (blk * DTU_BSIZE (uptr)) + wrd; /* buffer ptr */
dat = dt_substate? 0: M[ma]; /* get word */
if (dir) dat = dt_comobv (dat); /* rev? comp obv */
bptr[ba] = dat; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1;
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (wrd != (dir? 0: DTU_BSIZE (uptr) - 1)) /* not last? */
sim_activate (uptr, DT_WSIZE * dt_ltime);
else {
dt_substate = dt_substate | DTO_SOB;
sim_activate (uptr, ((2 * DT_HTLIN) + DT_WSIZE) * dt_ltime);
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; } /* set DTF */
break;
case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
@@ -794,29 +796,29 @@ case FNC_WRIT: /* write */
case FNC_RALL:
switch (dt_substate) { /* case on substate */
case 0: case DTO_SOB: /* read in progress */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dat = bptr[ba]; /* get tape word */
if (dir) dat = dt_comobv (dat); } /* rev? comp obv */
else dat = dt_gethdr (uptr, blk, relpos, dir); /* get hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (MEM_ADDR_OK (ma)) M[ma] = dat; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
dat = bptr[ba]; /* get tape word */
if (dir) dat = dt_comobv (dat); } /* rev? comp obv */
else dat = dt_gethdr (uptr, blk, relpos, dir); /* get hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (MEM_ADDR_OK (ma)) M[ma] = dat; /* mem addr legal? */
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
case DTO_WCO: case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
break;
/* Write all has two subcases
@@ -828,30 +830,30 @@ case FNC_RALL:
case FNC_WALL:
switch (dt_substate) { /* case on substate */
case 0: case DTO_SOB: /* read in progress */
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dat = M[ma]; /* get mem word */
if (dir) dat = dt_comobv (dat);
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
bptr[ba] = dat; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1; }
if (dtsb & DTB_DTF) { /* DTF set? */
dt_seterr (uptr, DTB_TIM); /* timing error */
return SCPE_OK; }
relpos = DT_LIN2OF (uptr->pos, uptr); /* cur pos in blk */
M[DT_WC] = (M[DT_WC] + 1) & 07777; /* incr WC, CA */
M[DT_CA] = (M[DT_CA] + 1) & 07777;
ma = DTB_GETMEX (dtsb) | M[DT_CA]; /* get mem addr */
if ((relpos >= DT_HTLIN) && /* in data zone? */
(relpos < (DTU_LPERB (uptr) - DT_HTLIN))) {
dat = M[ma]; /* get mem word */
if (dir) dat = dt_comobv (dat);
wrd = DT_LIN2WD (uptr->pos, uptr);
ba = (blk * DTU_BSIZE (uptr)) + wrd;
bptr[ba] = dat; /* write word */
if (ba >= uptr->hwmark) uptr->hwmark = ba + 1; }
/* /* ignore hdr */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
sim_activate (uptr, DT_WSIZE * dt_ltime);
if (M[DT_WC] == 0) dt_substate = DTO_WCO;
if (((dtsa & DTA_MODE) == 0) || (M[DT_WC] == 0))
dtsb = dtsb | DTB_DTF; /* set DTF */
break;
case DTO_WCO: case DTO_WCO | DTO_SOB: /* all done */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
dt_schedez (uptr, dir); /* sched end zone */
break; } /* end case substate */
break;
default:
dt_seterr (uptr, DTB_SEL); /* impossible state */
@@ -891,31 +893,31 @@ if (relpos >= DT_HTLIN) relpos = relpos - (DT_WSIZE * DTU_BSIZE (uptr));
if (dir) { /* reverse */
switch (relpos / DT_WSIZE) {
case 6: /* fwd csum */
return (dt_comobv (dt_csum (uptr, blk)));
return (dt_comobv (dt_csum (uptr, blk)));
case 2: /* lo fwd blk */
return dt_comobv ((blk & 077) << 6);
return dt_comobv ((blk & 077) << 6);
case 1: /* hi fwd blk */
return dt_comobv (blk >> 6);
return dt_comobv (blk >> 6);
case 12: /* hi rev blk */
return (blk >> 6) & 07777;
return (blk >> 6) & 07777;
case 11: /* lo rev blk */
return ((blk & 077) << 6);
return ((blk & 077) << 6);
default: /* others */
return 077; } }
return 077; } }
else { /* forward */
switch (relpos / DT_WSIZE) {
case 8: /* rev csum */
return (dt_csum (uptr, blk) << 6);
return (dt_csum (uptr, blk) << 6);
case 12: /* lo rev blk */
return dt_comobv ((blk & 077) << 6);
return dt_comobv ((blk & 077) << 6);
case 13: /* hi rev blk */
return dt_comobv (blk >> 6);
return dt_comobv (blk >> 6);
case 2: /* hi fwd blk */
return ((blk >> 6) & 07777);
return ((blk >> 6) & 07777);
case 3: /* lo fwd blk */
return ((blk & 077) << 6);
return ((blk & 077) << 6);
default: /* others */
break; } }
break; } }
return 0;
}
@@ -985,16 +987,17 @@ UNIT *uptr;
for (i = 0; i < DT_NUMDR; i++) { /* stop all activity */
uptr = dt_dev.units + i;
if (sim_is_running) { /* CAF? */
prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
if (dt_setpos (uptr)) continue; /* update pos */
sim_cancel (uptr);
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
} }
else { sim_cancel (uptr); /* sim reset */
uptr->STATE = 0;
uptr->LASTT = sim_grtime (); } }
prev_mot = DTS_GETMOT (uptr->STATE); /* get motion */
if ((prev_mot & ~DTS_DIR) > DTS_DECF) { /* accel or spd? */
if (dt_setpos (uptr)) continue; /* update pos */
sim_cancel (uptr);
sim_activate (uptr, dt_dctime); /* sched decel */
DTS_SETSTA (DTS_DECF | (prev_mot & DTS_DIR), 0);
} }
else {
sim_cancel (uptr); /* sim reset */
uptr->STATE = 0;
uptr->LASTT = sim_grtime (); } }
dtsa = dtsb = 0; /* clear status */
DT_UPDINT; /* reset interrupt */
return SCPE_OK;

4
PDP8/pdp8_lp.c
View File

@@ -99,8 +99,8 @@ case 4: /* PSTB */
lpt_unit.buf = AC & 0177; /* load buffer */
if ((lpt_unit.buf == 015) || (lpt_unit.buf == 014) ||
(lpt_unit.buf == 012)) {
sim_activate (&lpt_unit, lpt_unit.wait);
return AC; }
sim_activate (&lpt_unit, lpt_unit.wait);
return AC; }
return (lpt_svc (&lpt_unit) << IOT_V_REASON) + AC;
case 5: /* PSIE */
int_enable = int_enable | INT_LPT; /* set enable */

111
PDP8/pdp8_mt.c
View File

@@ -243,24 +243,24 @@ case 6: /* LFGR */
if (mt_busy ()) mt_sta = mt_sta | STA_ILL; /* busy? illegal op */
mt_fn = AC; /* load function */
if ((mt_fn & FN_GO) == 0) { /* go set? */
mt_updcsta (uptr); /* update status */
return 0; }
mt_updcsta (uptr); /* update status */
return 0; }
f = GET_FNC (mt_fn); /* get function */
if (((uptr->flags & UNIT_ATT) == 0) || !TUR (uptr) ||
(((f == FN_WRITE) || (f == FN_WREOF)) && (uptr->flags & UNIT_WPRT))
|| (((f == FN_SPACER) || (f == FN_REWIND)) && (uptr->USTAT & STA_BOT))) {
mt_sta = mt_sta | STA_ILL; /* illegal op error */
mt_set_done (); /* set done */
mt_updcsta (uptr); /* update status */
return 0; }
mt_sta = mt_sta | STA_ILL; /* illegal op error */
mt_set_done (); /* set done */
mt_updcsta (uptr); /* update status */
return 0; }
uptr->USTAT = uptr->USTAT & STA_WLK; /* clear status */
if (f == FN_UNLOAD) { /* unload? */
detach_unit (uptr); /* set offline */
uptr->USTAT = STA_REW | STA_REM; /* rewinding, off */
mt_set_done (); } /* set done */
detach_unit (uptr); /* set offline */
uptr->USTAT = STA_REW | STA_REM; /* rewinding, off */
mt_set_done (); } /* set done */
else if (f == FN_REWIND) { /* rewind */
uptr->USTAT = uptr->USTAT | STA_REW; /* rewinding */
mt_set_done (); } /* set done */
uptr->USTAT = uptr->USTAT | STA_REW; /* rewinding */
mt_set_done (); } /* set done */
else mt_done = 0; /* clear done */
mt_updcsta (uptr); /* update status */
sim_activate (uptr, mt_time); /* start io */
@@ -317,9 +317,10 @@ case 4: /* SKTR */
return (TUR (uptr))? IOT_SKP + AC: AC;
case 5: /* CLF */
if (TUR (uptr)) mt_reset (&mt_dev); /* if TUR, zap */
else { mt_sta = 0; /* clear status */
mt_done = 0; /* clear done */
mt_updcsta (uptr); } /* update status */
else { /* just ctrl zap */
mt_sta = 0; /* clear status */
mt_done = 0; /* clear done */
mt_updcsta (uptr); } /* update status */
return AC; } /* end switch */
return (stop_inst << IOT_V_REASON) + AC; /* ill inst */
}
@@ -347,11 +348,11 @@ MT_CLR_PNU (uptr); /* and clear */
if (uptr->USTAT & STA_REW) { /* rewind? */
uptr->pos = 0; /* update position */
if (uptr->flags & UNIT_ATT) /* still on line? */
uptr->USTAT = (uptr->USTAT & STA_WLK) | STA_BOT;
uptr->USTAT = (uptr->USTAT & STA_WLK) | STA_BOT;
else uptr->USTAT = STA_REM;
if (u == GET_UNIT (mt_cu)) { /* selected? */
mt_set_done (); /* set done */
mt_updcsta (uptr); } /* update status */
mt_set_done (); /* set done */
mt_updcsta (uptr); } /* update status */
return SCPE_OK; }
if ((uptr->flags & UNIT_ATT) == 0) { /* if not attached */
@@ -376,33 +377,34 @@ switch (f) { /* case on function */
case FN_READ: /* read */
case FN_CMPARE: /* read/compare */
if (mt_rdlntf (uptr, &tbc, &err)) { /* read rec lnt */
mt_sta = mt_sta | STA_RLE; /* err, eof/eom, tmk */
break; }
mt_sta = mt_sta | STA_RLE; /* err, eof/eom, tmk */
break; }
if (tbc > MT_MAXFR) return SCPE_MTRLNT; /* record too long? */
cbc = (mt_cu & CU_UNPAK)? wc: wc * 2; /* expected bc */
if (tbc != cbc) mt_sta = mt_sta | STA_RLE; /* wrong size? */
if (tbc < cbc) { /* record small? */
cbc = tbc; /* use smaller */
wc = (mt_cu & CU_UNPAK)? cbc: (cbc + 1) / 2; }
cbc = tbc; /* use smaller */
wc = (mt_cu & CU_UNPAK)? cbc: (cbc + 1) / 2; }
abc = fxread (dbuf, sizeof (uint8), cbc, uptr->fileref);
if (err = ferror (uptr->fileref)) { /* error? */
mt_sta = mt_sta | STA_RLE; /* set flag */
MT_SET_PNU (uptr); /* pos not upd */
break; }
mt_sta = mt_sta | STA_RLE; /* set flag */
MT_SET_PNU (uptr); /* pos not upd */
break; }
for ( ; abc < cbc; abc++) dbuf[abc] = 0; /* fill with 0's */
for (i = p = 0; i < wc; i++) { /* copy buffer */
xma = mt_ixma (xma); /* increment xma */
if (mt_cu & CU_UNPAK) c = dbuf[p++];
else { c1 = dbuf[p++] & 077;
c2 = dbuf[p++] & 077;
c = (c1 << 6) | c2; }
if ((f == FN_READ) && MEM_ADDR_OK (xma)) M[xma] = c;
else if ((f == FN_CMPARE) && (M[xma] != c)) {
mt_sta = mt_sta | STA_CPE;
break; } }
xma = mt_ixma (xma); /* increment xma */
if (mt_cu & CU_UNPAK) c = dbuf[p++];
else {
c1 = dbuf[p++] & 077;
c2 = dbuf[p++] & 077;
c = (c1 << 6) | c2; }
if ((f == FN_READ) && MEM_ADDR_OK (xma)) M[xma] = c;
else if ((f == FN_CMPARE) && (M[xma] != c)) {
mt_sta = mt_sta | STA_CPE;
break; } }
mt_wc = (mt_wc + wc) & 07777; /* update wc */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + /* update tape pos */
(2 * sizeof (t_mtrlnt));
(2 * sizeof (t_mtrlnt));
break;
case FN_WRITE: /* write */
@@ -410,15 +412,17 @@ case FN_WRITE: /* write */
tbc = (mt_cu & CU_UNPAK)? wc: wc * 2;
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
for (i = p = 0; i < wc; i++) { /* copy buf to tape */
xma = mt_ixma (xma); /* incr mem addr */
if (mt_cu & CU_UNPAK) dbuf[p++] = M[xma] & 0377;
else { dbuf[p++] = (M[xma] >> 6) & 077;
dbuf[p++] = M[xma] & 077; } }
xma = mt_ixma (xma); /* incr mem addr */
if (mt_cu & CU_UNPAK) dbuf[p++] = M[xma] & 0377;
else {
dbuf[p++] = (M[xma] >> 6) & 077;
dbuf[p++] = M[xma] & 077; } }
fxwrite (dbuf, sizeof (int8), (tbc + 1) & ~1, uptr->fileref);
fxwrite (&tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr); /* error? */
else { mt_wc = 0;
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + /* upd tape pos */
else {
mt_wc = 0;
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + /* upd tape pos */
(2 * sizeof (t_mtrlnt)); }
break;
@@ -432,19 +436,22 @@ case FN_WREOF:
break;
case FN_SPACEF: /* space forward */
do { mt_wc = (mt_wc + 1) & 07777; /* incr wc */
if (mt_rdlntf (uptr, &tbc, &err)) break;/* read rec lnt, err? */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt)); }
do {
mt_wc = (mt_wc + 1) & 07777; /* incr wc */
if (mt_rdlntf (uptr, &tbc, &err)) break; /* read rec lnt, err? */
uptr->pos = uptr->pos + ((tbc + 1) & ~1) +
(2 * sizeof (t_mtrlnt)); }
while (mt_wc != 0);
break;
case FN_SPACER: /* space reverse */
do { mt_wc = (mt_wc + 1) & 07777; /* incr wc */
if (pnu) pnu = 0; /* pos not upd? */
else { if (mt_rdlntr (uptr, &tbc, &err)) break;
uptr->pos = uptr->pos - ((tbc + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); } }
do {
mt_wc = (mt_wc + 1) & 07777; /* incr wc */
if (pnu) pnu = 0; /* pos not upd? */
else {
if (mt_rdlntr (uptr, &tbc, &err)) break;
uptr->pos = uptr->pos - ((tbc + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); } }
while (mt_wc != 0);
break; } /* end case */
@@ -482,7 +489,7 @@ UNIT *uptr;
for (u = 0; u < MT_NUMDR; u++) { /* loop thru units */
uptr = mt_dev.units + u;
if (sim_is_active (uptr) && ((uptr->USTAT & STA_REW) == 0))
return uptr; }
return uptr; }
return NULL;
}
@@ -568,8 +575,8 @@ for (u = 0; u < MT_NUMDR; u++) { /* loop thru units */
sim_cancel (uptr); /* cancel activity */
MT_CLR_PNU (uptr); /* clear pos flag */
if (uptr->flags & UNIT_ATT) uptr->USTAT =
((uptr->pos)? 0: STA_BOT) |
((uptr->flags & UNIT_WPRT)? STA_WLK: 0);
((uptr->pos)? 0: STA_BOT) |
((uptr->flags & UNIT_WPRT)? STA_WLK: 0);
else uptr->USTAT = STA_REM; }
return SCPE_OK;
}

4
PDP8/pdp8_pt.c
View File

@@ -148,8 +148,8 @@ if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */
return IORETURN (ptr_stopioe, SCPE_UNATT);
if ((temp = getc (ptr_unit.fileref)) == EOF) {
if (feof (ptr_unit.fileref)) {
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
else perror ("PTR I/O error");
clearerr (ptr_unit.fileref);
return SCPE_IOERR; }

25
PDP8/pdp8_rf.c
View File

@@ -191,8 +191,8 @@ case 2: /* DSAC */
case 5: /* DIML */
rf_sta = (rf_sta & 07007) | (AC & 0770); /* STA<3:8> <- AC */
if (rf_sta & RFS_PIE) /* photocell int? */
sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
rf_time);
sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
rf_time);
else sim_cancel (&pcell_unit);
RF_INT_UPDATE; /* update int req */
return 0; /* clear AC */
@@ -256,14 +256,15 @@ mex = GET_MEX (rf_sta);
do { M[RF_WC] = (M[RF_WC] + 1) & 07777; /* incr word count */
M[RF_MA] = (M[RF_MA] + 1) & 07777; /* incr mem addr */
pa = mex | M[RF_MA]; /* add extension */
if (uptr->FUNC == RF_READ) {
if (MEM_ADDR_OK (pa)) /* read, check nxm */
M[pa] = *(((int16 *) uptr->filebuf) + rf_da); }
else { t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
if ((rf_wlk >> t) & 1) rf_sta = rf_sta | RFS_WLS;
else { *(((int16 *) uptr->filebuf) + rf_da) = M[pa];
if (((t_addr) rf_da) >= uptr->hwmark)
uptr->hwmark = rf_da + 1; } }
if (uptr->FUNC == RF_READ) { /* read? */
if (MEM_ADDR_OK (pa)) /* check nxm */
M[pa] = *(((int16 *) uptr->filebuf) + rf_da); }
else { /* write */
t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
if ((rf_wlk >> t) & 1) rf_sta = rf_sta | RFS_WLS;
else {
*(((int16 *) uptr->filebuf) + rf_da) = M[pa];
if (((t_addr) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1; } }
rf_da = (rf_da + 1) & 03777777; } /* incr disk addr */
while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
@@ -330,10 +331,10 @@ extern int32 sim_switches, saved_PC;
if (rf_dib.dev != DEV_RF) return STOP_NOTSTD; /* only std devno */
if (sim_switches & SWMASK ('D')) {
for (i = 0; i < DM4_LEN; i = i + 2)
M[dm4_rom[i]] = dm4_rom[i + 1];
M[dm4_rom[i]] = dm4_rom[i + 1];
saved_PC = DM4_START; }
else { for (i = 0; i < OS8_LEN; i++)
M[OS8_START + i] = os8_rom[i];
M[OS8_START + i] = os8_rom[i];
saved_PC = OS8_START; }
return SCPE_OK;
}

50
PDP8/pdp8_rk.c
View File

@@ -205,23 +205,24 @@ case 2: /* DCLR */
rk_sta = 0; /* clear status */
switch (AC & 03) { /* decode AC<10:11> */
case RKX_CLS: /* clear status */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
case RKX_CLSA: /* clear status alt */
break;
break;
case RKX_CLC: /* clear control */
rk_cmd = rk_busy = 0; /* clear registers */
rk_ma = rk_da = 0;
for (i = 0; i < RK_NUMDR; i++) sim_cancel (&rk_unit[i]);
break;
rk_cmd = rk_busy = 0; /* clear registers */
rk_ma = rk_da = 0;
for (i = 0; i < RK_NUMDR; i++) sim_cancel (&rk_unit[i]);
break;
case RKX_CLD: /* reset drive */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
else rk_go (RKC_SEEK, 0); /* seek to 0 */
break; } /* end switch AC */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
else rk_go (RKC_SEEK, 0); /* seek to 0 */
break; } /* end switch AC */
break;
case 3: /* DLAG */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
else { rk_da = AC; /* load disk addr */
rk_go (GET_FUNC (rk_cmd), GET_CYL (rk_cmd, rk_da)); }
else {
rk_da = AC; /* load disk addr */
rk_go (GET_FUNC (rk_cmd), GET_CYL (rk_cmd, rk_da)); }
break;
case 4: /* DLCA */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
@@ -235,8 +236,9 @@ case 5: /* DRST */
return rk_sta;
case 6: /* DLDC */
if (rk_busy != 0) rk_sta = rk_sta | RKS_BUSY;
else { rk_cmd = AC; /* load command */
rk_sta = 0; } /* clear status */
else {
rk_cmd = AC; /* load command */
rk_sta = 0; } /* clear status */
break;
case 7: /* DMAN */
break; } /* end case pulse */
@@ -305,8 +307,8 @@ UNIT *seluptr;
if (uptr->FUNC == RKC_SEEK) { /* seek? */
seluptr = rk_dev.units + GET_DRIVE (rk_cmd); /* see if selected */
if ((uptr == seluptr) && ((rk_cmd & RKC_SKDN) != 0)) {
rk_sta = rk_sta | RKS_DONE;
RK_INT_UPDATE; }
rk_sta = rk_sta | RKS_DONE;
RK_INT_UPDATE; }
return SCPE_OK; }
if ((uptr->flags & UNIT_ATT) == 0) { /* not att? abort */
@@ -332,21 +334,21 @@ if ((uptr->FUNC == RKC_READ) && (err == 0) && MEM_ADDR_OK (pa)) { /* read? */
for ( ; awc < wc; awc++) M[pa + awc] = 0; /* fill if eof */
err = ferror (uptr->fileref);
if ((wc1 > 0) && (err == 0)) { /* field wraparound? */
pa = pa & 070000; /* wrap phys addr */
awc = fxread (&M[pa], sizeof (int16), wc1, uptr->fileref);
for ( ; awc < wc1; awc++) M[pa + awc] = 0; /* fill if eof */
err = ferror (uptr->fileref); } }
pa = pa & 070000; /* wrap phys addr */
awc = fxread (&M[pa], sizeof (int16), wc1, uptr->fileref);
for ( ; awc < wc1; awc++) M[pa + awc] = 0; /* fill if eof */
err = ferror (uptr->fileref); } }
if ((uptr->FUNC == RKC_WRITE) && (err == 0)) { /* write? */
fxwrite (&M[pa], sizeof (int16), wc, uptr->fileref);
err = ferror (uptr->fileref);
if ((wc1 > 0) && (err == 0)) { /* field wraparound? */
pa = pa & 070000; /* wrap phys addr */
fxwrite (&M[pa], sizeof (int16), wc1, uptr->fileref);
err = ferror (uptr->fileref); }
pa = pa & 070000; /* wrap phys addr */
fxwrite (&M[pa], sizeof (int16), wc1, uptr->fileref);
err = ferror (uptr->fileref); }
if ((rk_cmd & RKC_HALF) && (err == 0)) { /* fill half sector */
fxwrite (fill, sizeof (int16), RK_NUMWD/2, uptr->fileref);
err = ferror (uptr->fileref); } }
fxwrite (fill, sizeof (int16), RK_NUMWD/2, uptr->fileref);
err = ferror (uptr->fileref); } }
rk_ma = (rk_ma + swc) & 07777; /* incr mem addr reg */
rk_sta = rk_sta | RKS_DONE; /* set done */

51
PDP8/pdp8_rl.c
View File

@@ -278,26 +278,27 @@ case 4: /* RLCB */
uptr = rl_dev.units + GET_DRIVE (rlcsb); /* select unit */
switch (GET_FUNC (rlcsb)) { /* case on func */
case RLCSB_CLRD: /* clear drive */
uptr->STAT = uptr->STAT & ~RLDS_ERR; /* clear errors */
uptr->STAT = uptr->STAT & ~RLDS_ERR; /* clear errors */
case RLCSB_MNT: /* mnt */
rl_set_done (0);
break;
rl_set_done (0);
break;
case RLCSB_SEEK: /* seek */
curr = GET_CYL (uptr->TRK); /* current cylinder */
offs = GET_CYL (rlcsa); /* offset */
if (rlcsa & RLCSA_DIR) { /* in or out? */
newc = curr + offs; /* out */
maxc = (uptr->flags & UNIT_RL02)?
RL_NUMCY * 2: RL_NUMCY;
if (newc >= maxc) newc = maxc - 1; }
else { newc = curr - offs; /* in */
if (newc < 0) newc = 0; }
uptr->TRK = newc | (rlcsa & RLCSA_HD);
sim_activate (uptr, rl_swait * abs (newc - curr));
break;
curr = GET_CYL (uptr->TRK); /* current cylinder */
offs = GET_CYL (rlcsa); /* offset */
if (rlcsa & RLCSA_DIR) { /* in or out? */
newc = curr + offs; /* out */
maxc = (uptr->flags & UNIT_RL02)?
RL_NUMCY * 2: RL_NUMCY;
if (newc >= maxc) newc = maxc - 1; }
else {
newc = curr - offs; /* in */
if (newc < 0) newc = 0; }
uptr->TRK = newc | (rlcsa & RLCSA_HD);
sim_activate (uptr, rl_swait * abs (newc - curr));
break;
default: /* data transfer */
sim_activate (uptr, rl_swait); /* activate unit */
break; } /* end switch func */
sim_activate (uptr, rl_swait); /* activate unit */
break; } /* end switch func */
break;
case 5: /* RLSA */
rlsa = GET_SECT (AC);
@@ -322,7 +323,7 @@ case 0: /* RRER */
uptr = rl_dev.units + GET_DRIVE (rlcsb); /* select unit */
if (!sim_is_active (uptr) && /* update drdy */
(uptr->flags & UNIT_ATT))
rler = rler | RLER_DRDY;
rler = rler | RLER_DRDY;
else rler = rler & ~RLER_DRDY;
dat = rler & RLER_MASK;
break;
@@ -340,9 +341,9 @@ case 4: /* RRSA */
break;
case 5: /* RRSI */
if (rl_lft) { /* silo left? */
dat = (rlsi >> 8) & 0377; /* get left 8b */
rlsi = rlsi1; /* ripple */
rlsi1 = rlsi2; }
dat = (rlsi >> 8) & 0377; /* get left 8b */
rlsi = rlsi1; /* ripple */
rlsi1 = rlsi2; }
else dat = rlsi & 0377; /* get right 8b */
rl_lft = rl_lft ^ 1; /* change side */
break;
@@ -374,8 +375,8 @@ t_addr ma;
func = GET_FUNC (rlcsb); /* get function */
if (func == RLCSB_GSTA) { /* get status? */
rlsi = uptr->STAT |
((uptr->TRK & RLCSA_HD)? RLDS_HD: 0) |
((uptr->flags & UNIT_ATT)? RLDS_ATT: RLDS_UNATT);
((uptr->TRK & RLCSA_HD)? RLDS_HD: 0) |
((uptr->flags & UNIT_ATT)? RLDS_ATT: RLDS_UNATT);
if (uptr->flags & UNIT_RL02) rlsi = rlsi | RLDS_RL02;
if (uptr->flags & UNIT_WPRT) rlsi = rlsi | RLDS_WLK;
rlsi2 = rlsi1 = rlsi;
@@ -416,8 +417,8 @@ if (rlcsb & RLCSB_8B) { /* 8b mode? */
if (bc > maxc) wc = bc = maxc; } /* trk ovrun? limit */
else { bc = ((wc * 3) + 1) / 2; /* 12b mode */
if (bc > RL_NUMBY) { /* > 1 sector */
bc = RL_NUMBY; /* cap xfer */
wc = (RL_NUMBY * 2) / 3; } }
bc = RL_NUMBY; /* cap xfer */
wc = (RL_NUMBY * 2) / 3; } }
err = fseek (uptr->fileref, da, SEEK_SET);

51
PDP8/pdp8_rx.c
View File

@@ -223,44 +223,45 @@ case 1: /* LCD */
rx_tr = rx_err = 0; /* clear flags */
bptr = 0; /* clear buf pointer */
if (rx_28 && (AC & RXCS_MODE)) { /* RX28 8b mode? */
rx_dbr = rx_csr = AC & 0377; /* save 8b */
rx_tr = 1; /* xfer is ready */
rx_state = CMD8; } /* wait for part 2 */
else { rx_dbr = rx_csr = AC; /* save new command */
rx_cmd (); } /* issue command */
rx_dbr = rx_csr = AC & 0377; /* save 8b */
rx_tr = 1; /* xfer is ready */
rx_state = CMD8; } /* wait for part 2 */
else {
rx_dbr = rx_csr = AC; /* save new command */
rx_cmd (); } /* issue command */
return 0; /* clear AC */
case 2: /* XDR */
switch (rx_state & 017) { /* case on state */
case EMPTY: /* emptying buffer */
sim_activate (&rx_unit[drv], rx_xwait); /* sched xfer */
return READ_RXDBR; /* return data reg */
sim_activate (&rx_unit[drv], rx_xwait); /* sched xfer */
return READ_RXDBR; /* return data reg */
case CMD8: /* waiting for cmd */
rx_dbr = AC & 0377;
rx_csr = (rx_csr & 0377) | ((AC & 017) << 8);
rx_cmd ();
break;
rx_dbr = AC & 0377;
rx_csr = (rx_csr & 0377) | ((AC & 017) << 8);
rx_cmd ();
break;
case RWDS:case RWDT:case FILL:case SDCNF: /* waiting for data */
rx_dbr = AC; /* save data */
sim_activate (&rx_unit[drv], rx_xwait); /* schedule */
break;
rx_dbr = AC; /* save data */
sim_activate (&rx_unit[drv], rx_xwait); /* schedule */
break;
default: /* default */
return READ_RXDBR; } /* return data reg */
return READ_RXDBR; } /* return data reg */
break;
case 3: /* STR */
if (rx_tr != 0) {
rx_tr = 0;
return IOT_SKP + AC; }
rx_tr = 0;
return IOT_SKP + AC; }
break;
case 4: /* SER */
if (rx_err != 0) {
rx_err = 0;
return IOT_SKP + AC; }
rx_err = 0;
return IOT_SKP + AC; }
break;
case 5: /* SDN */
if ((dev_done & INT_RX) != 0) {
dev_done = dev_done & ~INT_RX;
int_req = int_req & ~INT_RX;
return IOT_SKP + AC; }
dev_done = dev_done & ~INT_RX;
int_req = int_req & ~INT_RX;
return IOT_SKP + AC; }
break;
case 6: /* INTR */
if (AC & 1) int_enable = int_enable | INT_RX;
@@ -293,9 +294,9 @@ case RXCS_READ: case RXCS_WRITE: case RXCS_WRDEL:
break;
case RXCS_SDEN:
if (rx_28) { /* RX28? */
rx_state = SDCNF; /* state = get conf */
rx_tr = 1; /* xfer is ready */
break; } /* else fall thru */
rx_state = SDCNF; /* state = get conf */
rx_tr = 1; /* xfer is ready */
break; } /* else fall thru */
default:
rx_state = CMD_COMPLETE; /* state = cmd compl */
sim_activate (&rx_unit[drv], rx_cwait); /* sched done */

213
PDP8/pdp8_sys.c
View File

@@ -114,59 +114,60 @@ rubout = state = field = newf = origin = csum = 0;
if ((sim_switches & SWMASK ('R')) || /* RIM format? */
(match_ext (fnam, "RIM") && !(sim_switches & SWMASK ('B')))) {
while ((i = getc (fileref)) != EOF) {
switch (state) {
case 0: /* leader */
if ((i != 0) && (i < 0200)) state = 1;
high = i;
break;
case 1: /* low byte */
word = (high << 6) | i; /* form word */
if (word > 07777) origin = word & 07777;
else M[origin] = word;
state = 2;
break;
case 2: /* high byte */
if (i >= 0200) return SCPE_OK; /* end of tape? */
high = i; /* save high */
state = 1;
break; } /* end switch */
} /* end while */
switch (state) {
case 0: /* leader */
if ((i != 0) && (i < 0200)) state = 1;
high = i;
break;
case 1: /* low byte */
word = (high << 6) | i; /* form word */
if (word > 07777) origin = word & 07777;
else M[origin] = word;
state = 2;
break;
case 2: /* high byte */
if (i >= 0200) return SCPE_OK; /* end of tape? */
high = i; /* save high */
state = 1;
break; } /* end switch */
} /* end while */
} /* end if */
else { while ((i = getc (fileref)) != EOF) { /* BIN format */
if (rubout) {
rubout = 0;
continue; }
if (i == 0377) {
rubout = 1;
continue; }
if (i > 0200) {
newf = (i & 070) << 9;
continue; }
switch (state) {
case 0: /* leader */
if ((i != 0) && (i != 0200)) state = 1;
high = i; /* save as high */
break;
case 1: /* low byte */
low = i;
state = 2;
break;
case 2: /* high with test */
word = (high << 6) | low;
if (i == 0200) { /* end of tape? */
if ((csum - word) & 07777) return SCPE_CSUM;
return SCPE_OK; }
csum = csum + low + high;
if (word >= 010000) origin = word & 07777;
else { if ((field | origin) >= MEMSIZE)
return SCPE_NXM;
M[field | origin] = word & 07777;
origin = (origin + 1) & 07777; }
field = newf;
high = i;
state = 1;
break; } /* end switch */
} /* end while */
if (rubout) {
rubout = 0;
continue; }
if (i == 0377) {
rubout = 1;
continue; }
if (i > 0200) {
newf = (i & 070) << 9;
continue; }
switch (state) {
case 0: /* leader */
if ((i != 0) && (i != 0200)) state = 1;
high = i; /* save as high */
break;
case 1: /* low byte */
low = i;
state = 2;
break;
case 2: /* high with test */
word = (high << 6) | low;
if (i == 0200) { /* end of tape? */
if ((csum - word) & 07777) return SCPE_CSUM;
return SCPE_OK; }
csum = csum + low + high;
if (word >= 010000) origin = word & 07777;
else {
if ((field | origin) >= MEMSIZE)
return SCPE_NXM;
M[field | origin] = word & 07777;
origin = (origin + 1) & 07777; }
field = newf;
high = i;
state = 1;
break; } /* end switch */
} /* end while */
} /* end else */
return SCPE_FMT; /* eof? error */
}
@@ -330,9 +331,9 @@ int32 i, j;
for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
if ((j == class) && (opc_val[i] & inst)) { /* same class? */
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
inst = inst & ~opc_val[i]; /* mask bit set? */
fprintf (of, (sp? " %s": "%s"), opcode[i]);
sp = 1; } }
return sp;
}
@@ -383,34 +384,34 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
switch (j) { /* case on class */
case I_V_NPN: /* no operands */
fprintf (of, "%s", opcode[i]); /* opcode */
break;
fprintf (of, "%s", opcode[i]); /* opcode */
break;
case I_V_FLD: /* field change */
fprintf (of, "%s %-o", opcode[i], (inst >> 3) & 07);
break;
fprintf (of, "%s %-o", opcode[i], (inst >> 3) & 07);
break;
case I_V_MRF: /* mem ref */
disp = inst & 0177; /* displacement */
fprintf (of, "%s%s", opcode[i], ((inst & 00400)? " I ": " "));
if (inst & 0200) { /* current page? */
if (cflag) fprintf (of, "%-o", (addr & 07600) | disp);
else fprintf (of, "C %-o", disp); }
else fprintf (of, "%-o", disp); /* page zero */
break;
disp = inst & 0177; /* displacement */
fprintf (of, "%s%s", opcode[i], ((inst & 00400)? " I ": " "));
if (inst & 0200) { /* current page? */
if (cflag) fprintf (of, "%-o", (addr & 07600) | disp);
else fprintf (of, "C %-o", disp); }
else fprintf (of, "%-o", disp); /* page zero */
break;
case I_V_IOT: /* IOT */
fprintf (of, "%s %-o", opcode[i], inst & 0777);
break;
fprintf (of, "%s %-o", opcode[i], inst & 0777);
break;
case I_V_OP1: /* operate group 1 */
sp = fprint_opr (of, inst & 0361, j, 0);
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
break;
sp = fprint_opr (of, inst & 0361, j, 0);
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
break;
case I_V_OP2: /* operate group 2 */
if (opcode[i]) fprintf (of, "%s", opcode[i]); /* skips */
fprint_opr (of, inst & 0206, j, opcode[i] != NULL);
break;
if (opcode[i]) fprintf (of, "%s", opcode[i]); /* skips */
fprint_opr (of, inst & 0206, j, opcode[i] != NULL);
break;
case I_V_OP3: /* operate group 3 */
sp = fprint_opr (of, inst & 0320, j, 0);
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
break; } /* end case */
sp = fprint_opr (of, inst & 0320, j, 0);
if (opcode[i]) fprintf (of, (sp? " %s": "%s"), opcode[i]);
break; } /* end case */
return SCPE_OK; } /* end if */
} /* end for */
return SCPE_ARG;
@@ -468,44 +469,46 @@ case I_V_IOT: /* IOT */
break;
case I_V_FLD: /* field */
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
if (opcode[i] != NULL) {
k = (opc_val[i] >> I_V_FL) & I_M_FL;
if (k != j) return SCPE_ARG;
val[0] = val[0] | (opc_val[i] & 07777); }
else { d = get_uint (gbuf, 8, 07, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | (d << 3);
break; } }
break;
if (opcode[i] != NULL) {
k = (opc_val[i] >> I_V_FL) & I_M_FL;
if (k != j) return SCPE_ARG;
val[0] = val[0] | (opc_val[i] & 07777); }
else {
d = get_uint (gbuf, 8, 07, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | (d << 3);
break; } }
break;
case I_V_MRF: /* mem ref */
cptr = get_glyph (cptr, gbuf, 0); /* get next field */
if (strcmp (gbuf, "I") == 0) { /* indirect? */
val[0] = val[0] | 0400;
cptr = get_glyph (cptr, gbuf, 0); }
val[0] = val[0] | 0400;
cptr = get_glyph (cptr, gbuf, 0); }
if ((k = (strcmp (gbuf, "C") == 0)) || (strcmp (gbuf, "Z") == 0)) {
cptr = get_glyph (cptr, gbuf, 0);
d = get_uint (gbuf, 8, 0177, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | d | (k? 0200: 0); }
else { d = get_uint (gbuf, 8, 07777, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (d <= 0177) val[0] = val[0] | d;
else if (cflag && (((addr ^ d) & 07600) == 0))
val[0] = val[0] | (d & 0177) | 0200;
else return SCPE_ARG; }
cptr = get_glyph (cptr, gbuf, 0);
d = get_uint (gbuf, 8, 0177, &r);
if (r != SCPE_OK) return SCPE_ARG;
val[0] = val[0] | d | (k? 0200: 0); }
else {
d = get_uint (gbuf, 8, 07777, &r);
if (r != SCPE_OK) return SCPE_ARG;
if (d <= 0177) val[0] = val[0] | d;
else if (cflag && (((addr ^ d) & 07600) == 0))
val[0] = val[0] | (d & 0177) | 0200;
else return SCPE_ARG; }
break;
case I_V_NPN: case I_V_OP1: case I_V_OP2: case I_V_OP3: /* operates */
for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
cptr = get_glyph (cptr, gbuf, 0)) {
for (i = 0; (opcode[i] != NULL) &&
(strcmp (opcode[i], gbuf) != 0) ; i++) ;
k = opc_val[i] & 07777;
if ((opcode[i] == NULL) || (((k ^ val[0]) & 07000) != 0))
return SCPE_ARG;
val[0] = val[0] | k; }
k = opc_val[i] & 07777;
if ((opcode[i] == NULL) || (((k ^ val[0]) & 07000) != 0))
return SCPE_ARG;
val[0] = val[0] | k; }
break; } /* end case */
if (*cptr != 0) return SCPE_ARG; /* junk at end? */
return SCPE_OK;

4
PDP8/pdp8_tt.c
View File

@@ -25,6 +25,7 @@
tti,tto KL8E terminal input/output
22-Dec-02 RMS Added break support
01-Nov-02 RMS Added 7B/8B support
04-Oct-02 RMS Added DIBs, device number support
30-May-02 RMS Widened POS to 32b
@@ -157,7 +158,8 @@ int32 c;
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
if (tti_unit.flags & UNIT_KSR) { /* UC only? */
if (c & SCPE_BREAK) tti_unit.buf = 0; /* break? */
else if (tti_unit.flags & UNIT_KSR) { /* UC only? */
c = c & 0177;
if (islower (c)) c = toupper (c);
tti_unit.buf = c | 0200; } /* add TTY bit */

28
PDP8/pdp8_ttx.c
View File

@@ -25,6 +25,7 @@
ttix,ttox PT08/KL8JA terminal input/output
22-Dec-02 RMS Added break support
02-Nov-02 RMS Added 7B/8B support
04-Oct-02 RMS Added DIB, device number support
22-Aug-02 RMS Updated for changes to sim_tmxr.c
@@ -202,15 +203,16 @@ if (ln >= 0) { /* got one? */
ttx_ldsc[ln].rcve = 1; } /* rcv enabled */
tmxr_poll_rx (&ttx_desc); /* poll for input */
for (ln = 0; ln < TTX_LINES; ln++) { /* loop thru lines */
if (ttx_ldsc[ln].conn) { /* connected? */
if (temp = tmxr_getc_ln (&ttx_ldsc[ln])) { /* get char */
if (ttox_unit[ln].flags & UNIT_UC) { /* UC mode? */
c = temp & 0177;
if (islower (c)) c = toupper (c); }
else c = temp & ((ttox_unit[ln].flags & UNIT_8B)? 0377: 0177);
ttix_buf[ln] = c;
dev_done = dev_done | (INT_TTI1 << ln);
int_req = INT_UPDATE; } } }
if (ttx_ldsc[ln].conn) { /* connected? */
if (temp = tmxr_getc_ln (&ttx_ldsc[ln])) { /* get char */
if (temp & SCPE_BREAK) c = 0; /* break? */
else if (ttox_unit[ln].flags & UNIT_UC) { /* UC? */
c = temp & 0177;
if (islower (c)) c = toupper (c); }
else c = temp & ((ttox_unit[ln].flags & UNIT_8B)? 0377: 0177);
ttix_buf[ln] = c;
dev_done = dev_done | (INT_TTI1 << ln);
int_req = INT_UPDATE; } } }
return SCPE_OK;
}
@@ -358,10 +360,10 @@ int32 i;
for (i = 0; (i < TTX_LINES) && (ttx_ldsc[i].conn == 0); i++) ;
if (i < TTX_LINES) {
for (i = 0; i < TTX_LINES; i++) {
if (ttx_ldsc[i].conn)
if (val) tmxr_fconns (st, &ttx_ldsc[i], i);
else tmxr_fstats (st, &ttx_ldsc[i], i); } }
for (i = 0; i < TTX_LINES; i++) {
if (ttx_ldsc[i].conn)
if (val) tmxr_fconns (st, &ttx_ldsc[i], i);
else tmxr_fstats (st, &ttx_ldsc[i], i); } }
else fprintf (st, "all disconnected\n");
return SCPE_OK;
}