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Notes For V2.10-0

Browse Source 
WARNING: V2.10 has reorganized and renamed some of the definition
files for the PDP-10, PDP-11, and VAX.  Be sure to delete all
previous source files before you unpack the Zip archive, or
unpack it into a new directory structure.

WARNING: V2.10 has a new, more comprehensive save file format.
Restoring save files from previous releases will cause 'invalid
register' errors and loss of CPU option flags, device enable/
disable flags, unit online/offline flags, and unit writelock
flags.

WARNING: If you are using Visual Studio .NET through the IDE,
be sure to turn off the /Wp64 flag in the project settings, or
dozens of spurious errors will be generated.

WARNING: Compiling Ethernet support under Windows requires
extra steps; see the Ethernet readme file.  Ethernet support is
currently available only for Windows, Linux, NetBSD, and OpenBSD.

1. New Features

1.1 SCP and Libraries

- The VT emulation package has been replaced by the capability
  to remote the console to a Telnet session.  Telnet clients
  typically have more complete and robust VT100 emulation.
- Simulated devices may now have statically allocated buffers,
  in addition to dynamically allocated buffers or disk-based
  data stores.
- The DO command now takes substitutable arguments (max 9).
  In command files, %n represents substitutable argument n.
- The initial command line is now interpreted as the command
  name and substitutable arguments for a DO command.  This is
  backward compatible to prior versions.
- The initial command line parses switches.  -Q is interpreted
  as quiet mode; informational messages are suppressed.
- The HELP command now takes an optional argument.  HELP <cmd>
  types help on the specified command.
- Hooks have been added for implementing GUI-based consoles,
  as well as simulator-specific command extensions.  A few
  internal data structures and definitions have changed.
- Two new routines (tmxr_open_master, tmxr_close_master) have
  been added to sim_tmxr.c.  The calling sequence for
  sim_accept_conn has been changed in sim_sock.c.
- The calling sequence for the VM boot routine has been modified
  to add an additional parameter.
- SAVE now saves, and GET now restores, controller and unit flags.
- Library sim_ether.c has been added for Ethernet support.

1.2 VAX

- Non-volatile RAM (NVR) can behave either like a memory or like
  a disk-based peripheral.  If unattached, it behaves like memory
  and is saved and restored by SAVE and RESTORE, respectively.
  If attached, its contents are loaded from disk by ATTACH and
  written back to disk at DETACH and EXIT.
- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape) has been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from vax_stddev.c and
  now references a common implementation file, dec_pt.h.
- Examine and deposit switches now work on all devices, not just
  the CPU.
- Device address conflicts are not detected until simulation starts.

1.3 PDP-11

- SHOW <device> VECTOR displays the device's interrupt vector.
  Most devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The TK50 (TMSCP tape), RK611/RK06/RK07 (cartridge disk),
  RX211 (double density floppy), and KW11P programmable clock
  have been added.
- The DEQNA/DELQA (Qbus Ethernet controllers) have been added.
- Autoconfiguration support has been added.
- The paper tape reader has been removed from pdp11_stddev.c and
  now references a common implementation file, dec_pt.h.
- Device bootstraps now use the actual CSR specified by the
  SET ADDRESS command, rather than just the default CSR.  Note
  that PDP-11 operating systems may NOT support booting with
  non-standard addresses.
- Specifying more than 256KB of memory, or changing the bus
  configuration, causes all peripherals that are not compatible
  with the current bus configuration to be disabled.
- Device address conflicts are not detected until simulation starts.

1.4 PDP-10

- SHOW <device> VECTOR displays the device's interrupt vector.
  A few devices allow the vector to be changed with SET
  <device> VECTOR=nnn.
- SHOW CPU IOSPACE displays the I/O space address map.
- The RX211 (double density floppy) has been added; it is off
  by default.
- The paper tape now references a common implementation file,
  dec_pt.h.
- Device address conflicts are not detected until simulation starts.

1.5 PDP-1

- DECtape (then known as MicroTape) support has been added.
- The line printer and DECtape can be disabled and enabled.

1.6 PDP-8

- The RX28 (double density floppy) has been added as an option to
  the existing RX8E controller.
- SHOW <device> DEVNO displays the device's device number.  Most
  devices allow the device number to be changed with SET <device>
  DEVNO=nnn.
- Device number conflicts are not detected until simulation starts.

1.7 IBM 1620

- The IBM 1620 simulator has been released.

1.8 AltairZ80

- A hard drive has been added for increased storage.
- Several bugs have been fixed.

1.9 HP 2100

- The 12845A has been added and made the default line printer (LPT).
  The 12653A has been renamed LPS and is off by default.  It also
  supports the diagnostic functions needed to run the DCPC and DMS
  diagnostics.
- The 12557A/13210A disk defaults to the 13210A (7900/7901).
- The 12559A magtape is off by default.
- New CPU options (EAU/NOEAU) enable/disable the extended arithmetic
  instructions for the 2116.  These instructions are standard on
  the 2100 and 21MX.
- New CPU options (MPR/NOMPR) enable/disable memory protect for the
  2100 and 21MX.
- New CPU options (DMS/NODMS) enable/disable the dynamic mapping
  instructions for the 21MX.
- The 12539 timebase generator autocalibrates.

1.10 Simulated Magtapes

- Simulated magtapes recognize end of file and the marker
  0xFFFFFFFF as end of medium.  Only the TMSCP tape simulator
  can generate an end of medium marker.
- The error handling in simulated magtapes was overhauled to be
  consistent through all simulators.

1.11 Simulated DECtapes

- Added support for RT11 image file format (256 x 16b) to DECtapes.

2. Release Notes

2.1 Bugs Fixed

- TS11/TSV05 was not simulating the XS0_MOT bit, causing failures
  under VMS.  In addition, two of the CTL options were coded
  interchanged.
- IBM 1401 tape was not setting a word mark under group mark for
  load mode reads.  This caused the diagnostics to crash.
- SCP bugs in ssh_break and set_logon were fixed (found by Dave
  Hittner).
- Numerous bugs in the HP 2100 extended arithmetic, floating point,
  21MX, DMS, and IOP instructions were fixed.  Bugs were also fixed
  in the memory protect and DMS functions.  The moving head disks
  (DP, DQ) were revised to simulate the hardware more accurately.
  Missing functions in DQ (address skip, read address) were added.

2.2 HP 2100 Debugging

- The HP 2100 CPU nows runs all of the CPU diagnostics.
- The peripherals run most of the peripheral diagnostics.  There
  is still a problem in overlapped seek operation on the disks.
  See the file hp2100_diag.txt for details.

3. In Progress

These simulators are not finished and are available in a separate
Zip archive distribution.

- Interdata 16b/32b: coded, partially tested.  See the file
  id_diag.txt for details.
- SDS 940: coded, partially tested.
This commit is contained in:
Bob Supnik
2002-11-17 15:54:00 -08:00
committed by Mark Pizzolato
parent df6475181c
commit 2c2dd5ea33
218 changed files with 44103 additions and 17112 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
PDP10/pdp10_cpu.c
View File

@@ -25,6 +25,8 @@
cpu KS10 central processor
08-Oct-02 RMS Revised to build dib_tab dynamically
Added SHOW IOSPACE
30-Dec-01 RMS Added old PC queue
25-Dec-01 RMS Cleaned up sim_inst declarations
07-Dec-01 RMS Revised to use new breakpoint package
@@ -111,11 +113,10 @@
3. Arithmetic. The PDP-10 is a 2's complement system.
4. Adding I/O devices. Three modules must be modified:
4. Adding I/O devices. These modules must be modified:
pdp10_defs.h add interrupt request definition
pdp10_ksio.c add I/O page linkages
pdp10_sys.c add pointer to data structures to sim_devices
pdp10_defs.h add device address and interrupt definitions
pdp10_sys.c add sim_devices table entry
A note on ITS 1-proceed. The simulator follows the implementation
on the KS10, keeping 1-proceed as a side flag (its_1pr) rather than
@@ -225,6 +226,8 @@ int32 pi_eval (void);
int32 test_int (void);
void set_ac_display (d10 *acbase);
extern t_stat build_dib_tab (void);
extern t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
extern d10 Read (a10 ea, int32 prv); /* read, read check */
extern d10 ReadM (a10 ea, int32 prv); /* read, write check */
extern d10 ReadE (a10 ea); /* read, exec */
@@ -361,8 +364,6 @@ REG cpu_reg[] = {
{ ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ DRDATA (INDMAX, ind_max, 8), PV_LEFT + REG_NZ },
{ DRDATA (XCTMAX, xct_max, 8), PV_LEFT + REG_NZ },
{ FLDATA (ITS, cpu_unit.flags, UNIT_V_ITS), REG_HRO },
{ FLDATA (T20V41, cpu_unit.flags, UNIT_V_T20V41), REG_HRO },
{ ORDATA (WRU, sim_int_char, 8) },
{ FLDATA (STOP_ILL, stop_op0, 0) },
{ BRDATA (REG, acs, 8, 36, AC_NUM * AC_NBLK) },
@@ -372,6 +373,8 @@ MTAB cpu_mod[] = {
{ UNIT_ITS+UNIT_T20V41, 0, "Standard microcode", "STANDARD", NULL },
{ UNIT_ITS+UNIT_T20V41, UNIT_T20V41, "TOPS-20 V4.1", "TOPS20V41", NULL },
{ UNIT_ITS+UNIT_T20V41, UNIT_ITS, "ITS microcode", "ITS", NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ 0 } };
DEVICE cpu_dev = {
@@ -581,9 +584,11 @@ t_stat sim_instr (void)
{
a10 PC; /* set by setjmp */
int abortval = 0; /* abort value */
t_stat r;
/* Restore register state */
if ((r = build_dib_tab ()) != SCPE_OK) return r; /* build, chk dib_tab */
pager_PC = PC = saved_PC & AMASK; /* load local PC */
set_dyn_ptrs (); /* set up local ptrs */
pager_tc = FALSE; /* not in trap cycle */
@@ -605,7 +610,7 @@ if ((abortval > 0) || pager_pi) { /* stop or pi err? */
abortval = STOP_PAGINT; /* stop for pi err */
saved_PC = pager_PC & AMASK; /* failing instr PC */
set_ac_display (ac_cur); /* set up AC display */
pcq_r -> qptr = pcq_p; /* update pc q ptr */
pcq_r->qptr = pcq_p; /* update pc q ptr */
return abortval; } /* return to SCP */
/* Page fail - checked against KS10 ucode
@@ -2044,7 +2049,7 @@ pi_eval ();
if (M == NULL) M = calloc (MAXMEMSIZE, sizeof (d10));
if (M == NULL) return SCPE_MEM;
pcq_r = find_reg ("PCQ", NULL, dptr);
if (pcq_r) pcq_r -> qptr = 0;
if (pcq_r) pcq_r->qptr = 0;
else return SCPE_IERR;
sim_brk_types = sim_brk_dflt = SWMASK ('E');
return SCPE_OK;
@@ -2087,6 +2092,6 @@ int i;
rptr = find_reg ("AC0", NULL, &cpu_dev);
if (rptr == NULL) return;
for (i = 0; i < AC_NUM; i++, rptr++) rptr -> loc = (void *) (acbase + i);
for (i = 0; i < AC_NUM; i++, rptr++) rptr->loc = (void *) (acbase + i);
return;
}

54
PDP10/pdp10_defs.h
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
29-Sep-02 RMS Added variable vector, RX211 support
22-Apr-02 RMS Removed magtape record length error
20-Jan-02 RMS Added multiboard DZ11 support
23-Oct-01 RMS New IO page address constants
@@ -34,6 +35,9 @@
19-May-01 RMS Added workaround for TOPS-20 V4.1 boot bug
*/
#ifndef _PDP10_DEFS_H_
#define _PDP10_DEFS_H_ 0
#include "sim_defs.h" /* simulator defns */
/* Digital Equipment Corporation's 36b family had six implementations:
@@ -576,19 +580,38 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
/* Device information block */
#define VEC_DEVMAX 8 /* max device vec */
struct pdp_dib {
uint32 enb; /* enabled */
uint32 ba; /* base addr */
uint32 lnt; /* length */
t_stat (*rd)(int32 *dat, int32 ad, int32 md);
t_stat (*wr)(int32 dat, int32 ad, int32 md); };
t_stat (*wr)(int32 dat, int32 ad, int32 md);
int32 vnum; /* vectors: number */
int32 vloc; /* locator */
int32 vec; /* value */
int32 (*ack[VEC_DEVMAX])(void); /* ack routines */
};
typedef struct pdp_dib DIB;
/* DZ11 parameters */
/* I/O system parameters */
#define DZ_MUXES 4 /* max # of muxes */
#define DZ_LINES 8 /* lines per mux */
#define DIB_MAX 100 /* max DIBs */
#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */
#define DEV_V_FLTA (DEV_V_UF + 2) /* float addr */
#define DEV_UBUS (1u << DEV_V_UBUS)
#define DEV_QBUS (1u << DEV_V_QBUS)
#define DEV_FLTA (1u << DEV_V_FLTA)
#define UNIBUS TRUE /* 18b only */
#define FST 0 /* Unibus 1 */
#define MAP 1 /* Unibus 3 */
/* I/O page layout */
@@ -614,12 +637,16 @@ typedef struct pdp_dib DIB;
#define IOLN_UBCS3 001
#define IOBA_UBMNT3 (IO_UBA3 + 0763101) /* Unibus 3 maint reg */
#define IOLN_UBMNT3 001
#define IOBA_RY (IO_UBA3 + 0777170) /* RX211 */
#define IOLN_RY 004
#define IOBA_TU (IO_UBA3 + 0772440) /* RH11/tape */
#define IOLN_TU 034
#define IOBA_LP20 (IO_UBA3 + 0775400) /* LP20 */
#define IOLN_LP20 020
#define IOBA_PT (IO_UBA3 + 0777550) /* PC11 */
#define IOLN_PT 010
#define IOBA_PTR (IO_UBA3 + 017550) /* PC11 reader */
#define IOLN_PTR 004
#define IOBA_PTP (IO_UBA3 + 017554) /* PC11 punch */
#define IOLN_PTP 004
/* Common Unibus CSR flags */
@@ -647,6 +674,7 @@ typedef struct pdp_dib DIB;
#define INT_V_TU 7 /* RH11/TM03/TU45 */
#define INT_V_DZRX 16 /* DZ11 */
#define INT_V_DZTX 17
#define INT_V_RY 18 /* RX211 */
#define INT_V_PTR 24 /* PC11 */
#define INT_V_PTP 25
#define INT_V_LP20 26 /* LPT20 */
@@ -655,6 +683,7 @@ typedef struct pdp_dib DIB;
#define INT_TU (1u << INT_V_TU)
#define INT_DZRX (1u << INT_V_DZRX)
#define INT_DZTX (1u << INT_V_DZTX)
#define INT_RY (1u << INT_V_RY)
#define INT_PTR (1u << INT_V_PTR)
#define INT_PTP (1u << INT_V_PTP)
#define INT_LP20 (1u << INT_V_LP20)
@@ -663,6 +692,7 @@ typedef struct pdp_dib DIB;
#define IPL_TU 6
#define IPL_DZRX 5
#define IPL_DZTX 5
#define IPL_RY 5
#define IPL_PTR 4
#define IPL_PTP 4
#define IPL_LP20 4
@@ -675,21 +705,31 @@ typedef struct pdp_dib DIB;
#define INT_IPL5 0x000FFF00
#define INT_IPL4 0x3FF00000
#define VEC_Q 0000 /* vector base */
#define VEC_PTR 0070 /* interrupt vectors */
#define VEC_PTP 0074
#define VEC_TU 0224
#define VEC_RP 0254
#define VEC_RY 0264
#define VEC_DZRX 0340
#define VEC_DZTX 0344
#define VEC_LP20 0754
#define IVCL(dv) (INT_V_##dv)
#define IREQ(dv) int_req
#define SET_INT(dv) IREQ(dv) = IREQ(dv) | (INT_##dv)
#define CLR_INT(dv) IREQ(dv) = IREQ(dv) & ~(INT_##dv)
/* Function prototypes */
int32 Map_ReadB (t_addr ba, int32 bc, uint8 *buf, t_bool ub);
int32 Map_ReadW (t_addr ba, int32 bc, uint16 *buf, t_bool ub);
int32 Map_WriteB (t_addr ba, int32 bc, uint8 *buf, t_bool ub);
int32 Map_WriteW (t_addr ba, int32 bc, uint16 *buf, t_bool ub);
t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);
t_bool dev_conflict (uint32 nba, DIB *curr);
t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat auto_config (uint32 rank, uint32 num);
#endif

93
PDP10/pdp10_doc.txt
View File

@@ -1,7 +1,7 @@
To: Users
From: Bob Supnik
Subj: PDP-10 Simulator Usage
Date: 15-Jun-2002
Date: 15-Nov-2002
COPYRIGHT NOTICE
@@ -39,13 +39,14 @@ This memorandum documents the PDP-10 simulator.
To compile the PDP-10, you must define USE_INT64 as part of the compilation
command line.
sim/ sim_defs.h
sim/ dec_dz.h
dec_pt.h
sim_defs.h
sim_rev.h
sim_sock.h
sim_tmxr.h
dec_dz.h
scp.c
scp_tty.c
sim_rev.c
sim_sock.c
sim_tmxr.c
@@ -63,6 +64,8 @@ sim/pdp10/ pdp10_defs.h
pdp10_tu.c
pdp10_xtnd.c
sim/pdp11/ pdp11_ry.c
2. PDP-10 Features
The PDP-10 simulator is configured as follows:
@@ -76,14 +79,19 @@ UBA Unibus adapters (translation maps)
FE console
TIM timer
PTR,PTP PC11 paper tape reader/punch
RY RX211/RX02 floppy disk and two drives
DZ DZ11 8-line terminal multiplexor (up to 4)
LP20 LP20 line printer
RP RH11/RP04/RP05/RP06/RP07/RM03/RM05/RM80 controller with
eight drives
TU RH11/TM02/TU45 controller with eight drives
The PTR/PTP are initially set DISABLED. The DZ11 and LP20 can also be
set DISABLED.
The PTR, PTP, and RX211 are initially set DISABLED. The DZ11 and LP20 can
also be set DISABLED. Some devices support the SET ADDRESS command, which
allows the I/O page address of the device to be changed, and the SET VECTOR
command, which allows the vector of the device to be changed. All devices
support the SHOW ADDRESS and SHOW VECTOR commands, which display the device
address and vector, respectively.
The PDP-10 simulator implements several unique stop condition:
@@ -112,6 +120,7 @@ microcode
SET CPU STANDARD Standard microcode
SET CPU TOPS20V41 Standard microcode with TOPS-20 V4.1 bug fix
SET CPU ITS ITS compatible microcode
SHOW CPU IOSPACE show I/O space address map
CPU registers include the visible state of the processor as well as the
control registers for the interrupt system.
@@ -234,6 +243,9 @@ The paper tape reader (PTR) reads data from a disk file. The POS
register specifies the number of the next data item to be read. Thus,
by changing POS, the user can backspace or advance the reader.
The paper tape reader requires an unsupported driver under TOPS-10
and is not supported under TOPS-20 or ITS.
The paper tape reader implements these registers:
name size comments
@@ -268,6 +280,9 @@ The paper tape punch (PTP) writes data to a disk file. The POS
register specifies the number of the next data item to be written.
Thus, by by changing POS, the user can backspace or advance the punch.
The paper tape punch requires an unsupported driver under TOPS-10
and is not supported under TOPS-20 or ITS.
The paper tape punch implements these registers:
name size comments
@@ -300,6 +315,13 @@ are supported. The number of lines can be changed with the command
The line count must be a multiple of 8, with a maximum of 32.
The DZ11 can support 8-bit input and output of characters. 8-bit
output is incompatible with TOPS-20 and is off by default. The command
SET DZ 8B
allows output characters to be 8 bits.
The terminal lines perform input and output through Telnet sessions
connected to a user-specified port. The ATTACH command specifies
the port to be used:
@@ -443,12 +465,11 @@ Error handling is as follows:
error processed as
not attached tape not ready
not attached tape not ready; if STOP_IOE, stop
end of file (read or space) end of physical tape
(write) ignored
end of file operation incomplete
OS I/O error report error and stop
OS I/O error parity error; if STOP_IOE, stop
2.11 LP20 DMA Line Printer (LP20)
@@ -492,7 +513,57 @@ Error handling is as follows:
OS I/O error x report error and stop
2.12 Symbolic Display and Input
2.12 RX211/RX02 Floppy Disk (RY)
RX211 options include the ability to set units write enabled or write
locked, single or double density, or autosized:
SET RYn LOCKED set unit n write locked
SET RYn WRITEENABLED set unit n write enabled
SET RYn SINGLE set unit n single density
SET RYn DOUBLE set unit n double density (default)
SET RYn AUTOSIZE set unit n autosized
The RX211 supports the BOOT command, but only for double density.
The floppy disk requires an unsupported driver under TOPS-10 and
is not supported under TOPS-20 or ITS.
The RX211 implements these registers:
name size comments
RYCS 16 status
RYBA 16 buffer address
RYWC 8 word count
RYDB 16 data buffer
RYES 12 error status
RYERR 8 error code
RYTA 8 current track
RYSA 8 current sector
STAPTR 4 controller state
INT 1 interrupt pending flag
ERR 1 error flag (CSR<15>)
TR 1 transfer ready flag (CSR<7>)
IE 1 interrupt enable flag (CSR<6>)
DONE 1 device done flag (CSR<5>)
CTIME 24 command completion time
STIME 24 seek time, per track
XTIME 24 transfer ready delay
STOP_IOE 1 stop on I/O error
SBUF[0:255] 8 sector buffer array
Error handling is as follows:
error STOP_IOE processed as
not attached 1 report error and stop
0 disk not ready
RX02 data files are buffered in memory; therefore, end of file and OS
I/O errors cannot occur.
2.13 Symbolic Display and Input
The PDP-10 simulator implements symbolic display and input. Display is
controlled by command line switches:

3
PDP10/pdp10_dz.c
View File

@@ -26,5 +26,8 @@
dz DZ11 terminal multiplexor
*/
#define VM_PDP10 0 /* no flt addr */
#define RANK_DZ 0 /* no autoconfig */
#include "pdp10_defs.h"
#include "dec_dz.h"

345
PDP10/pdp10_ksio.c
View File

@@ -25,6 +25,9 @@
uba Unibus adapters
10-Oct-02 RMS Revised for dynamic table generation
Added SHOW IOSPACE routine
29-Sep-02 RMS Added variable vector, central map support
25-Jan-02 RMS Revised for multiple DZ11's
06-Jan-02 RMS Revised enable/disable support
23-Sep-01 RMS New IO page address constants
@@ -66,6 +69,7 @@
#include "pdp10_defs.h"
#include <setjmp.h>
#define XBA_MBZ 0400000 /* ba mbz */
#define eaRB (ea & ~1)
#define GETBYTE(ea,x) ((((ea) & 1)? (x) >> 8: (x)) & 0377)
#define UBNXM_FAIL(pa,op) \
@@ -91,22 +95,25 @@ static const int32 ubabr76[UBANUM] = {
INT_UB1 & (INT_IPL7 | INT_IPL6), INT_UB3 & (INT_IPL7 | INT_IPL6) };
static const int32 ubabr54[UBANUM] = {
INT_UB1 & (INT_IPL5 | INT_IPL4), INT_UB3 & (INT_IPL5 | INT_IPL4) };
static const int32 ubashf[4] = { 18, 26, 0, 8 };
extern d10 *M; /* main memory */
extern d10 *ac_cur;
extern d10 pager_word;
extern int32 flags, pi_l2bit[8];
extern UNIT cpu_unit;
extern FILE *sim_log;
extern jmp_buf save_env;
extern DEVICE *sim_devices[];
extern d10 Read (a10 ea);
extern void pi_eval ();
extern DIB dz_dib, pt_dib, lp20_dib, rp_dib, tu_dib, tcu_dib;
extern int32 rp_inta (void);
extern int32 tu_inta (void);
extern int32 lp20_inta (void);
extern int32 dz_rxinta (void);
extern int32 dz_txinta (void);
t_stat ubmap_rd (int32 *data, int32 addr, int32 access);
t_stat ubmap_wr (int32 data, int32 addr, int32 access);
t_stat ubs_rd (int32 *data, int32 addr, int32 access);
@@ -118,7 +125,6 @@ t_stat uba_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat uba_reset (DEVICE *dptr);
d10 ReadIO (a10 ea);
void WriteIO (a10 ea, d10 val, int32 mode);
t_bool dev_conflict (uint32 nba, DIB *curr);
/* Unibus adapter data structures
@@ -127,13 +133,13 @@ t_bool dev_conflict (uint32 nba, DIB *curr);
uba_reg UBA register list
*/
DIB ubmp1_dib = { 1, IOBA_UBMAP1, IOLN_UBMAP1, &ubmap_rd, &ubmap_wr };
DIB ubmp3_dib = { 1, IOBA_UBMAP3, IOLN_UBMAP3, &ubmap_rd, &ubmap_wr };
DIB ubcs1_dib = { 1, IOBA_UBCS1, IOLN_UBCS1, &ubs_rd, &ubs_wr };
DIB ubcs3_dib = { 1, IOBA_UBCS3, IOLN_UBCS3, &ubs_rd, &ubs_wr };
DIB ubmn1_dib = { 1, IOBA_UBMNT1, IOLN_UBMNT1, &rd_zro, &wr_nop };
DIB ubmn3_dib = { 1, IOBA_UBMNT3, IOLN_UBMNT3, &rd_zro, &wr_nop };
DIB msys_dib = { 1, 00100000, 00100001, &rd_zro, &wr_nop };
DIB ubmp1_dib = { IOBA_UBMAP1, IOLN_UBMAP1, &ubmap_rd, &ubmap_wr, 0 };
DIB ubmp3_dib = { IOBA_UBMAP3, IOLN_UBMAP3, &ubmap_rd, &ubmap_wr, 0 };
DIB ubcs1_dib = { IOBA_UBCS1, IOLN_UBCS1, &ubs_rd, &ubs_wr, 0 };
DIB ubcs3_dib = { IOBA_UBCS3, IOLN_UBCS3, &ubs_rd, &ubs_wr, 0 };
DIB ubmn1_dib = { IOBA_UBMNT1, IOLN_UBMNT1, &rd_zro, &wr_nop, 0 };
DIB ubmn3_dib = { IOBA_UBMNT3, IOLN_UBMNT3, &rd_zro, &wr_nop, 0 };
DIB msys_dib = { 00100000, 1, &rd_zro, &wr_nop, 0 };
UNIT uba_unit[] = {
{ UDATA (NULL, UNIT_FIX, UMAP_MEMSIZE) },
@@ -149,17 +155,18 @@ DEVICE uba_dev = {
"UBA", uba_unit, uba_reg, NULL,
UBANUM, 8, UMAP_ASIZE, 1, 8, 32,
&uba_ex, &uba_dep, &uba_reset,
NULL, NULL, NULL };
NULL, NULL, NULL,
NULL, 0 };
/* PDP-11 I/O structures */
DIB *dib_tab[] = {
&rp_dib,
&tu_dib,
&dz_dib,
&lp20_dib,
&pt_dib,
&tcu_dib,
DIB *dib_tab[DIB_MAX]; /* run-time DIBs */
int32 (*int_ack[32])(void); /* int ack routines */
int32 int_vec[32]; /* int vectors */
DIB *std_dib[] = { /* standard DIBs */
&ubmp1_dib,
&ubmp3_dib,
&ubcs1_dib,
@@ -168,22 +175,6 @@ DIB *dib_tab[] = {
&ubmn3_dib,
&msys_dib,
NULL };
/* Interrupt request to interrupt action map */
int32 (*int_ack[32])() = { /* int ack routines */
NULL, NULL, NULL, NULL, NULL, NULL, &rp_inta, &tu_inta,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
&dz_rxinta, &dz_txinta, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, &lp20_inta, NULL, NULL, NULL, NULL, NULL };
/* Interrupt request to vector map */
int32 int_vec[32] = { /* int req to vector */
0, 0, 0, 0, 0, 0, VEC_RP, VEC_TU,
0, 0, 0, 0, 0, 0, 0, 0,
VEC_DZRX, VEC_DZTX, 0, 0, 0, 0, 0, 0,
VEC_PTR, VEC_PTP, VEC_LP20, 0, 0, 0, 0, 0 };
/* IO 710 (DEC) TIOE - test I/O word, skip if zero
(ITS) IORDI - read word from Unibus 3
@@ -378,9 +369,9 @@ int32 i, n, val;
DIB *dibp;
for (i = 0; dibp = dib_tab[i]; i++ ) {
if (dibp -> enb && (pa >= dibp -> ba) &&
(pa < (dibp -> ba + dibp -> lnt))) {
dibp -> rd (&val, pa, READ);
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->rd (&val, pa, READ);
pi_eval ();
return ((d10) val); } }
UBNXM_FAIL (pa, READ);
@@ -393,14 +384,97 @@ int32 i, n;
DIB *dibp;
for (i = 0; dibp = dib_tab[i]; i++ ) {
if (dibp -> enb && (pa >= dibp -> ba) &&
(pa < (dibp -> ba + dibp -> lnt))) {
dibp -> wr ((int32) val, pa, mode);
if ((pa >= dibp->ba) &&
(pa < (dibp->ba + dibp->lnt))) {
dibp->wr ((int32) val, pa, mode);
pi_eval ();
return; } }
UBNXM_FAIL (pa, mode);
}
/* Mapped read and write routines - used by word-oriented Unibus devices */
a10 Map_Addr10 (a10 ba, int32 ub)
{
a10 pa10;
int32 vpn = PAG_GETVPN (ba >> 2); /* get PDP-10 page number */
if ((vpn >= UMAP_MEMSIZE) || (ba & XBA_MBZ) ||
((ubmap[ub][vpn] & UMAP_VLD) == 0)) return -1; /* invalid map? */
pa10 = (ubmap[ub][vpn] + PAG_GETOFF (ba >> 2)) & PAMASK;
return pa10;
}
int32 Map_ReadB (t_addr ba, int32 bc, uint8 *buf, t_bool ub)
{
t_addr lim;
a10 pa10;
lim = ba + bc;
for ( ; ba < lim; ba++) { /* by bytes */
pa10 = Map_Addr10 (ba, ub); /* map addr */
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
ubcs[ub] = ubcs[ub] | UBCS_TMO; /* UBA times out */
return (lim - ba); } /* return bc */
*buf++ = (uint8) ((M[pa10] >> ubashf[ba & 3]) & 0377);
}
return 0;
}
int32 Map_ReadW (t_addr ba, int32 bc, uint16 *buf, t_bool ub)
{
t_addr lim;
a10 pa10;
ba = ba & ~01; /* align start */
lim = ba + (bc & ~01);
for ( ; ba < lim; ba = ba + 2) { /* by words */
pa10 = Map_Addr10 (ba, ub); /* map addr */
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
ubcs[ub] = ubcs[ub] | UBCS_TMO; /* UBA times out */
return (lim - ba); } /* return bc */
*buf++ = (uint16) ((M[pa10] >> ((ba & 2)? 0: 18)) & 0177777);
}
return 0;
}
int32 Map_WriteB (t_addr ba, int32 bc, uint8 *buf, t_bool ub)
{
t_addr lim;
a10 pa10;
static d10 mask = 0377;
lim = ba + bc;
for ( ; ba < lim; ba++) { /* by bytes */
pa10 = Map_Addr10 (ba, ub); /* map addr */
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
ubcs[ub] = ubcs[ub] | UBCS_TMO; /* UBA times out */
return (lim - ba); } /* return bc */
M[pa10] = (M[pa10] & ~(mask << ubashf[ba & 3])) |
(((d10) *buf++) << ubashf[ba & 3]); }
return 0;
}
int32 Map_WriteW (t_addr ba, int32 bc, uint16 *buf, t_bool ub)
{
t_addr lim;
a10 pa10;
d10 val;
ba = ba & ~01; /* align start */
lim = ba + (bc & ~01);
for ( ; ba < lim; ba++) { /* by bytes */
pa10 = Map_Addr10 (ba, ub); /* map addr */
if ((pa10 < 0) || MEM_ADDR_NXM (pa10)) { /* inv map or NXM? */
ubcs[ub] = ubcs[ub] | UBCS_TMO; /* UBA times out */
return (lim - ba); } /* return bc */
val = *buf++; /* get data */
if (ba & 2) M[pa10] = (M[pa10] & 0777777600000) | val;
else M[pa10] = (M[pa10] & 0600000777777) | (val << 18);
}
return 0;
}
/* Evaluate Unibus priority interrupts */
int32 pi_ub_eval ()
@@ -530,24 +604,27 @@ pi_eval ();
return SCPE_OK;
}
/* Change device number for a device */
/* Change device address */
t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc)
{
DEVICE *dptr;
DIB *dibp;
uint32 newba;
t_stat r;
if (cptr == NULL) return SCPE_ARG;
if ((val == 0) || (desc == NULL)) return SCPE_IERR;
dibp = (DIB *) desc;
if ((val == 0) || (uptr == NULL)) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
dibp = (DIB *) dptr->ctxt;
if (dibp == NULL) return SCPE_IERR;
newba = (uint32) get_uint (cptr, 8, PAMASK, &r); /* get new */
if ((r != SCPE_OK) || (newba == dibp -> ba)) return r;
if ((newba & AMASK) <= IOPAGEBASE) return SCPE_ARG; /* must be > 0 */
if ((r != SCPE_OK) || (newba == dibp->ba)) return r;
if (GET_IOUBA (newba) != GET_IOUBA (dibp->ba)) return SCPE_ARG;
if (newba % ((uint32) val)) return SCPE_ARG; /* check modulus */
if (GET_IOUBA (newba) != GET_IOUBA (dibp -> ba)) return SCPE_ARG;
if (dev_conflict (newba, dibp)) return SCPE_OK;
dibp -> ba = newba; /* store */
if (GET_IOUBA (newba) != GET_IOUBA (dibp->ba)) return SCPE_ARG;
dibp->ba = newba; /* store */
return SCPE_OK;
}
@@ -555,61 +632,163 @@ return SCPE_OK;
t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc)
{
DEVICE *dptr;
DIB *dibp;
if (desc == NULL) return SCPE_IERR;
dibp = (DIB *) desc;
if (dibp -> ba <= IOPAGEBASE) return SCPE_IERR;
fprintf (st, "address=%07o", dibp -> ba);
if (dibp -> lnt > 1)
fprintf (st, "-%07o", dibp -> ba + dibp -> lnt - 1);
if (uptr == NULL) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
dibp = (DIB *) dptr->ctxt;
if ((dibp == NULL) || (dibp->ba <= IOPAGEBASE)) return SCPE_IERR;
fprintf (st, "address=%07o", dibp->ba);
if (dibp->lnt > 1)
fprintf (st, "-%07o", dibp->ba + dibp->lnt - 1);
return SCPE_OK;
}
/* Enable or disable a device */
/* Change device vector */
t_stat set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc)
t_stat set_vec (UNIT *uptr, int32 arg, char *cptr, void *desc)
{
int32 i;
DEVICE *dptr;
DIB *dibp;
UNIT *up;
uint32 newvec;
t_stat r;
if (cptr != NULL) return SCPE_ARG;
if ((uptr == NULL) || (desc == NULL)) return SCPE_IERR;
dptr = find_dev_from_unit (uptr); /* find device */
if (cptr == NULL) return SCPE_ARG;
if (uptr == NULL) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
dibp = (DIB *) desc;
if ((val ^ dibp -> enb) == 0) return SCPE_OK; /* enable chg? */
if (val) { /* enable? */
if (dev_conflict (dibp -> ba, dibp)) return SCPE_OK; }
else { /* disable */
for (i = 0; i < dptr -> numunits; i++) { /* check units */
up = (dptr -> units) + i;
if ((up -> flags & UNIT_ATT) || sim_is_active (up))
return SCPE_NOFNC; } }
dibp -> enb = val;
if (dptr -> reset) return dptr -> reset (dptr);
else return SCPE_OK;
dibp = (DIB *) dptr->ctxt;
if (dibp == NULL) return SCPE_IERR;
newvec = (uint32) get_uint (cptr, 8, VEC_Q + 01000, &r);
if ((r != SCPE_OK) || (newvec <= VEC_Q) ||
((newvec + (dibp->vnum * 4)) >= (VEC_Q + 01000)) ||
(newvec & ((dibp->vnum > 1)? 07: 03))) return SCPE_ARG;
dibp->vec = newvec;
return SCPE_OK;
}
/* Show device vector */
t_stat show_vec (FILE *st, UNIT *uptr, int32 arg, void *desc)
{
DEVICE *dptr;
DIB *dibp;
uint32 vec, numvec;
if (uptr == NULL) return SCPE_IERR;
dptr = find_dev_from_unit (uptr);
if (dptr == NULL) return SCPE_IERR;
dibp = (DIB *) dptr->ctxt;
if (dibp == NULL) return SCPE_IERR;
vec = dibp->vec;
if (arg) numvec = arg;
else numvec = dibp->vnum;
if (vec == 0) fprintf (st, "no vector");
else { fprintf (st, "vector=%o", vec);
if (numvec > 1) fprintf (st, "-%o", vec + (4 * (numvec - 1))); }
return SCPE_OK;
}
/* Test for conflict in device addresses */
t_bool dev_conflict (uint32 nba, DIB *curr)
t_bool dev_conflict (DIB *curr)
{
uint32 i, end;
DEVICE *dptr;
DIB *dibp;
end = nba + curr -> lnt - 1; /* get end */
for (i = 0; dibp = dib_tab[i]; i++) { /* loop thru dev */
if (!dibp -> enb || (dibp == curr)) continue; /* skip disabled */
if (((nba >= dibp -> ba) &&
(nba < (dibp -> ba + dibp -> lnt))) ||
((end >= dibp -> ba) &&
(end < (dibp -> ba + dibp -> lnt)))) {
printf ("Device address conflict at %07o\n", dibp -> ba);
end = curr->ba + curr->lnt - 1; /* get end */
for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if ((dibp == NULL) || (dibp == curr) ||
(dptr->flags & DEV_DIS)) continue;
if (((curr->ba >= dibp->ba) && /* overlap start? */
(curr->ba < (dibp->ba + dibp->lnt))) ||
((end >= dibp->ba) && /* overlap end? */
(end < (dibp->ba + dibp->lnt)))) {
printf ("Device %s address conflict at %08o\n", dptr->name, dibp->ba);
if (sim_log) fprintf (sim_log,
"Device number conflict at %07o\n", dibp -> ba);
"Device %s address conflict at %08o\n", dptr->name, dibp->ba);
return TRUE; } }
return FALSE;
}
/* Build interrupt tables */
void build_int_vec (int32 vloc, int32 ivec, int32 (*iack)(void) )
{
if (iack != NULL) int_ack[vloc] = iack;
else int_vec[vloc] = ivec;
return;
}
/* Build dib_tab from device list */
t_bool build_dib_tab (void)
{
int32 i, j, k;
DEVICE *dptr;
DIB *dibp;
for (i = 0; i < 32; i++) { /* clear intr tables */
int_vec[i] = 0;
int_ack[i] = NULL; }
for (i = j = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
dibp = (DIB *) dptr->ctxt; /* get DIB */
if (dibp && !(dptr->flags & DEV_DIS)) { /* defined, enabled? */
if (dibp->vnum > VEC_DEVMAX) return SCPE_IERR;
for (k = 0; k < dibp->vnum; k++) /* loop thru vec */
build_int_vec (dibp->vloc + k, /* add vector */
dibp->vec + (k * 4), dibp->ack[k]);
if (dibp->lnt != 0) { /* I/O addresses? */
dib_tab[j++] = dibp; /* add DIB to dib_tab */
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
} /* end if enabled */
} /* end for */
for (i = 0; (dibp = std_dib[i]) != NULL; i++) { /* loop thru std */
dib_tab[j++] = dibp; /* add to dib_tab */
if (j >= DIB_MAX) return SCPE_IERR; } /* too many? */
dib_tab[j] = NULL; /* end with NULL */
for (i = 0; (dibp = dib_tab[i]) != NULL; i++) { /* test built dib_tab */
if (dev_conflict (dibp)) return SCPE_STOP; } /* for conflicts */
return SCPE_OK;
}
/* Show dib_tab */
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc)
{
int32 i, j, done = 0;
DEVICE *dptr;
DIB *dibt;
build_dib_tab (); /* build table */
while (done == 0) { /* sort ascending */
done = 1; /* assume done */
for (i = 0; dib_tab[i + 1] != NULL; i++) { /* check table */
if (dib_tab[i]->ba > dib_tab[i + 1]->ba) { /* out of order? */
dibt = dib_tab[i]; /* interchange */
dib_tab[i] = dib_tab[i + 1];
dib_tab[i + 1] = dibt;
done = 0; } } /* not done */
} /* end while */
for (i = 0; dib_tab[i] != NULL; i++) { /* print table */
for (j = 0, dptr = NULL; sim_devices[j] != NULL; j++) {
if (((DIB*) sim_devices[j]->ctxt) == dib_tab[i]) {
dptr = sim_devices[j];
break; } }
fprintf (st, "%07o - %07o\t%s\n", dib_tab[i]->ba,
dib_tab[i]->ba + dib_tab[i]->lnt - 1,
dptr? dptr->name: "CPU");
}
return SCPE_OK;
}
/* Stub auto-configure */
t_stat auto_config (uint32 rank, uint32 num)
{
return SCPE_OK;
}

46
PDP10/pdp10_lp20.c
View File

@@ -25,6 +25,9 @@
lp20 line printer
29-Sep-02 RMS Added variable vector support
Modified to use common Unibus routines
New data structures
30-May-02 RMS Widened POS to 32b
06-Jan-02 RMS Added enable/disable support
30-Nov-01 RMS Added extended SET/SHOW support
@@ -114,8 +117,6 @@
/* LPBA (765404) */
#define XBA_MBZ 0400000 /* addr<17> must be 0 */
/* LPBC (765506) */
#define BC_MASK 0007777 /* <15:12> MBZ */
@@ -134,8 +135,10 @@
extern d10 *M; /* main memory */
extern int32 int_req;
extern int32 int_vec[32];
extern int32 ubcs[UBANUM]; /* UBA csr */
extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* UBA map */
int32 lpcsa = 0; /* control/status A */
int32 lpcsb = 0; /* control/status B */
int32 lpba = 0; /* bus address */
@@ -153,8 +156,10 @@ int32 lp20_stopioe = 0; /* stop on error */
int16 txram[TX_SIZE] = { 0 }; /* translation RAM */
int16 davfu[DV_SIZE] = { 0 }; /* DAVFU */
DEVICE lp20_dev;
t_stat lp20_rd (int32 *data, int32 pa, int32 access);
t_stat lp20_wr (int32 data, int32 pa, int32 access);
int32 lp20_inta (void);
t_stat lp20_svc (UNIT *uptr);
t_stat lp20_reset (DEVICE *dptr);
t_stat lp20_attach (UNIT *uptr, char *ptr);
@@ -172,7 +177,8 @@ void update_lpcs (int32 flg);
lp20_reg LPT register list
*/
DIB lp20_dib = { 1, IOBA_LP20, IOLN_LP20, &lp20_rd, &lp20_wr };
DIB lp20_dib = { IOBA_LP20, IOLN_LP20, &lp20_rd, &lp20_wr,
1, IVCL (LP20), VEC_LP20, { &lp20_inta } };
UNIT lp20_unit = {
UDATA (&lp20_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
@@ -200,23 +206,24 @@ REG lp20_reg[] = {
{ FLDATA (STOP_IOE, lp20_stopioe, 0) },
{ BRDATA (TXRAM, txram, 8, 12, TX_SIZE) },
{ BRDATA (DAVFU, davfu, 8, 12, DV_SIZE) },
{ ORDATA (DEVADDR, lp20_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, lp20_dib.vec, 16), REG_HRO },
{ NULL } };
MTAB lp20_mod[] = {
{ UNIT_DUMMY, 0, NULL, "VFUCLEAR", &lp20_clear_vfu },
{ MTAB_XTD|MTAB_VDV, 004, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, &lp20_dib },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
&set_enbdis, NULL, &lp20_dib },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
&set_enbdis, NULL, &lp20_dib },
&set_addr, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
{ 0 } };
DEVICE lp20_dev = {
"LP20", &lp20_unit, lp20_reg, lp20_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &lp20_reset,
NULL, &lp20_attach, &lp20_detach };
NULL, &lp20_attach, &lp20_detach,
&lp20_dib, DEV_DISABLE | DEV_UBUS };
/* Line printer routines
@@ -338,11 +345,12 @@ return SCPE_OK;
t_stat lp20_svc (UNIT *uptr)
{
int32 fnc, i, tbc, vpn, temp, txst, wd10;
int32 fnc, i, tbc, temp, txst;
int32 dvld = -2; /* must be even */
int32 err = 0;
uint16 wd10;
t_bool cont;
a10 ba, pa10;
a10 ba;
static const uint32 txcase[32] = {
TX_CHR, TX_RAM, TX_CHR, TX_DVU, TX_RAM, TX_RAM, TX_DVU, TX_DVU,
@@ -362,20 +370,10 @@ if ((fnc == FNC_PR) && (dvlnt == 0)) {
return SCPE_OK; }
for (i = 0, cont = TRUE; (i < tbc) && cont; ba++, i++) {
vpn = PAG_GETVPN (ba >> 2); /* get PDP-10 page number */
if ((vpn >= UMAP_MEMSIZE) || (ba & XBA_MBZ) ||
((ubmap[1][vpn] & UMAP_VLD) == 0)) { /* invalid map? */
if (Map_ReadW (ba, 2, &wd10, MAP)) { /* get word, err? */
lpcsb = lpcsb | CSB_MTE; /* set NXM error */
ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
update_lpcs (CSA_ERR); /* set done */
break; }
pa10 = (ubmap[1][vpn] + PAG_GETOFF (ba >> 2)) & PAMASK;
if (MEM_ADDR_NXM (pa10)) { /* nxm? */
lpcsb = lpcsb | CSB_MTE; /* set NXM error */
ubcs[1] = ubcs[1] | UBCS_TMO; /* UBA times out */
update_lpcs (CSA_ERR); /* set done */
break; }
wd10 = (int32) ((M[pa10] >> ((ba & 2)? 0: 18)) & 0177777);
lpcbuf = (wd10 >> ((ba & 1)? 8: 0)) & 0377; /* get character */
lpcsum = (lpcsum + lpcbuf) & 0377; /* add into checksum */
switch (fnc) { /* switch on function */
@@ -442,7 +440,7 @@ if (lpbc) update_lpcs (CSA_MBZ); /* intr, but not done */
else update_lpcs (CSA_DONE); /* intr and done */
if ((fnc == FNC_PR) && ferror (lp20_unit.fileref)) {
perror ("LP I/O error");
clearerr (uptr -> fileref);
clearerr (uptr->fileref);
return SCPE_IOERR; }
return SCPE_OK;
}
@@ -547,7 +545,7 @@ return;
int32 lp20_inta (void)
{
lp20_irq = 0; /* clear int req */
return VEC_LP20;
return lp20_dib.vec;
}
t_stat lp20_reset (DEVICE *dptr)

54
PDP10/pdp10_mdfp.c
View File

@@ -620,18 +620,18 @@ void funpack (d10 h, d10 l, UFP *r, t_bool sgn)
{
d10 fphi, fplo;
r -> sign = GET_FPSIGN (h);
r -> exp = GET_FPEXP (h);
r->sign = GET_FPSIGN (h);
r->exp = GET_FPEXP (h);
fphi = GET_FPHI (h);
fplo = GET_FPLO (l);
r -> fhi = (fphi << FP_V_UFHI) | (fplo << FP_V_UFLO);
r -> flo = 0;
if (r -> sign) {
r -> exp = r -> exp ^ FP_M_EXP;
if (sgn) r -> fhi = r -> fhi | FP_UCRY; /* ext sign */
else { if (r -> fhi) r -> fhi = UNEG (r -> fhi) & FP_UFRAC;
else { r -> exp = r -> exp + 1;
r -> fhi = FP_UNORM; } } }
r->fhi = (fphi << FP_V_UFHI) | (fplo << FP_V_UFLO);
r->flo = 0;
if (r->sign) {
r->exp = r->exp ^ FP_M_EXP;
if (sgn) r->fhi = r->fhi | FP_UCRY; /* ext sign */
else { if (r->fhi) r->fhi = UNEG (r->fhi) & FP_UFRAC;
else { r->exp = r->exp + 1;
r->fhi = FP_UNORM; } } }
return;
}
@@ -645,20 +645,20 @@ static t_uint64 normmask[6] = {
0x7FFF800000000000, 0x7FFFFFFF80000000, 0x7FFFFFFFFFFFFFFF };
static int32 normtab[7] = { 1, 2, 4, 8, 16, 32, 63 };
if ((a -> fhi | a -> flo) == 0) { /* if fraction = 0 */
a -> sign = a -> exp = 0; /* result is 0 */
if ((a->fhi | a->flo) == 0) { /* if fraction = 0 */
a->sign = a->exp = 0; /* result is 0 */
return; }
while ((a -> fhi & FP_UNORM) == 0) { /* normalized? */
while ((a->fhi & FP_UNORM) == 0) { /* normalized? */
for (i = 0; i < 6; i++) {
if (a -> fhi & normmask[i]) break; }
a -> fhi = (a -> fhi << normtab[i]) | (a -> flo >> (64 - normtab[i]));
a -> flo = a -> flo << normtab[i];
a -> exp = a -> exp - normtab[i]; }
if (a->fhi & normmask[i]) break; }
a->fhi = (a->fhi << normtab[i]) | (a->flo >> (64 - normtab[i]));
a->flo = a->flo << normtab[i];
a->exp = a->exp - normtab[i]; }
if (rnd) { /* rounding? */
a -> fhi = a -> fhi + rnd; /* add round const */
if (a -> fhi & FP_UCRY) { /* if carry out, */
a -> fhi = a -> fhi >> 1; /* renormalize */
a -> exp = a -> exp + 1; } }
a->fhi = a->fhi + rnd; /* add round const */
if (a->fhi & FP_UCRY) { /* if carry out, */
a->fhi = a->fhi >> 1; /* renormalize */
a->exp = a->exp + 1; } }
return;
}
@@ -668,13 +668,13 @@ d10 fpack (UFP *r, d10 *lo, t_bool fdvneg)
{
d10 val[2];
if (r -> exp < 0) SETF (F_AOV | F_FOV | F_FXU | F_T1);
else if (r -> exp > FP_M_EXP) SETF (F_AOV | F_FOV | F_T1);
val[0] = (((((d10) r -> exp) & FP_M_EXP) << FP_V_EXP) |
((r -> fhi & FP_UFHI) >> FP_V_UFHI)) & DMASK;
if (lo) val[1] = ((r -> fhi & FP_UFLO) >> FP_V_UFLO) & MMASK;
if (r->exp < 0) SETF (F_AOV | F_FOV | F_FXU | F_T1);
else if (r->exp > FP_M_EXP) SETF (F_AOV | F_FOV | F_T1);
val[0] = (((((d10) r->exp) & FP_M_EXP) << FP_V_EXP) |
((r->fhi & FP_UFHI) >> FP_V_UFHI)) & DMASK;
if (lo) val[1] = ((r->fhi & FP_UFLO) >> FP_V_UFLO) & MMASK;
else val[1] = 0;
if (r -> sign) { /* negate? */
if (r->sign) { /* negate? */
if (fdvneg) { /* fdvr special? */
val[1] = ~val[1] & MMASK; /* 1's comp */
val[0] = ~val[0] & DMASK; }

3
PDP10/pdp10_pag.c
View File

@@ -142,7 +142,8 @@ DEVICE pag_dev = {
"PAG", pag_unit, pag_reg, NULL,
2, 8, PTBL_ASIZE, 1, 8, 32,
&pag_ex, &pag_dep, &pag_reset,
NULL, NULL, NULL };
NULL, NULL, NULL,
NULL, 0 };
/* Memory read and write routines

284
PDP10/pdp10_pt.c
View File

@@ -1,4 +1,4 @@
/* pdp10_pt.c: PDP-10 Unibus paper tape reader/punch simulator
/* pdp10_pt.c: PDP-10 paper tape reader/punch simulator
Copyright (c) 1993-2002, Robert M Supnik
@@ -26,283 +26,13 @@
ptr paper tape reader
ptp paper tape punch
30-May-02 RMS Widened POS to 32b
06-Jan-02 RMS Revised enable/disable support
29-Nov-01 RMS Added read only unit support
07-Sep-01 RMS Revised disable mechanism
12-Sep-02 RMS Consolidated source
*/
#define VM_PDP10 1
#define PT_RDX 8
#define PT_DIS DEV_DIS
#include "pdp10_defs.h"
#define PTRCSR_IMP (CSR_ERR+CSR_BUSY+CSR_DONE+CSR_IE) /* paper tape reader */
#define PTRCSR_RW (CSR_IE)
#define PTPCSR_IMP (CSR_ERR + CSR_DONE + CSR_IE) /* paper tape punch */
#define PTPCSR_RW (CSR_IE)
extern int32 int_req;
int32 ptr_csr = 0; /* control/status */
int32 ptr_stopioe = 0; /* stop on error */
int32 ptp_csr = 0; /* control/status */
int32 ptp_stopioe = 0; /* stop on error */
t_stat pt_rd (int32 *data, int32 PA, int32 access);
t_stat pt_wr (int32 data, int32 PA, int32 access);
t_stat ptr_svc (UNIT *uptr);
t_stat ptp_svc (UNIT *uptr);
t_stat ptr_reset (DEVICE *dptr);
t_stat ptp_reset (DEVICE *dptr);
t_stat ptr_attach (UNIT *uptr, char *ptr);
t_stat ptr_detach (UNIT *uptr);
t_stat ptp_attach (UNIT *uptr, char *ptr);
t_stat ptp_detach (UNIT *uptr);
/* PTR data structures
ptr_dev PTR device descriptor
ptr_unit PTR unit descriptor
ptr_reg PTR register list
*/
DIB pt_dib = { 0, IOBA_PT, IOLN_PT, &pt_rd, &pt_wr };
UNIT ptr_unit = {
UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),
SERIAL_IN_WAIT };
REG ptr_reg[] = {
{ ORDATA (CSR, ptr_csr, 16) },
{ ORDATA (BUF, ptr_unit.buf, 8) },
{ FLDATA (INT, int_req, INT_V_PTR) },
{ FLDATA (ERR, ptr_csr, CSR_V_ERR) },
{ FLDATA (BUSY, ptr_csr, CSR_V_BUSY) },
{ FLDATA (DONE, ptr_csr, CSR_V_DONE) },
{ FLDATA (IE, ptr_csr, CSR_V_IE) },
{ DRDATA (POS, ptr_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) },
{ FLDATA (*DEVENB, pt_dib.enb, 0), REG_HRO },
{ NULL } };
MTAB ptr_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, &pt_dib },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
&set_enbdis, NULL, &pt_dib },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
&set_enbdis, NULL, &pt_dib },
{ 0 } };
DEVICE ptr_dev = {
"PTR", &ptr_unit, ptr_reg, ptr_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptr_reset,
NULL, &ptr_attach, &ptr_detach };
/* PTP data structures
ptp_dev PTP device descriptor
ptp_unit PTP unit descriptor
ptp_reg PTP register list
*/
UNIT ptp_unit = {
UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG ptp_reg[] = {
{ ORDATA (BUF, ptp_unit.buf, 8) },
{ ORDATA (CSR, ptp_csr, 16) },
{ FLDATA (INT, int_req, INT_V_PTP) },
{ FLDATA (ERR, ptp_csr, CSR_V_ERR) },
{ FLDATA (DONE, ptp_csr, CSR_V_DONE) },
{ FLDATA (IE, ptp_csr, CSR_V_IE) },
{ DRDATA (POS, ptp_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, ptp_stopioe, 0) },
{ FLDATA (*DEVENB, pt_dib.enb, 0), REG_HRO },
{ NULL } };
MTAB ptp_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, &pt_dib },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
&set_enbdis, NULL, &pt_dib },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
&set_enbdis, NULL, &pt_dib },
{ 0 } };
DEVICE ptp_dev = {
"PTP", &ptp_unit, ptp_reg, ptp_mod,
1, 10, 31, 1, 8, 8,
NULL, NULL, &ptp_reset,
NULL, &ptp_attach, &ptp_detach };
/* Standard I/O dispatch routine, I/O addresses 17777550-17777557
17777550 ptr CSR
17777552 ptr buffer
17777554 ptp CSR
17777556 ptp buffer
Note: Word access routines filter out odd addresses. Thus,
an odd address implies an (odd) byte access.
*/
t_stat pt_rd (int32 *data, int32 PA, int32 access)
{
switch ((PA >> 1) & 03) { /* decode PA<2:1> */
case 0: /* ptr csr */
*data = ptr_csr & PTRCSR_IMP;
return SCPE_OK;
case 1: /* ptr buf */
ptr_csr = ptr_csr & ~CSR_DONE;
int_req = int_req & ~INT_PTR;
*data = ptr_unit.buf & 0377;
return SCPE_OK;
case 2: /* ptp csr */
*data = ptp_csr & PTPCSR_IMP;
return SCPE_OK;
case 3: /* ptp buf */
*data = ptp_unit.buf;
return SCPE_OK; }
return SCPE_NXM; /* can't get here */
}
t_stat pt_wr (int32 data, int32 PA, int32 access)
{
switch ((PA >> 1) & 03) { /* decode PA<2:1> */
case 0: /* ptr csr */
if (PA & 1) return SCPE_OK;
if ((data & CSR_IE) == 0) int_req = int_req & ~INT_PTR;
else if (((ptr_csr & CSR_IE) == 0) && (ptr_csr & (CSR_ERR | CSR_DONE)))
int_req = int_req | INT_PTR;
if (data & CSR_GO) {
ptr_csr = (ptr_csr & ~CSR_DONE) | CSR_BUSY;
int_req = int_req & ~INT_PTR;
if (ptr_unit.flags & UNIT_ATT) /* data to read? */
sim_activate (&ptr_unit, ptr_unit.wait);
else sim_activate (&ptr_unit, 0); } /* error if not */
ptr_csr = (ptr_csr & ~PTRCSR_RW) | (data & PTRCSR_RW);
return SCPE_OK;
case 1: /* ptr buf */
return SCPE_OK;
case 2: /* ptp csr */
if (PA & 1) return SCPE_OK;
if ((data & CSR_IE) == 0) int_req = int_req & ~INT_PTP;
else if (((ptp_csr & CSR_IE) == 0) && (ptp_csr & (CSR_ERR | CSR_DONE)))
int_req = int_req | INT_PTP;
ptp_csr = (ptp_csr & ~PTPCSR_RW) | (data & PTPCSR_RW);
return SCPE_OK;
case 3: /* ptp buf */
if ((PA & 1) == 0) ptp_unit.buf = data & 0377;
ptp_csr = ptp_csr & ~CSR_DONE;
int_req = int_req & ~INT_PTP;
if (ptp_unit.flags & UNIT_ATT) /* file to write? */
sim_activate (&ptp_unit, ptp_unit.wait);
else sim_activate (&ptp_unit, 0); /* error if not */
return SCPE_OK; } /* end switch PA */
return SCPE_NXM; /* can't get here */
}
/* Paper tape reader routines
ptr_svc process event (character ready)
ptr_reset process reset
ptr_attach process attach
ptr_detach process detach
*/
t_stat ptr_svc (UNIT *uptr)
{
int32 temp;
ptr_csr = (ptr_csr | CSR_ERR) & ~CSR_BUSY;
if (ptr_csr & CSR_IE) int_req = int_req | INT_PTR;
if ((ptr_unit.flags & UNIT_ATT) == 0)
return IORETURN (ptr_stopioe, SCPE_UNATT);
if ((temp = getc (ptr_unit.fileref)) == EOF) {
if (feof (ptr_unit.fileref)) {
if (ptr_stopioe) printf ("PTR end of file\n");
else return SCPE_OK; }
else perror ("PTR I/O error");
clearerr (ptr_unit.fileref);
return SCPE_IOERR; }
ptr_csr = (ptr_csr | CSR_DONE) & ~CSR_ERR;
ptr_unit.buf = temp & 0377;
ptr_unit.pos = ptr_unit.pos + 1;
return SCPE_OK;
}
t_stat ptr_reset (DEVICE *dptr)
{
ptr_unit.buf = 0;
ptr_csr = 0;
if ((ptr_unit.flags & UNIT_ATT) == 0) ptr_csr = ptr_csr | CSR_ERR;
int_req = int_req & ~INT_PTR;
sim_cancel (&ptr_unit);
return SCPE_OK;
}
t_stat ptr_attach (UNIT *uptr, char *cptr)
{
t_stat reason;
reason = attach_unit (uptr, cptr);
if ((ptr_unit.flags & UNIT_ATT) == 0) ptr_csr = ptr_csr | CSR_ERR;
else ptr_csr = ptr_csr & ~CSR_ERR;
return reason;
}
t_stat ptr_detach (UNIT *uptr)
{
ptr_csr = ptr_csr | CSR_ERR;
return detach_unit (uptr);
}
/* Paper tape punch routines
ptp_svc process event (character punched)
ptp_reset process reset
ptp_attach process attach
ptp_detach process detach
*/
t_stat ptp_svc (UNIT *uptr)
{
ptp_csr = ptp_csr | CSR_ERR | CSR_DONE;
if (ptp_csr & CSR_IE) int_req = int_req | INT_PTP;
if ((ptp_unit.flags & UNIT_ATT) == 0)
return IORETURN (ptp_stopioe, SCPE_UNATT);
if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) {
perror ("PTP I/O error");
clearerr (ptp_unit.fileref);
return SCPE_IOERR; }
ptp_csr = ptp_csr & ~CSR_ERR;
ptp_unit.pos = ptp_unit.pos + 1;
return SCPE_OK;
}
t_stat ptp_reset (DEVICE *dptr)
{
ptp_unit.buf = 0;
ptp_csr = CSR_DONE;
if ((ptp_unit.flags & UNIT_ATT) == 0) ptp_csr = ptp_csr | CSR_ERR;
int_req = int_req & ~INT_PTP;
sim_cancel (&ptp_unit); /* deactivate unit */
return SCPE_OK;
}
t_stat ptp_attach (UNIT *uptr, char *cptr)
{
t_stat reason;
reason = attach_unit (uptr, cptr);
if ((ptp_unit.flags & UNIT_ATT) == 0) ptp_csr = ptp_csr | CSR_ERR;
else ptp_csr = ptp_csr & ~CSR_ERR;
return reason;
}
t_stat ptp_detach (UNIT *uptr)
{
ptp_csr = ptp_csr | CSR_ERR;
return detach_unit (uptr);
}
extern int32 int_vec[32];
#include "dec_pt.h"

104
PDP10/pdp10_rp.c
View File

@@ -25,6 +25,8 @@
rp RH/RP/RM moving head disks
29-Sep-02 RMS Added variable vector support
New data structures
30-Nov-01 RMS Added read only unit, extended SET/SHOW support support
24-Nov-01 RMS Changed RPER, RPDS, FNC, FLG to arrays
23-Oct-01 RMS Fixed bug in error interrupts
@@ -73,11 +75,10 @@
#define UNIT_V_DTYPE (UNIT_V_UF + 1) /* disk type */
#define UNIT_M_DTYPE 7
#define UNIT_V_AUTO (UNIT_V_UF + 4) /* autosize */
#define UNIT_V_DUMMY (UNIT_V_UF + 5) /* dummy flag */
#define UNIT_WLK (1 << UNIT_V_WLK)
#define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE)
#define UNIT_AUTO (1 << UNIT_V_AUTO)
#define UNIT_W_UF 6 /* user flags width */
#define UNIT_V_DUMMY (UNIT_V_UF + UNIT_W_UF) /* dummy flag */
#define UNIT_DUMMY (1 << UNIT_V_DUMMY)
#define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE)
#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */
@@ -313,9 +314,11 @@ struct drvtyp drv_tab[] = {
extern d10 *M; /* memory */
extern int32 int_req;
extern int32 int_vec[32];
extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* Unibus maps */
extern int32 ubcs[UBANUM];
extern UNIT cpu_unit;
int32 rpcs1 = 0; /* control/status 1 */
int32 rpwc = 0; /* word count */
int32 rpba = 0; /* bus address */
@@ -341,9 +344,10 @@ int reg_in_drive[32] = {
t_stat rp_rd (int32 *data, int32 PA, int32 access);
t_stat rp_wr (int32 data, int32 PA, int32 access);
int32 rp_inta (void);
t_stat rp_svc (UNIT *uptr);
t_stat rp_reset (DEVICE *dptr);
t_stat rp_boot (int32 unitno);
t_stat rp_boot (int32 unitno, DEVICE *dptr);
t_stat rp_attach (UNIT *uptr, char *cptr);
t_stat rp_detach (UNIT *uptr);
void update_rpcs (int32 flags, int32 drv);
@@ -358,7 +362,8 @@ t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
rp_mod RP modifier list
*/
DIB rp_dib = { 1, IOBA_RP, IOLN_RP, &rp_rd, &rp_wr };
DIB rp_dib = { IOBA_RP, IOLN_RP, &rp_rd, &rp_wr,
1, IVCL (RP), VEC_RP, { &rp_inta } };
UNIT rp_unit[] = {
{ UDATA (&rp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
@@ -402,8 +407,6 @@ REG rp_reg[] = {
{ DRDATA (STIME, rp_swait, 24), REG_NZ + PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), REG_NZ + PV_LEFT },
{ URDATA (FNC, rp_unit[0].FUNC, 8, 5, 0, RP_NUMDR, REG_HRO) },
{ URDATA (FLG, rp_unit[0].flags, 8, UNIT_W_UF, UNIT_V_UF - 1,
RP_NUMDR, REG_HRO) },
{ URDATA (CAPAC, rp_unit[0].capac, 10, 31, 0,
RP_NUMDR, PV_LEFT | REG_HRO) },
{ FLDATA (STOP_IOE, rp_stopioe, 0) },
@@ -451,14 +454,17 @@ MTAB rp_mod[] = {
{ (UNIT_AUTO+UNIT_DTYPE), (RP07_DTYPE << UNIT_V_DTYPE),
NULL, "RP07", &rp_set_size },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, &rp_dib },
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 } };
DEVICE rp_dev = {
"RP", rp_unit, rp_reg, rp_mod,
RP_NUMDR, 8, 30, 1, 8, 36,
NULL, NULL, &rp_reset,
&rp_boot, &rp_attach, &rp_detach };
&rp_boot, &rp_attach, &rp_detach,
&rp_dib, DEV_UBUS };
/* I/O dispatch routines, I/O addresses 17776700 - 17776776 */
@@ -577,17 +583,17 @@ case 000: /* RPCS1 */
if ((data & CS1_DONE) && (data & CS1_IE)) /* to DONE+IE? */
rpiff = 1; /* set CSTB INTR */
rpcs1 = (rpcs1 & ~CS1_IE) | (data & CS1_IE);
if (uptr -> flags & UNIT_DIS) { /* nx disk? */
if (uptr->flags & UNIT_DIS) { /* nx disk? */
rpcs2 = rpcs2 | CS2_NED; /* set error flag */
cs1f = CS1_SC; } /* req interrupt */
else if (sim_is_active (uptr))
rper1[drv] = rper1[drv] | ER1_RMR; /* won't write */
else if (data & CS1_GO) { /* start op */
uptr -> FUNC = GET_FNC (data); /* set func */
if ((uptr -> FUNC >= FNC_XFER) && /* data xfer and */
uptr->FUNC = GET_FNC (data); /* set func */
if ((uptr->FUNC >= FNC_XFER) && /* data xfer and */
((rpcs1 & CS1_DONE) == 0)) /* ~rdy? PGE */
rpcs2 = rpcs2 | CS2_PGE;
else rp_go (drv, uptr -> FUNC); } }
else rp_go (drv, uptr->FUNC); } }
break;
case 001: /* RPWC */
if (access == WRITEB) data = (PA & 1)?
@@ -669,7 +675,7 @@ int32 dc, dtype, t;
UNIT *uptr;
uptr = rp_dev.units + drv; /* get unit */
if (uptr -> flags & UNIT_DIS) { /* nx unit? */
if (uptr->flags & UNIT_DIS) { /* nx unit? */
rpcs2 = rpcs2 | CS2_NED; /* set error flag */
update_rpcs (CS1_SC, drv); /* request intr */
return; }
@@ -678,7 +684,7 @@ if ((fnc != FNC_DCLR) && (rpds[drv] & DS_ERR)) { /* err & ~clear? */
rpds[drv] = rpds[drv] | DS_ATA; /* set attention */
update_rpcs (CS1_SC, drv); /* request intr */
return; }
dtype = GET_DTYPE (uptr -> flags); /* get drive type */
dtype = GET_DTYPE (uptr->flags); /* get drive type */
rpds[drv] = rpds[drv] & ~DS_ATA; /* clear attention */
dc = rpdc; /* assume seek, sch */
@@ -700,7 +706,7 @@ case FNC_PACK: /* pack acknowledge */
case FNC_OFFSET: /* offset mode */
case FNC_RETURN:
if ((uptr -> flags & UNIT_ATT) == 0) { /* not attached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
rper1[drv] = rper1[drv] | ER1_UNS; /* unsafe */
break; }
rpds[drv] = (rpds[drv] & ~DS_RDY) | DS_PIP; /* set positioning */
@@ -712,7 +718,7 @@ case FNC_RECAL: /* recalibrate */
dc = 0; /* seek to 0 */
case FNC_SEEK: /* seek */
case FNC_SEARCH: /* search */
if ((uptr -> flags & UNIT_ATT) == 0) { /* not attached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
rper1[drv] = rper1[drv] | ER1_UNS; /* unsafe */
break; }
if ((GET_CY (dc) >= drv_tab[dtype].cyl) || /* bad cylinder */
@@ -721,10 +727,10 @@ case FNC_SEARCH: /* search */
rper1[drv] = rper1[drv] | ER1_IAE;
break; }
rpds[drv] = (rpds[drv] & ~DS_RDY) | DS_PIP; /* set positioning */
t = abs (dc - uptr -> CYL); /* cyl diff */
t = abs (dc - uptr->CYL); /* cyl diff */
if (t == 0) t = 1; /* min time */
sim_activate (uptr, rp_swait * t); /* schedule */
uptr -> CYL = dc; /* save cylinder */
uptr->CYL = dc; /* save cylinder */
return;
case FNC_WRITEH: /* write headers */
@@ -732,7 +738,7 @@ case FNC_WRITE: /* write */
case FNC_WCHK: /* write check */
case FNC_READ: /* read */
case FNC_READH: /* read headers */
if ((uptr -> flags & UNIT_ATT) == 0) { /* not attached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
rper1[drv] = rper1[drv] | ER1_UNS; /* unsafe */
break; }
rpcs2 = rpcs2 & ~CS2_ERR; /* clear errors */
@@ -743,8 +749,8 @@ case FNC_READH: /* read headers */
rper1[drv] = rper1[drv] | ER1_IAE;
break; }
rpds[drv] = rpds[drv] & ~DS_RDY; /* clear drive rdy */
sim_activate (uptr, rp_rwait + (rp_swait * abs (dc - uptr -> CYL)));
uptr -> CYL = dc; /* save cylinder */
sim_activate (uptr, rp_rwait + (rp_swait * abs (dc - uptr->CYL)));
uptr->CYL = dc; /* save cylinder */
return;
default: /* all others */
@@ -770,11 +776,11 @@ a10 pa10, mpa10;
int32 wc10, twc10, awc10, fc10;
static d10 dbuf[RP_MAXFR];
dtype = GET_DTYPE (uptr -> flags); /* get drive type */
dtype = GET_DTYPE (uptr->flags); /* get drive type */
drv = uptr - rp_dev.units; /* get drv number */
rpds[drv] = (rpds[drv] & ~DS_PIP) | DS_RDY; /* change drive status */
switch (uptr -> FUNC) { /* case on function */
switch (uptr->FUNC) { /* case on function */
case FNC_OFFSET: /* offset */
rpds[drv] = rpds[drv] | DS_OF | DS_ATA; /* set offset, attention */
update_rpcs (CS1_SC, drv);
@@ -804,7 +810,7 @@ case FNC_SEEK: /* seek */
#define XBA_MBZ 0000003 /* addr<1:0> must be 0 */
case FNC_WRITE: /* write */
if (uptr -> flags & UNIT_WPRT) { /* write locked? */
if (uptr->flags & UNIT_WPRT) { /* write locked? */
rper1[drv] = rper1[drv] | ER1_WLE; /* set drive error */
update_rpcs (CS1_DONE | CS1_TRE, drv); /* set done, err */
break; }
@@ -819,8 +825,8 @@ case FNC_READH: /* read headers */
if (wc10 > (drv_tab[dtype].size - da))
wc10 = drv_tab[dtype].size - da; }
err = fseek (uptr -> fileref, da * sizeof (d10), SEEK_SET);
if (uptr -> FUNC == FNC_WRITE) { /* write? */
err = fseek (uptr->fileref, da * sizeof (d10), SEEK_SET);
if (uptr->FUNC == FNC_WRITE) { /* write? */
for (twc10 = 0; twc10 < wc10; twc10++) {
pa10 = ba >> 2;
vpn = PAG_GETVPN (pa10); /* map addr */
@@ -836,15 +842,15 @@ case FNC_READH: /* read headers */
break; }
dbuf[twc10] = M[mpa10]; /* write to disk */
if ((rpcs2 & CS2_UAI) == 0) ba = ba + 4; }
if (fc10 = twc10 & (RP_NUMWD - 1)) { /* fill? */
if (fc10 = twc10 & (RP_NUMWD - 1)) { /* fill? */
fc10 = RP_NUMWD - fc10;
for (i = 0; i < fc10; i++) dbuf[twc10 + i] = 0; }
fxwrite (dbuf, sizeof (d10), twc10 + fc10, uptr -> fileref);
err = ferror (uptr -> fileref);
fxwrite (dbuf, sizeof (d10), twc10 + fc10, uptr->fileref);
err = ferror (uptr->fileref);
} /* end if */
else { /* read, wchk */
awc10 = fxread (dbuf, sizeof (d10), wc10, uptr -> fileref);
err = ferror (uptr -> fileref);
awc10 = fxread (dbuf, sizeof (d10), wc10, uptr->fileref);
err = ferror (uptr->fileref);
for ( ; awc10 < wc10; awc10++) dbuf[awc10] = 0;
for (twc10 = 0; twc10 < wc10; twc10++) {
pa10 = ba >> 2;
@@ -859,7 +865,7 @@ case FNC_READH: /* read headers */
rpcs2 = rpcs2 | CS2_NEM; /* set error */
ubcs[0] = ubcs[0] | UBCS_TMO; /* UBA times out */
break; }
if (uptr -> FUNC == FNC_READ) M[mpa10] = dbuf[twc10];
if (uptr->FUNC == FNC_READ) M[mpa10] = dbuf[twc10];
else if (M[mpa10] != dbuf[twc10]) {
rpcs2 = rpcs2 | CS2_WCE; /* set error */
break; }
@@ -881,7 +887,7 @@ case FNC_READH: /* read headers */
rper1[drv] = rper1[drv] | ER1_PAR; /* set drive error */
update_rpcs (CS1_DONE | CS1_TRE, drv); /* set done, err */
perror ("RP I/O error");
clearerr (uptr -> fileref);
clearerr (uptr->fileref);
return SCPE_IOERR; }
case FNC_WRITEH: /* write headers stub */
update_rpcs (CS1_DONE, drv); /* set done */
@@ -913,7 +919,7 @@ if (rper1[drv] | rper2 | rper3) rpds[drv] = rpds[drv] | DS_ERR | DS_ATA;
else rpds[drv] = rpds[drv] & ~DS_ERR;
rpcs1 = (rpcs1 & ~(CS1_SC | CS1_MCPE | CS1_MBZ | CS1_DRV)) | CS1_DVA | flag;
rpcs1 = rpcs1 | (uptr -> FUNC << CS1_V_FNC);
rpcs1 = rpcs1 | (uptr->FUNC << CS1_V_FNC);
if (sim_is_active (uptr)) rpcs1 = rpcs1 | CS1_GO;
if (rpcs2 & CS2_ERR) rpcs1 = rpcs1 | CS1_TRE | CS1_SC;
else if (rpcs1 & CS1_TRE) rpcs1 = rpcs1 | CS1_SC;
@@ -952,10 +958,10 @@ int_req = int_req & ~INT_RP; /* clear intr req */
for (i = 0; i < RP_NUMDR; i++) {
uptr = rp_dev.units + i;
sim_cancel (uptr);
uptr -> CYL = uptr -> FUNC = 0;
if (uptr -> flags & UNIT_ATT) rpds[i] = (rpds[i] & DS_VV) |
DS_DPR | DS_RDY | DS_MOL | ((uptr -> flags & UNIT_WPRT)? DS_WRL: 0);
else if (uptr -> flags & UNIT_DIS) rpds[i] = 0;
uptr->CYL = uptr->FUNC = 0;
if (uptr->flags & UNIT_ATT) rpds[i] = (rpds[i] & DS_VV) |
DS_DPR | DS_RDY | DS_MOL | ((uptr->flags & UNIT_WPRT)? DS_WRL: 0);
else if (uptr->flags & UNIT_DIS) rpds[i] = 0;
else rpds[i] = DS_DPR;
rper1[i] = 0; }
return SCPE_OK;
@@ -968,22 +974,22 @@ t_stat rp_attach (UNIT *uptr, char *cptr)
int drv, i, p;
t_stat r;
uptr -> capac = drv_tab[GET_DTYPE (uptr -> flags)].size;
uptr->capac = drv_tab[GET_DTYPE (uptr->flags)].size;
r = attach_unit (uptr, cptr);
if (r != SCPE_OK) return r;
drv = uptr - rp_dev.units; /* get drv number */
rpds[drv] = DS_ATA | DS_MOL | DS_RDY | DS_DPR |
((uptr -> flags & UNIT_WPRT)? DS_WRL: 0);
((uptr->flags & UNIT_WPRT)? DS_WRL: 0);
rper1[drv] = 0;
update_rpcs (CS1_SC, drv);
if ((uptr -> flags & UNIT_AUTO) == 0) return SCPE_OK; /* autosize? */
if (fseek (uptr -> fileref, 0, SEEK_END)) return SCPE_OK;
if ((p = ftell (uptr -> fileref)) == 0) return SCPE_OK;
if ((uptr->flags & UNIT_AUTO) == 0) return SCPE_OK; /* autosize? */
if (fseek (uptr->fileref, 0, SEEK_END)) return SCPE_OK;
if ((p = ftell (uptr->fileref)) == 0) return SCPE_OK;
for (i = 0; drv_tab[i].sect != 0; i++) {
if (p <= (drv_tab[i].size * (int) sizeof (d10))) {
uptr -> flags = (uptr -> flags & ~UNIT_DTYPE) | (i << UNIT_V_DTYPE);
uptr -> capac = drv_tab[i].size;
uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (i << UNIT_V_DTYPE);
uptr->capac = drv_tab[i].size;
return SCPE_OK; } }
return SCPE_OK;
}
@@ -1000,7 +1006,7 @@ rpds[drv] = (rpds[drv] & ~(DS_MOL | DS_RDY | DS_WRL | DS_VV | DS_OF)) |
if (sim_is_active (uptr)) { /* unit active? */
sim_cancel (uptr); /* cancel operation */
rper1[drv] = rper1[drv] | ER1_OPI; /* set drive error */
if (uptr -> FUNC >= FNC_WCHK) /* data transfer? */
if (uptr->FUNC >= FNC_WCHK) /* data transfer? */
rpcs1 = rpcs1 | CS1_DONE | CS1_TRE; } /* set done, err */
update_rpcs (CS1_SC, drv); /* request intr */
return detach_unit (uptr);
@@ -1010,8 +1016,8 @@ return detach_unit (uptr);
t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
{
if (uptr -> flags & UNIT_ATT) return SCPE_ALATT;
uptr -> capac = drv_tab[GET_DTYPE (val)].size;
if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
uptr->capac = drv_tab[GET_DTYPE (val)].size;
return SCPE_OK;
}
@@ -1114,7 +1120,7 @@ static const d10 boot_rom_its[] = {
0254017000000, /* jrst 0(17) ; return */
};
t_stat rp_boot (int32 unitno)
t_stat rp_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
extern a10 saved_PC;

4
PDP10/pdp10_sys.c
View File

@@ -23,6 +23,7 @@
be used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
12-Sep-02 RMS Added RX211 support
22-Apr-02 RMS Removed magtape record length error
17-Sep-01 RMS Removed multiconsole support
25-Aug-01 RMS Enabled DZ11
@@ -41,7 +42,7 @@ extern DEVICE cpu_dev, pag_dev;
extern DEVICE tim_dev, fe_dev, uba_dev;
extern DEVICE ptr_dev, ptp_dev;
extern DEVICE rp_dev, tu_dev;
extern DEVICE dz_dev;
extern DEVICE dz_dev, ry_dev;
extern DEVICE lp20_dev;
extern UNIT cpu_unit;
extern REG cpu_reg[];
@@ -72,6 +73,7 @@ DEVICE *sim_devices[] = {
&uba_dev,
&ptr_dev,
&ptp_dev,
&ry_dev,
&lp20_dev,
&rp_dev,
&tu_dev,

29
PDP10/pdp10_tim.c
View File

@@ -25,6 +25,7 @@
tim timer subsystem
29-Jan-02 RMS New data structures
06-Jan-02 RMS Added enable/disable support
02-Dec-01 RMS Fixed bug in ITS PC sampling (found by Dave Conroy)
31-Aug-01 RMS Changed int64 to t_int64 for Windoze
@@ -55,6 +56,7 @@ d10 quant = 0; /* ITS quantum */
int32 diagflg = 0; /* diagnostics? */
int32 tmxr_poll = TIM_DELAY * DZ_MULT; /* term mux poll */
DEVICE tim_dev;
t_stat tcu_rd (int32 *data, int32 PA, int32 access);
extern t_stat wr_nop (int32 data, int32 PA, int32 access);
t_stat tim_svc (UNIT *uptr);
@@ -72,7 +74,7 @@ extern int32 pi_eval (void);
tim_reg TIM register list
*/
DIB tcu_dib = { 1, IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop };
DIB tcu_dib = { IOBA_TCU, IOLN_TCU, &tcu_rd, &wr_nop, 0 };
UNIT tim_unit = { UDATA (&tim_svc, 0, 0), TIM_DELAY };
@@ -90,18 +92,15 @@ MTAB tim_mod[] = {
{ UNIT_Y2K, 0, "non Y2K OS", "NOY2K", NULL },
{ UNIT_Y2K, UNIT_Y2K, "Y2K OS", "Y2K", NULL },
{ MTAB_XTD|MTAB_VDV, 000, "ADDRESS", NULL,
NULL, &show_addr, &tcu_dib },
{ MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLED",
&set_enbdis, NULL, &tcu_dib },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLED",
&set_enbdis, NULL, &tcu_dib },
NULL, &show_addr, NULL },
{ 0 } };
DEVICE tim_dev = {
"TIM", &tim_unit, tim_reg, tim_mod,
1, 0, 0, 0, 0, 0,
NULL, NULL, &tim_reset,
NULL, NULL, NULL };
NULL, NULL, NULL,
&tcu_dib, DEV_DISABLE | DEV_UBUS };
/* Timer instructions */
@@ -179,21 +178,21 @@ struct tm *tptr;
curtim = time (NULL); /* get time */
tptr = localtime (&curtim); /* decompose */
if (tptr == NULL) return SCPE_NXM; /* Y2K prob? */
if ((tptr -> tm_year > 99) && !(tim_unit.flags & UNIT_Y2K))
tptr -> tm_year = 99;
if ((tptr->tm_year > 99) && !(tim_unit.flags & UNIT_Y2K))
tptr->tm_year = 99;
switch ((PA >> 1) & 03) { /* decode PA<3:1> */
case 0: /* year/month/day */
*data = (((tptr -> tm_year) & 0177) << 9) |
(((tptr -> tm_mon + 1) & 017) << 5) |
((tptr -> tm_mday) & 037);
*data = (((tptr->tm_year) & 0177) << 9) |
(((tptr->tm_mon + 1) & 017) << 5) |
((tptr->tm_mday) & 037);
return SCPE_OK;
case 1: /* hour/minute */
*data = (((tptr -> tm_hour) & 037) << 8) |
((tptr -> tm_min) & 077);
*data = (((tptr->tm_hour) & 037) << 8) |
((tptr->tm_min) & 077);
return SCPE_OK;
case 2: /* second */
*data = (tptr -> tm_sec) & 077;
*data = (tptr->tm_sec) & 077;
return SCPE_OK;
case 3: /* status */
*data = CSR_DONE;

256
PDP10/pdp10_tu.c
View File

@@ -25,6 +25,9 @@
tu RH11/TM03/TU45 magtape
29-Sep-02 RMS Added variable vector support
New data structures
28-Aug-02 RMS Added end of medium support
30-May-02 RMS Widened POS to 32b
22-Apr-02 RMS Changed record length error code
06-Jan-02 RMS Revised enable/disable support
@@ -73,8 +76,9 @@
#define TU_NUMFM 1 /* #formatters */
#define TU_NUMDR 8 /* #drives */
#define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */
#define UNIT_V_PNU (UNIT_V_UF + 1) /* pos not updated */
#define UNIT_WLK (1 << UNIT_V_WLK)
#define UNIT_W_UF 2 /* saved user flags */
#define UNIT_PNU (1 << UNIT_V_PNU)
#define USTAT u3 /* unit status */
#define UDENS u4 /* unit density */
#define UD_UNK 0 /* unknown */
@@ -181,7 +185,7 @@
#define ER_MCP 0000010 /* Mbus cpar err NI */
#define ER_FER 0000020 /* format sel err */
#define ER_MDP 0000040 /* Mbus dpar err NI */
#define ER_VPE 0000100 /* vert parity err NI */
#define ER_VPE 0000100 /* vert parity err */
#define ER_CRC 0000200 /* CRC err NI */
#define ER_NSG 0000400 /* non std gap err NI */
#define ER_FCE 0001000 /* frame count err */
@@ -270,9 +274,11 @@
extern d10 *M; /* memory */
extern int32 int_req;
extern int32 int_vec[32];
extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* Unibus map */
extern int32 ubcs[UBANUM];
extern UNIT cpu_unit;
int32 tucs1 = 0; /* control/status 1 */
int32 tuwc = 0; /* word count */
int32 tuba = 0; /* bus address */
@@ -301,14 +307,17 @@ int den_test[8] = { /* valid densities */
t_stat tu_rd (int32 *data, int32 PA, int32 access);
t_stat tu_wr (int32 data, int32 PA, int32 access);
int32 tu_inta (void);
t_stat tu_svc (UNIT *uptr);
t_stat tu_reset (DEVICE *dptr);
t_stat tu_attach (UNIT *uptr, char *cptr);
t_stat tu_detach (UNIT *uptr);
t_stat tu_boot (int32 unitno);
t_stat tu_boot (int32 unitno, DEVICE *dptr);
void tu_go (int32 drv);
void update_tucs (int32 flag, int32 drv);
t_stat tu_vlock (UNIT *uptr, int32 val, char *cptr, void *desc);
t_bool tu_rdlntf (UNIT *uptr, t_mtrlnt *tbc, int32 *err);
t_bool tu_rdlntr (UNIT *uptr, t_mtrlnt *tbc, int32 *err);
/* TU data structures
@@ -318,7 +327,8 @@ t_stat tu_vlock (UNIT *uptr, int32 val, char *cptr, void *desc);
tu_mod TU modifier list
*/
DIB tu_dib = { 1, IOBA_TU, IOLN_TU, &tu_rd, &tu_wr };
DIB tu_dib = { IOBA_TU, IOLN_TU, &tu_rd, &tu_wr,
1, IVCL (TU), VEC_TU, { &tu_inta } };
UNIT tu_unit[] = {
{ UDATA (&tu_svc, UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE, 0) },
@@ -351,8 +361,6 @@ REG tu_reg[] = {
{ URDATA (UST, tu_unit[0].USTAT, 8, 17, 0, TU_NUMDR, 0) },
{ URDATA (POS, tu_unit[0].pos, 8, 32, 0,
TU_NUMDR, PV_LEFT | REG_RO) },
{ URDATA (FLG, tu_unit[0].flags, 8, UNIT_W_UF, UNIT_V_UF - 1,
TU_NUMDR, REG_HRO) },
{ ORDATA (LOG, tu_log, 8), REG_HIDDEN },
{ NULL } };
@@ -360,14 +368,17 @@ MTAB tu_mod[] = {
{ UNIT_WLK, 0, "write enabled", "WRITEENABLED", &tu_vlock },
{ UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", &tu_vlock },
{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
NULL, &show_addr, &tu_dib },
NULL, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
NULL, &show_vec, NULL },
{ 0 } };
DEVICE tu_dev = {
"TU", tu_unit, tu_reg, tu_mod,
TU_NUMDR, 10, 31, 1, 8, 8,
NULL, NULL, &tu_reset,
&tu_boot, &tu_attach, &tu_detach };
&tu_boot, &tu_attach, &tu_detach,
&tu_dib, DEV_UBUS };
/* I/O dispatch routine, I/O addresses 17772440 - 17772472 */
@@ -560,7 +571,7 @@ case FNC_FCLR: /* drive clear */
tutc = tutc & ~TC_FCS; /* clear fc status */
tufs = tufs & ~(FS_SAT | FS_SSC | FS_ID | FS_TMK | FS_ERR);
sim_cancel (uptr); /* reset drive */
uptr -> USTAT = 0;
uptr->USTAT = 0;
case FNC_NOP:
tucs1 = tucs1 & ~CS1_GO; /* no operation */
return;
@@ -572,19 +583,19 @@ case FNC_RIP: /* read-in preset */
return;
case FNC_UNLOAD: /* unload */
if ((uptr -> flags & UNIT_ATT) == 0) { /* unattached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* unattached? */
tuer = tuer | ER_UNS;
break; }
detach_unit (uptr);
uptr -> USTAT = FS_REW;
uptr->USTAT = FS_REW;
sim_activate (uptr, tu_time);
tucs1 = tucs1 & ~CS1_GO;
return;
case FNC_REWIND:
if ((uptr -> flags & UNIT_ATT) == 0) { /* unattached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* unattached? */
tuer = tuer | ER_UNS;
break; }
uptr -> USTAT = FS_PIP | FS_REW;
uptr->USTAT = FS_PIP | FS_REW;
sim_activate (uptr, tu_time);
tucs1 = tucs1 & ~CS1_GO;
return;
@@ -592,13 +603,13 @@ case FNC_REWIND:
case FNC_SPACEF:
space_test = FS_EOT;
case FNC_SPACER:
if ((uptr -> flags & UNIT_ATT) == 0) { /* unattached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* unattached? */
tuer = tuer | ER_UNS;
break; }
if ((tufs & space_test) || ((tutc & TC_FCS) == 0)) {
tuer = tuer | ER_NXF;
break; }
uptr -> USTAT = FS_PIP;
uptr->USTAT = FS_PIP;
goto GO_XFER;
case FNC_WCHKR: /* wchk = read */
@@ -615,13 +626,13 @@ case FNC_WRITE: /* write */
break; }
case FNC_WREOF: /* write tape mark */
case FNC_ERASE: /* erase */
if (uptr -> flags & UNIT_WPRT) { /* write locked? */
if (uptr->flags & UNIT_WPRT) { /* write locked? */
tuer = tuer | ER_NXF;
break; }
case FNC_WCHKF: /* wchk = read */
case FNC_READF: /* read */
DATA_XFER:
if ((uptr -> flags & UNIT_ATT) == 0) { /* unattached? */
if ((uptr->flags & UNIT_ATT) == 0) { /* unattached? */
tuer = tuer | ER_UNS;
break; }
if (fmt_test[GET_FMT (tutc)] == 0) { /* invalid format? */
@@ -630,11 +641,11 @@ DATA_XFER:
if (den_test[den] == 0) { /* invalid density? */
tuer = tuer | ER_NXF;
break; }
if (uptr -> UDENS == UD_UNK) uptr -> UDENS = den; /* set dens */
/* else if (uptr -> UDENS != den) { /* density mismatch? */
if (uptr->UDENS == UD_UNK) uptr->UDENS = den; /* set dens */
/* else if (uptr->UDENS != den) { /* density mismatch? */
/* tuer = tuer | ER_NXF;
/* break; } */
uptr -> USTAT = 0;
uptr->USTAT = 0;
tucs1 = tucs1 & ~CS1_DONE; /* clear done */
GO_XFER:
tucs2 = tucs2 & ~CS2_ERR; /* clear errors */
@@ -662,17 +673,19 @@ return;
t_stat tu_svc (UNIT *uptr)
{
int32 f, fmt, i, j, k, err, wc10, ba10;
int32 f, fmt, i, j, k, err, wc10, ba10, pnu;
int32 ba, fc, wc, drv, mpa10, vpn;
d10 val, v[4];
t_mtrlnt tbc;
static t_mtrlnt bceof = { 0 };
t_mtrlnt abc, tbc;
static t_mtrlnt bceof = { MTR_TMK };
static uint8 xbuf[XBUFLNT + 4];
drv = uptr - tu_dev.units;
if (uptr -> USTAT & FS_REW) { /* rewind or unload? */
uptr -> pos = 0; /* update position */
uptr -> USTAT = 0; /* clear status */
drv = uptr - tu_dev.units; /* get drive # */
pnu = MT_TST_PNU (uptr); /* get pos not upd */
MT_CLR_PNU (uptr); /* and clear */
if (uptr->USTAT & FS_REW) { /* rewind or unload? */
uptr->pos = 0; /* update position */
uptr->USTAT = 0; /* clear status */
tufs = tufs | FS_ATA | FS_SSC;
update_tucs (CS1_SC, drv); /* update status */
return SCPE_OK; }
@@ -685,55 +698,42 @@ fc = 0200000 - tufc; /* get frame count */
wc10 = wc >> 1; /* 10 word count */
ba10 = ba >> 2; /* 10 word addr */
err = 0;
uptr -> USTAT = 0; /* clear status */
uptr->USTAT = 0; /* clear status */
switch (f) { /* case on function */
/* Unit service - non-data transfer commands - set ATA when done */
case FNC_SPACEF: /* space forward */
do { tufc = (tufc + 1) & 0177777; /* incr fc */
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) || /* error or eof? */
feof (uptr -> fileref)) {
uptr -> USTAT = FS_EOT;
break; }
if (tbc == 0) { /* zero bc? */
tufs = tufs | FS_TMK;
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
break; }
uptr -> pos = uptr -> pos + ((MTRL (tbc) + 1) & ~1) +
if (tu_rdlntf (uptr, &tbc, &err)) break;/* read rec lnt, err? */
uptr->pos = uptr->pos + ((MTRL (tbc) + 1) & ~1) +
(2 * sizeof (t_mtrlnt)); }
while (tufc != 0);
if (tufc) tuer = tuer | ER_FCE;
else tutc = tutc & ~TC_FCS;
tufs = tufs | FS_ATA;
break;
case FNC_SPACER: /* space reverse */
do { tufc = (tufc + 1) & 0177777; /* incr wc */
fseek (uptr -> fileref, uptr -> pos - sizeof (t_mtrlnt),
SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) || /* error or eof? */
feof (uptr -> fileref)) {
uptr -> pos = 0;
break; }
if (tbc == 0) { /* start of prv file? */
tufs = tufs | FS_TMK;
uptr -> pos = uptr -> pos - sizeof (t_mtrlnt);
break; }
uptr -> pos = uptr -> pos - ((MTRL (tbc) + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); }
while ((tufc != 0) && (uptr -> pos));
if (pnu) pnu = 0; /* pos not upd? */
else { if (tu_rdlntr (uptr, &tbc, &err)) break;
uptr->pos = uptr->pos - ((MTRL (tbc) + 1) & ~1) -
(2 * sizeof (t_mtrlnt)); } }
while (tufc != 0);
if (tufc) tuer = tuer | ER_FCE;
else tutc = tutc & ~TC_FCS;
tufs = tufs | FS_ATA;
break;
case FNC_WREOF:
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxwrite (&bceof, sizeof (t_mtrlnt), 1, uptr -> fileref);
err = ferror (uptr -> fileref);
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt); /* update position */
fseek (uptr->fileref, uptr->pos, SEEK_SET);
fxwrite (&bceof, sizeof (t_mtrlnt), 1, uptr->fileref);
tufs = tufs | FS_ATA;
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr);
else uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* update position */
break;
case FNC_ERASE:
tufs = tufs | FS_ATA;
break;
@@ -754,29 +754,23 @@ case FNC_ERASE:
case FNC_READF: /* read */
case FNC_WCHKF: /* wcheck = read */
tufc = 0; /* clear frame count */
if ((uptr -> UDENS == TC_1600) && (uptr -> pos == 0))
if ((uptr->UDENS == TC_1600) && (uptr->pos == 0))
tufs = tufs | FS_ID; /* PE BOT? ID burst */
TXFR (ba, wc, 0); /* validate transfer */
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) || /* error or eof? */
(feof (uptr -> fileref))) {
uptr -> USTAT = FS_EOT;
break; }
if (tu_rdlntf (uptr, &tbc, &err)) break; /* read rec lnt, err? */
fseek (uptr->fileref, uptr->pos, SEEK_SET);
if (MTRF (tbc)) { /* bad record? */
tuer = tuer | ER_CRC; /* set error flag */
uptr -> pos = uptr -> pos + ((MTRL (tbc) + 1) & ~1) +
uptr->pos = uptr->pos + ((MTRL (tbc) + 1) & ~1) +
(2 * sizeof (t_mtrlnt));
break; }
if (tbc == 0) { /* tape mark? */
tufs = tufs | FS_TMK;
uptr -> pos = uptr -> pos + sizeof (t_mtrlnt);
break; }
if (tbc > XBUFLNT) return SCPE_MTRLNT; /* bad rec length? */
i = fxread (xbuf, sizeof (int8), tbc, uptr -> fileref);
for ( ; i < tbc + 4; i++) xbuf[i] = 0; /* fill/pad with 0's */
err = ferror (uptr -> fileref);
for (i = j = 0; (i < wc10) && (j < tbc); i++) {
abc = fxread (xbuf, sizeof (int8), tbc, uptr->fileref);
if (err = ferror (uptr->fileref)) { /* error? */
MT_SET_PNU (uptr); /* pos not upd */
break; }
for ( ; abc < tbc + 4; abc++) xbuf[abc] = 0; /* fill/pad with 0's */
for (i = j = 0; (i < wc10) && (j < ((int32) tbc)); i++) {
if ((i == 0) || NEWPAGE (ba10 + i, 0)) { /* map new page */
MAPM (ba10 + i, mpa10, 0); }
for (k = 0; k < 4; k++) v[k] = xbuf[j++];
@@ -784,15 +778,15 @@ case FNC_WCHKF: /* wcheck = read */
if (fmt == TC_10C) val = val | ((d10) xbuf[j++] & 017);
if (f == FNC_READF) M[mpa10] = val;
mpa10 = mpa10 + 1; } /* end for */
uptr -> pos = uptr -> pos + ((tbc + 1) & ~1) + (2 * sizeof (t_mtrlnt));
uptr->pos = uptr->pos + ((tbc + 1) & ~1) + (2 * sizeof (t_mtrlnt));
tufc = tbc & 0177777;
tuwc = (tuwc + (i << 1)) & 0177777;
ba = ba + (i << 2);
break;
case FNC_WRITE: /* write */
TXFR (ba, wc, 0); /* validate transfer */
fseek (uptr -> fileref, uptr -> pos, SEEK_SET);
fseek (uptr->fileref, uptr->pos, SEEK_SET);
for (i = j = 0; (i < wc10) && (j < fc); i++) {
if ((i == 0) || NEWPAGE (ba10 + i, 0)) { /* map new page */
MAPM (ba10 + i, mpa10, 0); }
@@ -804,41 +798,34 @@ case FNC_WRITE: /* write */
if (fmt == TC_10C) xbuf[j++] = (uint8) (val & 017);
mpa10 = mpa10 + 1; } /* end for */
if (j < fc) fc = j; /* short record? */
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr -> fileref);
fxwrite (xbuf, sizeof (int8), (fc + 1) & ~1, uptr -> fileref);
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr -> fileref);
err = ferror (uptr -> fileref);
uptr -> pos = uptr -> pos + ((fc + 1) & ~1) + (2 * sizeof (t_mtrlnt));
tufc = (tufc + fc) & 0177777;
if (tufc == 0) tutc = tutc & ~TC_FCS;
tuwc = (tuwc + (i << 1)) & 0177777;
ba = ba + (i << 2);
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr->fileref);
fxwrite (xbuf, sizeof (int8), (fc + 1) & ~1, uptr->fileref);
fxwrite (&fc, sizeof (t_mtrlnt), 1, uptr->fileref);
if (err = ferror (uptr->fileref)) MT_SET_PNU (uptr);
else { uptr->pos = uptr->pos + ((fc + 1) & ~1) +
(2 * sizeof (t_mtrlnt));
tufc = (tufc + fc) & 0177777;
if (tufc == 0) tutc = tutc & ~TC_FCS;
tuwc = (tuwc + (i << 1)) & 0177777;
ba = ba + (i << 2); }
break;
case FNC_READR: /* read reverse */
case FNC_WCHKR: /* wcheck = read */
tufc = 0; /* clear frame count */
TXFR (ba, wc, 1); /* validate xfer rev */
fseek (uptr -> fileref, uptr -> pos - sizeof (t_mtrlnt), SEEK_SET);
fxread (&tbc, sizeof (t_mtrlnt), 1, uptr -> fileref);
if ((err = ferror (uptr -> fileref)) || /* error or eof? */
(feof (uptr -> fileref))) {
uptr -> USTAT = FS_EOT;
break; }
if (tu_rdlntr (uptr, &tbc, &err)) break; /* read rec lnt, err? */
if (MTRF (tbc)) { /* bad record? */
tuer = tuer | ER_CRC; /* set error flag */
uptr -> pos = uptr -> pos - ((MTRL (tbc) + 1) & ~1) -
uptr->pos = uptr->pos - ((MTRL (tbc) + 1) & ~1) -
(2 * sizeof (t_mtrlnt));
break; }
if (tbc == 0) { /* tape mark? */
tufs = tufs | FS_TMK;
uptr -> pos = uptr -> pos - sizeof (t_mtrlnt);
break; }
if (tbc > XBUFLNT) return SCPE_MTRLNT; /* bad rec length? */
fseek (uptr -> fileref, uptr -> pos - sizeof (t_mtrlnt)
fseek (uptr->fileref, uptr->pos - sizeof (t_mtrlnt)
- ((tbc + 1) & ~1), SEEK_SET);
fxread (xbuf + 4, sizeof (int8), tbc, uptr -> fileref);
fxread (xbuf + 4, sizeof (int8), tbc, uptr->fileref);
for (i = 0; i < 4; i++) xbuf[i] = 0;
err = ferror (uptr->fileref); /* set err but finish */
for (i = 0, j = tbc + 4; (i < wc10) && (j >= 4); i++) {
if ((i == 0) || NEWPAGE (ba10 - i, PAG_M_OFF)) { /* map page */
MAPM (ba10 - i, mpa10, UMAP_RRV); }
@@ -847,23 +834,21 @@ case FNC_WCHKR: /* wcheck = read */
val = val | (v[0] << 4) | (v[1] << 12) | (v[2] << 20) | (v[3] << 28);
if (f == FNC_READR) M[mpa10] = val;
mpa10 = mpa10 - 1; } /* end for */
uptr -> pos = uptr -> pos - ((tbc + 1) & ~1) - (2 * sizeof (t_mtrlnt));
uptr->pos = uptr->pos - ((tbc + 1) & ~1) - (2 * sizeof (t_mtrlnt));
tufc = tbc & 0177777;
tuwc = (tuwc + (i << 1)) & 0177777;
ba = ba - (i << 2);
break; } /* end case */
/* Unit service, continued */
tucs1 = (tucs1 & ~CS1_UAE) | ((ba >> (16 - CS1_V_UAE)) & CS1_UAE);
tuba = ba & 0177777; /* update mem addr */
tucs1 = tucs1 & ~CS1_GO; /* clear go */
if (err != 0) { /* I/O error */
tuer = tuer | ER_CRC; /* flag error */
tuer = tuer | ER_VPE; /* flag error */
update_tucs (CS1_DONE | CS1_TRE, drv); /* set done, err */
perror ("TU I/O error");
clearerr (uptr -> fileref);
return IORETURN (tu_stopioe, SCPE_IOERR); }
clearerr (uptr->fileref);
return (tu_stopioe? SCPE_IOERR: SCPE_OK); }
update_tucs (CS1_DONE, drv);
return SCPE_OK;
}
@@ -910,6 +895,52 @@ tucs1 = tucs1 & ~CS1_IE; /* clear int enable */
tuiff = 0; /* clear CSTB INTR */
return VEC_TU; /* acknowledge */
}
/* Read record length forward - return T if error, EOM, or EOF */
t_bool tu_rdlntf (UNIT *uptr, t_mtrlnt *tbc, int32 *err)
{
fseek (uptr->fileref, uptr->pos, SEEK_SET); /* set tape pos */
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref); /* read rec lnt */
if (*err = ferror (uptr->fileref)) { /* error? */
tuer = tuer | ER_VPE; /* parity error */
MT_SET_PNU (uptr); /* pos not updated */
return TRUE; }
if (feof (uptr->fileref) || (*tbc == MTR_EOM)) { /* eof or eom? */
tuer = tuer | ER_OPI; /* incomplete */
MT_SET_PNU (uptr); /* pos not updated */
return TRUE; }
if (*tbc == MTR_TMK) { /* tape mark? */
tufs = tufs | FS_TMK;
uptr->pos = uptr->pos + sizeof (t_mtrlnt); /* spc over tmk */
return TRUE; }
return FALSE;
}
/* Read record length reverse - return T if error, EOM, or EOF */
t_bool tu_rdlntr (UNIT *uptr, t_mtrlnt *tbc, int32 *err)
{
if (uptr->pos < sizeof (t_mtrlnt)) return TRUE;
fseek (uptr->fileref, uptr->pos - sizeof (t_mtrlnt), SEEK_SET);
fxread (tbc, sizeof (t_mtrlnt), 1, uptr->fileref);
if (*err = ferror (uptr->fileref)) { /* error? */
tuer = tuer | ER_VPE; /* parity error */
return TRUE; }
if (feof (uptr->fileref)) { /* eof? */
tuer = tuer | ER_OPI; /* incomplete */
return TRUE; }
if (*tbc == MTR_EOM) { /* eom? */
tuer = tuer | ER_OPI; /* incomplete */
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* spc over eom */
return TRUE; }
if (*tbc == MTR_TMK) { /* tape mark? */
tufs = tufs | FS_TMK;
uptr->pos = uptr->pos - sizeof (t_mtrlnt); /* spc over tmk */
return TRUE; }
*tbc = MTRL (*tbc); /* ignore error flag */
return FALSE;
}
/* Reset routine */
@@ -927,8 +958,9 @@ tuiff = 0; /* clear CSTB INTR */
int_req = int_req & ~INT_TU; /* clear interrupt */
for (u = 0; u < TU_NUMDR; u++) { /* loop thru units */
uptr = tu_dev.units + u;
MT_CLR_PNU (uptr); /* clear pos flag */
sim_cancel (uptr); /* cancel activity */
uptr -> USTAT = 0; }
uptr->USTAT = 0; }
return SCPE_OK;
}
@@ -941,8 +973,9 @@ t_stat r;
r = attach_unit (uptr, cptr);
if (r != SCPE_OK) return r;
uptr -> USTAT = 0; /* clear unit status */
uptr -> UDENS = UD_UNK; /* unknown density */
MT_CLR_PNU (uptr);
uptr->USTAT = 0; /* clear unit status */
uptr->UDENS = UD_UNK; /* unknown density */
tufs = tufs | FS_ATA | FS_SSC; /* set attention */
if ((GET_FMTR (tucs2) == 0) && (GET_DRV (tutc) == drv)) /* selected drive? */
tufs = tufs | FS_SAT; /* set slave attn */
@@ -959,9 +992,10 @@ int32 drv = uptr - tu_dev.units;
if (sim_is_active (uptr)) { /* unit active? */
sim_cancel (uptr); /* cancel operation */
tuer = tuer | ER_UNS; /* set formatter error */
if ((uptr -> USTAT & FS_REW) == 0) /* data transfer? */
if ((uptr->USTAT & FS_REW) == 0) /* data transfer? */
tucs1 = tucs1 | CS1_DONE | CS1_TRE; } /* set done, err */
uptr -> USTAT = 0; /* clear status flags */
MT_CLR_PNU (uptr);
uptr->USTAT = 0; /* clear status flags */
tufs = tufs | FS_ATA | FS_SSC; /* set attention */
update_tucs (CS1_SC, drv); /* update status */
return detach_unit (uptr);
@@ -1055,7 +1089,7 @@ static const d10 boot_rom_its[] = {
0254200377052, /* halt */
0254017000000, /* jrst 0(17) ; return */
};
t_stat tu_boot (int32 unitno)
t_stat tu_boot (int32 unitno, DEVICE *dptr)
{
int32 i;
extern a10 saved_PC;